San 16 Banwol-Ri
Taean-Eup Hwasung-City
Kyungki Do, Korea
Tel.) 82 -31 -208 -6463
Fax.) 82 -31 -208 -6799
March. 2003
ELECTRONICS
1
1
1Gb
Gb 1.8V NAND Flash Errata
1.8V NAND Flash Errata
Description : Some of AC characteristics are not meeting the specification.
> AC characteristics : Refer to Table
Affected Products : K9F1G08Q0M-YCB0/YIB0, K9F1G16Q0M-YCB0/YIB0
K9K2G08Q0M-YCB0/YIB0, K9K2G16Q0M-YCB0/YIB0
Improvement schedule : The components targeted to meet the specification
is scheduled to be available by workweek 25 along
with the final specification values.
Sincerely,
chwoosun@sec.samsung.com
Product Planning & Application Eng.
Memory Division
Samsung Electronics Co.
Table
Parameters
Specification
Relaxed Condition
tWC
45
80
tWH
15
20
tWP
25
60
tRC
50
80
tREH
15
20
tRP
25
60
tREA
30
60
UNIT : ns
Workaround : Relax the relevant timing parameters according to the table.
tCEA
45
75
FLASH MEMORY
1SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Document Title
128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
Revision No
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Remark
Advance
History
1. Initial issue
1. Iol(R/B) of 1.8V is changed.
- min. value : 7mA --> 3mA
- Typ. value : 8mA --> 4mA
2. AC parameter is changed.
tRP(min.) : 30ns --> 25ns
3. A recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences as shown in Figure 17.
---> A recovery time of minimum 10µs is required before internal circuit gets
ready for any command sequences as shown in Figure 17.
1. ALE status fault in ’Random data out in a page’ timing diagram(page 19)
is fixed.
1. tAR1, tAR2 are merged to tAR.(Page11)
(Before revision) min. tAR1 = 10ns , min. tAR2 = 50ns
(After revision) min. tAR = 10ns
2. min. tCLR is changed from 50ns to 10ns.(Page11)
3. min. tREA is changed from 35ns to 30ns.(Page11)
4. min. tWC is changed from 50ns to 45ns.(Page11)
5. tRHZ is devided into tRHZ and tOH.(Page11)
- tRHZ : RE High to Output Hi-Z
- tOH : RE High to Output Hold
6. tCHZ is devided into tCHZ and tOH.(Page11)
- tCHZ : CE High to Output Hi-Z
- tOH : CE High to Output Hold
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 35)
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 36)
The min. Vcc value 1.8V devices is changed.
K9F1GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V
Pb-free Package is added.
K9F1G08U0M-FCB0,FIB0
K9F1G08Q0M-PCB0,PIB0
K9F1G08U0M-PCB0,PIB0
K9F1G16U0M-PCB0,PIB0
K9F1G16Q0M-PCB0,PIB0
Draft Date
July. 5. 2001
Nov. 5. 2001
Dec. 4. 2001
Apr. 25. 2002
Nov. 22.2002
Mar. 6.2003
Mar. 13.2003
FLASH MEMORY
2SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Document Title
128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
Revision No
0.7
0.8
RemarkHistory
Errata is added.(Front Page)-K9F1GXXQ0M
tWC tWP tWH tRC tREH tRP tREA tCEA
Specification 45 25 15 50 15 25 30 45
Relaxed value 80 60 20 60 80 60 60 75
1. The 3rd Byte ID after 90h ID read command is don’t cared.
The 5th Byte ID after 90h ID read command is deleted.
Draft Date
Mar.17. 2003
Apr. 9. 2003
FLASH MEMORY
3SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
GENERAL DESCRIPTION
FEATURES
• Voltage Supply
-1.8V device(K9F1GXXQ0M): 1.70V~1.95V
-3.3V device(K9F1GXXU0M): 2.7 V ~3.6 V
• Organization
- Memory Cell Array
-X8 device(K9F1G08X0M) : (128M + 4,096K)bit x 8bit
-X16 device(K9F1G16X0M) : (64M + 2,048K)bit x 16bit
- Data Register
-X8 device(K9F1G08X0M): (2K + 64)bit x8bit
-X16 device(K9F1G16X0M): (1K + 32)bit x16bit
- Cache Register
-X8 device(K9F1G08X0M): (2K + 64)bit x8bit
-X16 device(K9F1G16X0M): (1K + 32)bit x16bit
• Automatic Program and Erase
- Page Program
-X8 device(K9F1G08X0M): (2K + 64)Byte
-X16 device(K9F1G16X0M): (1K + 32)Word
- Block Erase
-X8 device(K9F1G08X0M): (128K + 4K)Byte
-X16 device(K9F1G16X0M): (64K + 2K)Word
• Page Read Operation
- Page Size
- X8 device(K9F1G08X0M): 2K-Byte
- X16 device(K9F1G16X0M) : 1K-Word
- Random Read : 25µs(Max.)
- Serial Access : 50ns(Min.)
128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
• Fast Write Cycle Time
- Program time : 300µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Cache Program Operation for High Performance Program
• Power-On Auto-Read Operation
• Intelligent Copy-Back Operation
• Unique ID for Copyright Protection
• Package :
- K9F1GXXX0M-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F1G08U0M-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F1GXXX0M-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9F1G08U0M-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F1G08U0M-V,F(WSOPI ) is the same device as
K9F1G08U0M-Y,P(TSOP1) except package type.
Offered in 128Mx8bit or 64Mx16bit, the K9F1GXXX0M is 1G bit with spare 32M bit capacity. Its NAND cell provides the most cost-
effective solution for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112-
byte(X8 device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device)
or 64K-word(X16 device) block. Data in the data page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for
address and data input/output as well as command input. The on-chip write controller automates all program and erase functions
including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take
advantage of the K9F1GXXX0M′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with
real time mapping-out algorithm. The K9F1GXXX0M is an optimum solution for large nonvolatile storage applications such as solid
state file storage and other portable applications requiring non-volatility.
PRODUCT LIST
Part Number Vcc Range Organization PKG Type
K9F1G08Q0M-Y,P 1.70 ~ 1.95V X8
TSOP1
K9F1G16Q0M-Y,P X16
K9F1G08U0M-Y,P 2.7 ~ 3.6V X8
K9F1G16U0M-Y,P X16
K9F1G08U0M-V,F X8 WSOP1
FLASH MEMORY
4SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
PIN CONFIGURATION (TSOP1)
K9F1GXXX0M-YCB0,PCB0/YIB0,PIB0
X8X16 X16X8
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F Unit :mm/Inch
0.787±0.008
20.00±0.20
#1
#24
0.20+0.07
-0.03
0.008+0.003
-0.001
0.50
0.0197
#48
#25
0.488
12.40MAX
12.00
0.472
0.10
0.004 MAX
0.25
0.010
( )
0.039±0.002
1.00±0.05 0.002
0.05 MIN
0.047
1.20 MAX
0.45~0.75
0.018~0.030
0.724±0.004
18.40±0.10
0~8¡Æ
0.010
0.25 TYP
0.125+0.075
0.035
0.005+0.003
-0.001
0.50
0.020
( )
48-pin TSOP1
Standard Type
12mm x 20mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
PRE
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
PRE
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
FLASH MEMORY
5SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
PIN CONFIGURATION (WSOP1)
K9F1G08U0M-VCB0,FCB0/VIB0,FIB0
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F Unit :mm
15.40±0.10
#1
#24
0.20 +0.07
-0.03 0.16 +0.07
-0.03
0.50TYP
(0.50±0.06)
#48
#25
12.00±0.10
0.10+0.075
-0.035
0.58±0.04
0.70 MAX
(0.1Min)
17.00±0.20
0°~8°
0.45~0.75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
FLASH MEMORY
6SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
PIN DESCRIPTION
Pin Name Pin Function
I/O0 ~ I/O7
(K9F1G08X0M)
I/O0 ~ I/O15
(K9F1G16X0M)
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
CLE COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode.
RE READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
PRE POWER-ON READ ENABLE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when
PRE pin is tied to Vcc.
Vcc POWER
VCC is the power supply for device.
Vss GROUND
N.C NO CONNECTION
Lead is not internally connected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
FLASH MEMORY
7SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
2K Bytes 64 Bytes
Figure 1-1. K9F1G08X0M (X8) Functional Block Diagram
Figure 2-1. K9F1G08X0M (X8) Array Organization
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
1st Cycle A0A1A2A3A4A5A6A7
2nd Cycle A8A9A10 A11 *L *L *L *L
3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19
4th Cycle A20 A21 A22 A23 A24 A25 A26 A27
VCC
X-Buffers
Command
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator Global Buffers Output
Driver
VSS
A12 - A27
A0 - A11
Command
CE
RE
WE
CLE WP
I/0 0
I/0 7
VCC
VSS
64K Pages
(=1,024 Blocks)
2K Bytes
8 bit
64 Bytes
1 Block = 64 Pages
(128K + 4k) Byte
I/O 0 ~ I/O 7
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 1024 Blocks
= 1056 Mbits
Row Address
Page Register
ALE PRE
1024M + 32M Bit
NAND Flash
ARRAY
(1024 + 32)Byte x 65536
Y-Gating
Cache Register
Row Address
Column Address
Column Address
Data Register & S/A
FLASH MEMORY
8SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
1K Words 32 Words
Figure 1-2. K9F1G16X0M (X16) Functional Block Diagram
Figure 2-2. K9F1G16X0M (X16) Array Organization
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O8 ~ 15
1st Cycle A0A1A2A3A4A5A6A7*L
2nd Cycle A8A9A10 *L *L *L *L *L *L
3rd Cycle A11 A12 A13 A14 A15 A16 A17 A18 *L
4th Cycle A19 A20 A21 A22 A23 A24 A25 A26 *L
VCC
X-Buffers
Command
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator Global Buffers Output
Driver
VSS
A11 - A26
A0 - A10
Command
CE
RE
WE
CLE WP
I/0 0
I/0 15
VCC
VSS
64K Pages
(=1,024 Blocks)
1K Words
16 bit
32 Words
1 Block = 64 Pages
(64K + 2k) Word
I/O 0 ~ I/O 15
1 Page = (1K + 32)Words
1 Block = (1K + 32)Word x 64 Pages
= (64K + 2K) Words
1 Device = (1K+32)Word x 64Pages x 1024 Blocks
= 1056 Mbits
Row Address
Page Register
ALE PRE
1024M + 32M Bit
NAND Flash
ARRAY
(512 + 64)Word x 65536
Y-Gating
Cache Register
Row Address
Column Address
Column Address
Data Register & S/A
FLASH MEMORY
9SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Product Introduction
The K9F1GXXX0M is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8(X8 device) or
1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or
1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056-
word(X16 device) cache register are serially connected to each other. Those serially connected registers are connected to memory
cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program opera-
tions. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in
a different page. A block consists of the 64 pages formed by two NAND structures, totaling 33792 NAND structures of 32 cells. The
program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 1024 separately erasable 128K-byte(X8 device) or 64K-word(X16 device) blocks. It indicates that the bit by bit
erase operation is prohibited on the K9F1GXXX0M.
The K9F1GXXX0M has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). This scheme dramatically reduces pin
counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and
data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch
Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com-
mands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other
commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execu-
tion. The 128M byte(X8 device) or 64M word(X16 device) physical space requires 28(X8) or 27(X16) addresses, thereby requiring
four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need
the same four address cycles following the required command input. In Block Erase operation, however, only the two row address
cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the spe-
cific commands of the K9F1GXXX0M.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers
are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
The device embodies power-on auto-read feature which enables serial access of data of the 1st page without command and address
input after power-on.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Command not specified in command sets table is not permitted to be entered to the device, which can raise erroneous operation.
Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy
Read 00h 30h
Read for Copy Back 00h 35h
Read ID 90h -
Reset FFh -O
Page Program 80h 10h
Cache Program 80h 15h
Copy-Back Program 85h 10h
Block Erase 60h D0h
Random Data Input*85h -
Random Data Output*05h E0h
Read Status 70h O
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
FLASH MEMORY
10 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Symbol Test Conditions K9F1GXXQ0M(1.8V) K9F1GXXU0M(3.3V) Unit
Min Typ Max Min Typ Max
Operat-
ing
Current
Page Read with
Serial Access ICC1tRC=50ns, CE=VIL
IOUT=0mA -5 15 -10 20
mA
Program ICC2- - 5 15 -10 20
Erase ICC3- - 5 15 -10 20
Stand-by Current(TTL) ISB1CE=VIH, WP=PRE=0V/VCC - - 1- - 1
Stand-by Current(CMOS) ISB2CE=VCC-0.2,
WP=PRE=0V/VCC -20 100 -20 100
µA
Input Leakage Current ILI VIN=0 to Vcc(max) - - ±20 - - ±20
Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±20 - - ±20
Input High Voltage VIH -VCC-0.4 -VCC+
0.3 2.0 -VCC+0.3
V
Input Low Voltage, All inputs VIL --0.3 -0.4 -0.3 -0.8
Output High Voltage Level VOH K9F1GXXQ0M :IOH=-100µA
K9F1GXXU0M :IOH=-400µAVcc-0.1 - - 2.4 - -
Output Low Voltage Level VOL K9F1GXXQ0M :IOL=100uA
K9F1GXXU0M :IOL=2.1mA - - 0.1 - - 0.4
Output Low Current(R/B)IOL(R/B)K9F1GXXQ0M :VOL=0.1V
K9F1GXXU0M :VOL=0.4V 3 4 -8 10 -mA
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F1GXXX0M-XCB0 :TA=0 to 70°C, K9F1GXXX0M-XIB0:TA=-40 to 85°C)
Parameter Symbol K9F1GXXQ0M(1.8V) K9F1GXXU0M(3.3V) Unit
Min Typ. Max Min Typ. Max
Supply Voltage VCC 1.70 1.8 1.95 2.7 3.3 3.6 V
Supply Voltage VSS 0 0 0 0 0 0 V
ABSOLUTE MAXIMUM RATINGS
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
K9F1GXXQ0M(1.8V) K9F1GXXU0M(3.3V)
Voltage on any pin relative to VSS VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6 V
VCC -0.2 to + 2.45 -0.6 to + 4.6
Temperature Under Bias K9F1GXXX0M-XCB0 TBIAS -10 to +125 °C
K9F1GXXX0M-XIB0 -40 to +125
Storage Temperature K9F1GXXX0M-XCB0 TSTG -65 to +150 °C
K9F1GXXX0M-XIB0
Short Circuit Current Ios 5mA
FLASH MEMORY
11 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item Symbol Test Condition Min Max Unit
Input/Output Capacitance CI/O VIL=0V -10 pF
Input Capacitance CIN VIN=0V -10 pF
VALID BLOCK
NOTE :
1. The K9F1GXXX0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase
or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction.
Parameter Symbol Min Typ. Max Unit
Valid Block Number NVB 1004 -1024 Blocks
AC TEST CONDITION
(K9F1GXXX0M-XCB0 :TA=0 to 70°C, K9F1GXXX0M-XIB0:TA=-40 to 85°C
K9F1GXXQ0M : Vcc=1.70V~1.95V, K9F1GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)
Parameter K9F1GXXQ0M K9F1GXXU0M
Input Pulse Levels 0V to Vcc 0.4V to 2.4V
Input Rise and Fall Times 5ns 5ns
Input and Output Timing Levels Vcc/2 1.5V
K9F1GXXQ0M:Output Load (Vcc:1.8V +/-10%)
K9F1GXXU0M:Output Load (Vcc:3.0V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
K9F1GXXU0M:Output Load (Vcc:3.3V +/-10%) -1 TTL GATE and CL=100pF
Program / Erase Characteristics
NOTE : 1. Max. time of tCBSY depends on timing between internal program completion and data in
Parameter Symbol Min Typ Max Unit
Program Time tPROG -300 700 µs
Dummy Busy Time for Cache Program tCBSY 3 700 µs
Number of Partial Program Cycles
in the Same Page Main Array Nop - - 4cycles
Spare Array - - 4cycles
Block Erase Time tBERS -2 3 ms
MODE SELECTION
NOTE : 1. X can be VIL or VIH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
CLE ALE CE WE RE WP PRE Mode
HL L HX X Read Mode Command Input
LHLHX X Address Input(4clock)
HL L H H XWrite Mode Command Input
LHLH H X Address Input(4clock)
LLL H H X Data Input
LLLHX X Data Output
X X X X HX X During Read(Busy)
X X X X X HX During Program(Busy)
X X X X X HX During Erase(Busy)
XX(1) X X X LX Write Protect
X X HX X 0V/VCC(2) 0V/VCC(2) Stand-by
FLASH MEMORY
12 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
AC Characteristics for Operation
NOTE :
1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
Parameter Symbol Min Max Unit
Data Transfer from Cell to Register tR-25 µs
ALE to RE Delay tAR 10 -ns
CLE to RE Delay tCLR 10 -ns
Ready to RE Low tRR 20 -ns
RE Pulse Width tRP 25 -ns
WE High to Busy tWB -100 ns
Read Cycle Time tRC 50 -ns
RE Access Time tREA -30 ns
CE Access Time tCEA -45 ns
RE High to Output Hi-Z tRHZ -30 ns
CE High to Output Hi-Z tCHZ -20 ns
RE or CE High to Output hold tOH 15 -ns
RE High Hold Time tREH 15 -ns
Output Hi-Z to RE Low tIR 0-ns
WE High to RE Low tWHR 60 -ns
Device Resetting Time(Read/Program/Erase) tRST -5/10/500(1) µs
AC Timing Characteristics for Command / Address / Data Input
NOTE :
1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
Parameter Symbol Min Max Unit
CLE setup Time tCLS 0-ns
CLE Hold Time tCLH 10 -ns
CE setup Time tCS 0-ns
CE Hold Time tCH 10 -ns
WE Pulse Width tWP 25 (1) -ns
ALE setup Time tALS 0-ns
ALE Hold Time tALH 10 -ns
Data setup Time tDS 20 -ns
Data Hold Time tDH 10 -ns
Write Cycle Time tWC 45 -ns
WE High Hold Time tWH 15 -ns
FLASH MEMORY
13 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
NAND Flash Technical Notes
Identifying Invalid Block(s)
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-
anteed to be a valid block, does not require Error Correction.
All device locations are erased(FFh for X8, FFFFh for X16) except locations where the invalid block(s) information is written prior to
shipping. The invalid block(s) status is defined by the 1st byte(X8 device) or 1st word(X16 device) in the spare area. Samsung
makes sure that either the 1st or 2nd page of every invalid block has non-FFh(X8) or non-FFFFh(X16) data at the column address of
2048(X8 device) or 1024(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover
the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original
invalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of
the original invalid block information is prohibited.
*Check "FFh( or FFFFh)" at the column address
Figure 3. Flow chart to create invalid block table.
Start
Set Block Address = 0
Check "FFh
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update) No
Invalid Block(s) Table of the 1st and 2nd page in the block
2048(X8 device) or 1024(X16 device)
or FFFFh" ?
FLASH MEMORY
14 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
NAND Flash Technical Notes (Continued)
Program Flow Chart
Start
I/O 6 = 1 ?
Write 00h
I/O 0 = 0 ?
No
*
If ECC is used, this verification
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
Write Address
Wait for tR Time
Verify Data Fail
Program Completed
or R/B = 1 ?
Program Error
Yes
No
Yes
*
Program Error
Pass
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
operation is not needed.
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block.To improve the efficiency of mem-
ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Detection and Countermeasure sequence
Write
Erase Failure Status Read after Erase --> Block Replacement
Program Failure Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Read Single Bit Failure Verify ECC -> ECC Correction
ECC : Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Write 30h
FLASH MEMORY
15 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Erase Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 60h
Write Block Address
Write D0h
Read Status Register
or R/B = 1 ?
Erase Error
Yes
No
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Erase Completed
Yes
Read Flow Chart
Start
Verify ECC
No
Write 00h
Write Address
Read Data
ECC Generation
Reclaim the Error
Page Read Completed
Yes
NAND Flash Technical Notes (Continued)
Write 30h
Block Replacement
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
Buffer memory of the controller.
1st Block A
Block B
(n-1)th
nth
(page)
1
2
{
∼
1st
(n-1)th
nth
(page)
{
∼
an error occurs.
FLASH MEMORY
16 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal
2112byte(X8 device) or 1056word(X16 device) data registers are utilized as separate buffers for this operation and the system
design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activat-
ing CE during the data-loading and serial access would provide significant savings in power consumption.
Figure 4. Program Operation with CE don’t-care.
CE
WE tWP
tCH
tCS
Address(4Cycles)80h Data Input
CE
CLE
ALE
WE
Data Input
CE don’t-care
≈
≈
10h
Address(4Cycle)00h
CE
CLE
ALE
WE
Data Output(serial access)
CE don’t-care
≈
R/BtR
RE
tCEA
out
tREA
CE
RE
I/O0~7
Figure 5. Read Operation with CE don’t-care.
30h
I/Ox
I/Ox
FLASH MEMORY
17 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
K9F1G16X0M : I/O8~15 must be set to "0"
K9F1G16X0M : I/O8~15 must be set to "0"
* Command Latch Cycle
CE
WE
CLE
ALE
Command
* Address Latch Cycle
tCLS
tCS
tCLH
tCH
tWP
tALS tALH
tDS tDH
CE
WE
CLE
ALE
Col. Add1
tCLS
tCS tWC
tWP
tALS
tDS tDH
tALH tALS
tWH
tWC
tWP
tDS tDH
tALH tALS
tWH
tWC
tWP
tDS tDH
tALH tALS
tWH tALH
tDS tDH
tWP
NOTE
Device I/O DATA ADDRESS
I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2
K9F1G08X0B(X8 device) I/O 0 ~ I/O 7 ~2112byte A0~A7 A8~A11 A12~A19 A20~A27
K9F1G16X0B(X16 device) I/O 0 ~ I/O 15 ~1056word A0~A7 A8~A10 A11~A18 A19~A26
I/Ox
I/Ox Col. Add2 Row Add1 Row Add2
FLASH MEMORY
18 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
* Input Data Latch Cycle
CE
CLE
WE
DIN 0 DIN 1 DIN final*
ALE tALS
tCLH
tWC
tCH
tDS tDH tDS tDH tDS tDH
tWP
tWH
tWP tWP
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
RE
CE
R/B
Dout Dout Dout
tRC
tREA
tRR
tOH
tREA
tREH tREA tOH
tRHZ*
≈
≈
≈
≈≈≈≈
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
tCEA
I/Ox
I/Ox
≈
≈
≈
NOTES : DIN final means 2112(X8) or 1056(X16)
tCHZ*
tRHZ*
tRP
FLASH MEMORY
19 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
* Status Read Cycle
CE
WE
CLE
RE
70h Status Output
tCLR
tCLH
tCS
tWP tCH
tDS tDH tREA
tIR* tOH
tOH
tWHR
tCEA
tCLS
K9F1G16X0M : I/O8~15 must be set to "0"
I/Ox
tCHZ*
tRHZ*
FLASH MEMORY
20 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Read Operation(Intercepted by CE)
CE
CLE
R/B
WE
ALE
RE
Busy
00h Dout N Dout N+1 Dout N+2
Row Address
Column Address
tWB tAR tCHZ
tR
tRR
tRC
30h
Read Operation
CE
CLE
R/B
WE
ALE
RE
Busy
00h Col. Add1 Col. Add2 Row Add1 Dout N Dout N+1
Column Address Row Address
tWB tAR
tRtRC tRHZ
tRR
Dout M
tWC
≈≈ ≈
Row Add2 30h
tCLR
I/Ox
I/Ox Col. Add1 Col. Add2 Row Add1 Row Add2
tOH
tOH
FLASH MEMORY
21 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
tCLR
Random Data Output In a Page
CE
CLE
R/B
WE
ALE
RE
Busy
00h Dout NDout N+1
Row Address
Column Address
tWBtAR
tR
tRR
tRC
30h 05h
Column Address
Dout MDout M+1
E0h
I/Ox
Col. Add1 Col. Add2 Row Add1 Row Add2 Col Add1 Col Add2
tWHR
tREA
FLASH MEMORY
22 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
X8 device : m = 2112byte
X16 device : m = 1056word
Page Program Operation
CE
CLE
R/B
WE
ALE
RE
80h 70h I/O0
Din
NDin 10h
M
SerialData
Input Command Column Address Row Address 1 up to m Byte
Serial Input Program
Command Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
tPROG
tWB
tWC tWC tWC
≈≈
≈
≈
I/Ox
Co.l Add1 Col. Add2 Row Add1 Row Add2
FLASH MEMORY
23 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Page Program Operation with Random Data Input
CE
CLE
R/B
WE
ALE
RE
80h 70h I/O0
Din
NDin10h
M
Serial Data
Input Command Column Address Row Address Serial InputProgram
Command Read Status
Command
tPROG
tWB
tWCtWC
≈≈
≈
≈
85h
Random Data
Input Command Column Address
tWC
Din
JDin
K
Serial Input
≈≈ ≈
I/Ox
Col. Add1 Col. Add2 Row Add1 Row Add2 Col. Add1 Col. Add2
FLASH MEMORY
24 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Copy-Back Program Operation with Random Data Input
CE
CLE
R/B
WE
ALE
RE
00h 70h I/O0
85h
Column Address Row Address Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
tPROG
tWB
tWC
≈
Busy
tWB
tR
Busy
≈
10h
Copy-Back Data
Input Command
35h
Column Address Row Address
Data 1Data N
≈ ≈
I/Ox
Col Add1 Col Add2 Row Add1 Row Add2 Col Add1 Col Add2 Row Add1 Row Add2
FLASH MEMORY
25 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Cache Program Operation(available only within a block)
CE
CLE
R/B
WE
ALE
RE
80h Din
NDin15h
M
Serial Data
Input Command
Column Address Serial Input
Program
Max. 63 times repeatable
tCBSY
tWB
tWC
≈≈
≈
≈
Command
Last Page Input & Program
t
CBSY :
max. 700us
(Dummy)
Din
NDin10h
tPROG
tWB
≈
≈
≈
≈
I/O
80h
Col Add1,2 & Row Add1,2
R/B
Data
Address &
Data Input15h 80h Address &
Data Input15h 80h Address &
Data Input15h 80h Address &
Data Input10h
Ex.) Cache Program
tCBSY tCBSY tCBSY tPROG
Program Confirm
Command
(True)
80h 70h
70h
M
Row Address
I/Ox
I/Ox
Col Add1 Col Add2 Row Add1 Row Add2 Col Add1 Col Add2 Row Add1 Row Add2
FLASH MEMORY
26 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
BLOCK ERASE OPERATION
CE
CLE
R/B
WE
ALE
RE
60h
Erase Command Read Status
Command I/O0=1 Error in Erase
D0h 70h I/O 0
Busy
tWB tBERS
I/O0=0 Successful Erase
Row Address
tWC
≈
Auto Block Erase
Setup Command
I/Ox
Row Add1 Row Add2
FLASH MEMORY
27 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Read ID Operation
CE
CLE
WE
ALE
RE
90h
Read ID Command Maker Code Device Code
00h ECh Device
tREA
Address. 1cycle
XXh 4th cyc.*
I/Ox
tAR
Device Device Code*(2nd Cycle) 4th Cycle*
K9F1G08Q0M A1h 15h
K9F1G08U0M F1h 15h
K9F1G16Q0M B1h 55h
K9F1G16U0M C1h 55h
Code*
ID Defintition Table
90 ID : Access command = 90H
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
Maker Code
Device Code
Don’t care
Page Size, Block Size, Spare Size, Organization,Serial access minimum
FLASH MEMORY
28 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
4th ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Page Size
(w/o redundant area )
1KB
2KB
Reserved
Reserved
0 0
0 1
1 0
1 1
Blcok Size
(w/o redundant area )
64KB
128KB
256KB
Reserved
0 0
0 1
1 0
1 1
Redundant Area Size
( byte/512byte) 8
16 0
1
Organization x8
x16 0
1
Serial Access minimum
50ns
30ns
Reserved
Reserved
0
0
1
1
0
1
0
1
FLASH MEMORY
29 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the com-
mand register along with four address cycles. In two consecutive read operations, the second one doesn’t need 00h command,
which five address cycles and 30h command initiates that operation.Two types of operations are available : random read, serial page
read The random read mode is enabled when the page address is changed. The 2112 bytes(X8 device) or 1056 words(X16 device)
of data within the selected page are transferred to the data registers in less than 25µs(tR). The system controller can detect the com-
pletion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may
be read out in 50ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device out-
put the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
Address(4Cycle)00h
Col Add1,2 & Row Add1,2
Data Output(Serial Access)
Data Field Spare Field
CE
CLE
ALE
R/B
WE
RE
tR
30h
I/Ox
FLASH MEMORY
30 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Figure 7. Random Data Output In a Page
Address
00h Data Output
R/B
RE
tR
30h Address
05h E0h
4Cycles 2Cycles Data Output
Data Field Spare Field Data Field Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2112(X8 device) or words up to 1056(X16 device), in a single page program cycle. The number of consecutive partial
page programming operation within the same page without an intervening erase operation must not exceed 4 times for main
array(X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array(X8 device:1time/16byte ,X16 device:1time/
8word). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period
in which up to 2112bytes(X8 device) or 1056words(X16 device) of data may be loaded into the data register, followed by a non-vola-
tile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data
input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-
ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a
program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and
Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
80h
R/B
Address & Data Input I/O0Pass
Data
10h 70h
Fail
tPROG
I/Ox
I/Ox
Col Add1,2 & Row Add1,2
"0"
"1"
Col Add1,2 & Row Add1,2
FLASH MEMORY
31 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Cache Program
Figure 9. Random Data Input In a Page
80h
R/B
Address & Data Input I/O0Pass
10h 70h
Fail
tPROG
85h Address & Data Input
Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data regis-
ters, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while
data stored in data register are programmed into memory cell.
After writing the first set of data up to 2112byte(X8 device) or 1056word(X16 device) into the selected cache registers, Cache Pro-
gram command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time(tCBSY)
and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data
registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy sta-
tus bit(I/O 6). Pass/fail status of only the previouse page is available upon the return to Ready state. When the next set of data is
inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming
of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer
of data from cache registers. The status bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal pro-
gramming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence
must be progammed with actual Page Program command (10h). If the Cache Program command (15h) is used instead, status bit (I/
O5) must be polled to find out when the last programming is actually finished before starting other operations such as read. Pass/fail
status is available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit changing to "1", and
later I/O 0 with the status of current page upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/
O 1 may be read together when I/O 0 is checked.
Figure 10. Cache Program(available only within a block)
80h
R/B
80h Address &
Data Input 15h 80h Address &
Data Input 15h 80h Address &
Data Input 10h
tCBSY tCBSY tCBSY tPROG
70h
Address &
Data Input* 15h
80h
R/B
70h
tCBSY
Address &
Data Input 15h Status
output 80h 70h
tCBSY
Address &
Data Input 15h Status
output 80h
tCBSY
Address &
Data Input 15h
80h
tCBSY
Address &
Data Input 15h
70h
Status
output
70h Status
output
Status
output
Check I/O5 for internal ready/busy
Check I/O0,1 for pass/fail
Check I/O1 for pass/fail
I/Ox
I/Ox
Col Add1,2 & Row Add1,2 Col Add1,2
Data Data
Col Add1,2 & Row Add1,2 Col Add1,2 & Row Add1,2 Col Add1,2 & Row Add1,2
Data Data Data Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
"0"
"1"
FLASH MEMORY
32 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Copy-Back Program
Figure 11. Page Copy-Back program Operation
00h
R/B
Add.(4Cycles) I/O0Pass
85h 70h
Fail
tPROG
Add.(4Cycles)
tR
Source Address Destination Address
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-
efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-
ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves
the whole 2112byte(X8 device) or 1056word(X16 device) data into the internal data buffer. As soon as the device returns to Ready
state, Page-Copy Data-input command (85h) with the address cycles of destination page followed may be written. The Program
Confirm command (10h) is required to actually begin the programming operation. Data input cycle for modifying a portion or multiple
distant portions of the source page is allowed as shown in Figure 12. "When there is a program-failure at Copy-Back operation,
error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is
not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for
the use of Copy-Back operation."
35h
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if
the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after com-
pletion of the previous cycle, which can be expressed as the following formula.
tPROG= Program time for the last page+ Program time for the ( last -1 )th page
- (Program command cycle time + Last page data loading time)
10h
Figure 12. Page Copy-Back program Operation with Random Data Input
00h
R/B
Add.(4Cycles) 85h 70h
tPROG
Add.(4Cycles)
tR
Source Address Destination Address
Data
35h 10h
85h Data
Add.(2Cycles)
There is no limitation for the number of repetition.
I/Ox
I/Ox
Col. Add1,2 & Row Add1,2
Col. Add1,2 & Row Add1,2
Col. Add1,2 & Row Add1,2 Col. Add1,2 & Row Add1,2 Col Add1,2
FLASH MEMORY
33 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Figure 13. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com-
mand(60h). Only address A18 to A27(X8) or A17 to A26(X16) is valid while A12 to A17(X8) or A11 to A16(X16) is ignored. The Erase
Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
60h
Block Add. : A12 ~ A27 (X8)
R/B
Address Input(2Cycle) I/O0Pass
D0h 70h
Fail
tBERS
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
I/O No. Page Program Block Erase Cache Prorgam Read Definition
I/O 0 Pass/Fail Pass/Fail Pass/Fail(N) Not use Pass : "0" Fail : "1"
I/O 1 Not use Not use Pass/Fail(N-1) Not use Pass : "0" Fail : "1"
I/O 2 Not use Not use Not use Not use "0"
I/O 3 Not Use Not Use Not Use Not Use "0"
I/O 4 Not Use Not Use Not Use Not Use "0"
I/O 5 Ready/Busy Ready/Busy True Ready/Busy Ready/Busy Busy : "0" Ready : "1"
I/O 6 Ready/Busy Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"
I/O 7 Write Protect Write Protect Write Protect Write Protect Protected:"0" Not Protected:"1"
I/O 8~15
(X16 device
only) Not use Not use Not use Not use Don’t -care
Table2. Read Staus Register Definition
NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
I/Ox
or A11 ~ A26 (X16)
"0"
"1"
FLASH MEMORY
34 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Figure 14. Read ID Operation
CE
CLE
I/OX
ALE
RE
WE
90h 00h
Address. 1cycle Maker code Device code
tCEA
tAR
tREA
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, respectively. The
command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Device XXh 4th Cyc.*
ECh
Figure 15. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. The R/B pin
transitions to low for tRST after the Reset command is written. Refer to Figure 15 below.
FFh
I/OX
R/BtRST
tWHR
tCLR
Code*
Device Device Code*(2nd Cycle) 4th Cycle*
K9F1G08Q0M A1h 15h
K9F1G08U0M F1h 15h
K9F1G16Q0M B1h 55h
K9F1G16U0M C1h 55h
After Power-up After Reset
PRE status High Low Waiting for next command
Operation Mode First page data access is ready 00h command is latched
Table3. Device Status
FLASH MEMORY
35 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Power-On Auto-Read
The device is designed to offer automatic reading of the first page without command and address input sequence during power-on.
An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto-
page read function. Auto-page read function is enabled only when PRE pin is tied to Vcc. Serial access may be done after power-on
without latency. Power-On Auto Read mode is available only on 3.3V device(K9F1GXXU0M).
Figure 15. Power-On Auto-Read (3.3V device only)
VCC
CE
CLE
I/OX
ALE
RE
WE
1st
~ 1.8V
PRE
R/B
2nd 3rd .... n th
≈≈ ≈ ≈ ≈≈ ≈ ≈
≈
tR
FLASH MEMORY
36 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 16). Its value can
be determined by the following guidance.
tr,tf [s]
VCC
R/B
open drain output
Device
GND
Rp
tr,tf [s]
Ibusy [A]
Rp(ohm)
Fig 16 Rp vs tr ,tf & Rp vs ibusy
Ibusy
tr
ibusy
Busy
Ready Vcc
@ Vcc = 3.3V, Ta = 25
°
C , C
L
= 100pF
VOH
tf tr
1K 2K 3K 4K
100n
200n
300n 3m
2m
1m
100
tf
200
300
400
3.6 3.6 3.6 3.6
2.4
1.2
0.8
0.6
VOL
Rp(min, 1.8V part) = VCC(Max.) - VOL(Max.)
IOL + ΣIL = 1.85V
3mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp value guidance
Rp(max) is determined by maximum permissible limit of tr
Rp(min, 3.3V part) = VCC(Max.) - VOL(Max.)
IOL + ΣIL = 3.2V
8mA + ΣIL
1.8V device - VOL : 0.1V, VOH : VCCq-0.1V
3.3V device - VOL : 0.4V, VOH : 2.4V
Ibusy [A]
Rp(ohm)
Ibusy
tr
@ Vcc = 1.8V, Ta = 25
°
C , C
L
= 30pF
1K 2K 3K 4K
100n
200n
300n 3m
2m
1m
30
tf
60 90 120
1.7 1.7 1.7 1.7
1.7
0.85
0.57 0.43
C
L
FLASH MEMORY
37 SAMSUNG
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection and
is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10µs is required before internal cir-
cuit gets ready for any command sequences as shown in Figure 17. The two step command sequence for program/erase provides
additional software protection.
Figure 17. AC Waveforms for Power Transition
VCC
WP
High
≈
≈
WE
1.8V device : ~ 1.5V
3.3V device : ~ 2.5V 1.8V device : ~ 1.5V
3.3V device : ~ 2.5V
10µs
≈≈