CD4000-Series Ratings and Classifications Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (Vpp)..--..--...eee eee ~0.5Vto+20V Thermal Resistance Sia 8ic (Voltage Reterenced to Vgg Terminals) Ceramic DIP Package............06 28C/W TBDOC/AW Flatpack Package ............0e00 22C/W TBDOC/W Maximum Package Power Dissipation (Pp) at +125C For Ta = -559C to +100C (Package Types D,F,K)..... 500W Input Voltage Range, All Inputs .. DC Input Current, Any One Input. ......2... 0... cece eee i -5501 0 Operating Temperature ee (TA) ccc eecceeee 559C to +1259C ForTa = +1009C to +1259C (Package Types D, F, K)... .Derate Package Types D, F, K, Linearity at 12mW/C to 200mW -5 10 Storage Temperature Range {TsTG) .-..-.-.-. 50C to +150C Device Dissipation Per Output Transistor ..............- 100mW Lead Temperature (During Soldering) ...........6..0005 +265C For Ta = Full Package Temperature Range (All Package Types) At Distance 1/16 + 1/32 Inch (1.59mm + 0.79mm) from case for . Junction Temperature ......... 2. eee eee enter teers +1759C 10s Maximum Recommended Operating Conditions For reliabili inal op ing cor should be selected so that operation is always within the follawing ranges: Supply Voltage Range......... 20. c ccc e eee eee 3V Min, 18V Max (For Ta = Full Package Temperature Range) Device Classification for Leakage Current The table below classifies the levels of device leakage as_ which apply to a specific device type, consult the standard SSI, MSI-1 and MSI-2. In order to determine the limits DC electrical characteristics chart. CLASSIFICATION ACCORDING TO CIRCUIT COMPLEXITY BUFFERS/FLIP-FLOPS/ GATES/ LATCHES/MULTILEVEL INVERTERS (SSI) GATES (MSI-1) COMPLEX LOGIC (MSI-2) CD40008 CD4009uUB* cb4085B cCD4006B CD4060B CD4556B CD40018 CD4010B CD4086B cCD4008B CD4063B CD4585B CD4002B CD4013B CD4093B* CD40148 CD4067B* cb4724B CD4007UB CD4019B cb4095B CD4015B CD4076B CD14538B CD4011B CD4027B CD4096B CD4017B cb4089B CD40100B CD40128 cCD4030B cb4098B cD4018B cD4094B CD40101B CD4016B" CD4041UB* CD4502B* cCD40208 cb4097B* CD40102B CD4023B cD4042B CD4503B* cb4021B cb4099B CD40103B CD40258 CD40438 CD401088* CD40228 CD4508B CD40104B CD40486 CD4044B CD401078* CD4024B CD45108 cb40105B CD4066B* CD4047B CD40109B* cCD4026B CD4511B* cb401088 cDa068B cCD4049UB* cb40147B cbD4028B cCD4512B cCD401108* CD4069UB CD4050B cD401748 Cb40298 CD45148 Cb401608 CD40718 CD4070B CD401758 CD4031B* CD45158 CD401618 cD40728 CD4077B CD40257B CD4033B CD4516B CD40162B CD40738 cCD4034B CD4517B CD40163B CD4075B cD4035B CD4518B CD40181B cCD4078B cb40408 CD4520B CD40182B cp40818 cD4046B* CD4527B CD40192B CD4082B CD4051B* CD4532B CD40193B CD4052B* CD4536B cD40194B CD4053B* CD4555B cbD40208B * indicates type for which, because of design requirements, one or more static characteristics differ fram the standardized data. These differences are defined in separate DC Electrical Characteristics charts. 12-218Radiation Hardened High Reliability ICs Radiation Resistant CD4000-Series Harris radiation hardened CD4000-series CMOS integrated circuits tested to withstand total ionizing radiation dosages of 1 x 105 rads (Si) R-suffix types, and 1 x 106 rads (Si) H-suffix types. These radiation tolerances are achieved by special process controls imposed during wafer fabrication. Harris radiation hardened types may be screened to Mil-M-38510 Class S and to leve! /MS. The specified levels of radiation resistance are verified per Table V group E subgroup 2 of Method 5005 and tested according to Method 1019 of Mil-Std-883. Four elec- trically good packaged samples from each wafer, one from each quadrant, are exposed in a Cobalt 60 source for a time period corresponding to the specified total dose. The samples are then electrically tested within one hour after exposure for threshold voltage, threshold voitage delta, Ipp leakage current, and functionality. Propagation delay is also measured for 38510 tested product. p THRESHOLD THRESHOLD VOLTAGE Vv 39 O85 10 15 2.0 TOTAL DOSE 10RADS (Si) g2cs-31443 TYPICAL THRESHOLD VOLTAGE VARIATIONS OF HARRIS MEGARAD CD4000-SERIES CMOS INTEGRATED CIRCUITS AS A FUNCTION OF TOTAL DOSE GAMMA RADIATION RADIATION RESISTANT CD4000-SERIES CMOS ICs Post Radiation Test Criteria Maximum Limits for Ipp, (VDD = 18V for B-Series Types or 15V for A-Series Types) pp (MAX) Ipp (MAX) Ipp (MAX) Ipp (MAX) TYPE pA TYPE yA TYPE pA TYPE HA CD4000 25 cD4040 25 CD4078 25 CD4555 25 cp4001 2.5 cp4041 7.5 cD4081 25 CD4556 25 cD4002 25 cD4042 7.5 cD4082 2.5 cD4585 25 cD4006 25 CD4043 7.5 cD4085 25 cb4724 25 CD4007 25 CD4044 7.5 cb4086 2.5 cD40100 25 cD4008 25 cp4046 25 cD4089 25 CD40101 25 CD4009 75 CD4047 25 CD4093 7.5 cb40102 25 cD4010 7.5 cD4048 75 cD4094 25 cD40103 25 cD4011 2.5 cb4049 75 CD4095 7.5 cb40104 25 cp4012 2.5 CD4050 75 CD4096 7.5 cCD40105 25 CD4013 7.5 CD4051 25 CD4097 25 040106 75 cD4014 25 CD4052 25 CD4098 7.5 CD40107 75 CD4015 25 CD4053 25 cD4099 25 cD40108 25 CD4016 2.5 CD4060 25 CD4502 7.5 cD40109* 75 CD4017 25 cD4063 25 CD4503 7.5 cCD40147 25 cD4018 25 CD4066 25 CD4504 7.5 CD40160 25 CD4019 75 CD4067 25 cb4508 25 cD40161 25 CD4020 25 CD4068 7.5 CD4510 25 CD40162 25 cp4021 25 cD4069 25 cD4511 25 CD40163 25 Cb4022 25 CD4070 2.5 cD4512 25 Cb40174 7.5 CD4023 25 cCp4071 2.5 CD4514 25 CD40175 75 cD4024 25 cp4072 25 CD4515 25 CD40181 25 cb4025 2.5 CD4073 25 CD4516 25 cD40182 25 CD4026 25 cD4075 25 CD4517 25 CD40192 25 CD4027 7.5 CD4076 25 CD4518 25 CD40193 25 cb4028 25 CD4077 25 CD4520 25 CD40194 25 cb4029 25 CD4527 25 CD40208 25 CD4030 7.5 CD4532 25 CD40257 75 CD4031 25 CD4536 25 CD4033 25 CD4034 25 CD4035 25 Post Radiation Threshold Voltage Test Criteria (Vpp = 10V; 1 = Constant 10pA) N Threshold = 0.2V min P Threshold = 2.8V max *P Threshold = 3.5V max CD40109 and 40106 AP Threshold = 1.0V max AN Threshold = 1.0V max 12-219 LOGIC CIRCUITSRadiation Hardened High Reliability ICs Radiation Hardness Assurance Testing CD4000-Series Total Dose Testing Procedures * Class S Wafer Sampling > Test Four Samples (High-Rel Visual Rejects) > One From Each Quadrant of Wafer > Reject If Any One Sample Fails * Class B Inspection Lot Sampling > LT PD = 20, 11/0 18/1 CD4000-SERIES POST RADIATION TESTS SYMBOL CHARACTERISTIC JAN LIMIT NONJAN LIMIT VOLTAGE VIN N Threshold Voltage 0.3V Min 0.2V Min 10V Vip P Threshold Voltage 2.8V Max 2.8V Max 10V AVT Delta Threshold Voltage 1.4V Max 1.0V Max 10V Iss Quiescent Current 100 x Max 100 x Max 18V CD4000B-Series Pra-Rad Value Pre-Rad Value TPLH: Propagation Delay 1.35 x Max 5V* TPHL Pre-Rad Value * Worst case tes! condition Radiation Resistant CD4000 Series SCREENING LEVELS FOR HARRIS HIGH RELIABILITY RADIATION RESISTANT CD4000-SERIES CMOS ICs SCREENING LEVELS | APPLICATION DESCRIPTION PACKAGED DEVICES (D, F, K OR J SUFFIX) Class S with SEM Inspection and Aerospace and For devices intended for use where mainten- Condition A Precap Visual inspection Missiles ance and replacement are difficult and /MSR + Radiation Hardened to 105 Rads (Si) reliability is imperative /MSH +Radiation Hardened to 106 Rads (Si) CHIPS (H SUFFIX) SEM Inspection and Condition A Visual Aerospace and For hybrid applications where mainten- Inspection Missiles ance and replacement are extremely difficult /SR + Radiation Hardened to to 105 Rads (Si) and reliability is imperative /SH + Radiation Hardened to to 10 Rads (Si) 12-220Radiation Hardened High Reliability ICs CD4000-Series CMOS ICs Transient Radiation Resistance Samples of CD4000-series devices representing all levels of circuit complexity have been characterized for transient radiation effects. The data indicate the ranges of occurence of upset, latchup and survivability as a function of radiation dose rate. SURVIVABILITY LATCH UP UPSET 108 =109 1010 4011) 4982 1018 RADIATION DOSE RATE - RAD(S) / SEC EFFECTS OF TRANSIENT RADIATION (108 RADS (Si) ON CD4000-SERIES INTEGRATED CIRCUITS (ALUMINUM GATE CMOS ON BULK SILICON) Latchup Latchup occurs because of the presence of inherent bipolar SCR structures in bulk CMOS devices. In normal operation, the parasitic bipolar SCR remains inactive. The device is said to be in the latchup state when the parasitic SCR structures become activated, thereby creating a low impedance path from Vpp to Vsgs. In the ON condition, the SCR can conduct heavily at low voltages. Latchup may be induced by the resultant photocurrents of high intensity transient ionizing radiation or by applying excessive voltage. Once turned on, the SCR can be rendered dormant again only by removing the power supply. Burn-out of the device may result if the current is not limited in some way. The region of occurance of the latch condition in CMOS ICs under high intensity transient radiation is quite wide. Only two known device types latch below the 1 x 109 RAD (Si)/s level. A significant number of device types do nat latch above dose rates of 1 x 1011 RADs (Si)/s. Latchup Protection Latchup protection in bulk CMOS devices can be achieved by taking advantage of the effects of neu- tron irradiation. Neutron irradiation will reduce minori- ty-carrier lifetime, which, in turn attenuates the current gains, or betas, of bipolar transistors. To turn on the SCR structure of CMOS devices, it is necessa- ry for the beta product of its bipolar transistors are majority- carrier devices, normal CMOS performance is generally unaffected by neutron irradiation. There- fore, neutron irradiation is a suitable method for precluding latchup in CMOS devices. In addition, neutron-irradiated CMOS devices are less suscepti- ble to logic upset due to transient radiation. Neutron-irradiated CMOS Harris offers custom CD4000-series devices which are made from wafers that are exposed to a neutron fluence of approximately 1 x 1014n/cm2, After neutron irradiation, wafers can be assembled and screened to all requirements of the Harris leve! product. Survivability Survivability level is the maximum transient-radiation level at which damage does not occur. Above this level photocurrents are created to the extent that excessive dissipation is caused, resulting in perma- nent damage to the device. 12-221 LOGIC CIRCUITSHigh Reliability CD4000B8-Series CMOS ICs Standard DC Electrical Characteristics Standard B Series Devices The following table contains electrical characteristics for devices. These parameters are 100% tested except all CD4000B-series standard output CMOS. where indicated. Limits at indicated Temperatures Static Conditions Electrical -55C +25C +125C Units | Notes Parameters ramele Vo Vw | Voo | Min. | Max. | Min. | Max. | Min. | Max. Functional Teste _ _ _ _ _ _ _ _ - 4 Quiescent device _ 0,5 5 - 0.25 - 0.25 _ 7.50 current lpp _ 0,10 10 _ 0.5 _ 0.5 _ 15 A 1 SSI Types 0,15 15 1 10 300 | See Classification Chart _ 0,20 20 _ 5 _ 5. _ 150. MSI-1 _ 05 5 - te - Ie _ 30 See Classification _ 0,10 10 _ 2e _ ae - 60 A 12 Chart 0,15 15 4e 4e 1200 | # , - 0,20 20 _ 20. - 20 _ 600 MSI-2 - 0,5 5 _ 5e a 5e | 150 See Classification - 0,10 10 - 10 _ 10 _ 300 A 1 Chart 0,15 15 _ 206 ~ 20 600e | * _ 0,20 20 = 100- _ 100 _ 3000 Output low drive 0.4 0,5 5 0.640 _ 0.51 _- 0.36 - current 0.5 0,10 10 1.6 _ 13 _ 0.9 - mA lot min. 15 0,15 15 4.20 _ 3.4 _ 2.40 - Output high drive 46 05 5 -0.64 - 051 _ -0.36 - current 2.5 0,5 5 -2.0 _ -1.6 _ -1.15 _ mA low min. 9.5 0,10 10 -1.6 _ -1.3 _ -0.9 - 13.5 0,15 15 4.2 _ -3.4 _ -2.4 _ Output voltage _ 0,5 5 _ 0.05 _- 0.05 _ 0.05 low-level _ 0,10 10 - 0.056 _ 0.05 _ 0.05 v VoL max. 0,15 15 _ 0.05 _ 0.05 _ 0.05 Output voltage _ 0,5 4.959 _ 4.95 _ 4.95 _- high-level _ 0,10 10 9.950 _ 9.95 _ 9.95 - v Vou min. 0,15 15 14.95 _ 14.95 _ 14.95 _ Input low voltage 45 _ 5 - 1.5 - 1.5 _ 16 Vi max. 9 _ 10 - 3e _ 3 _ 3 v Buffered (B) 13.5 _ 15 _ 4 4 4 45 5 _ te _ 1 Unbuffered (UB) 9 _ 10 _ 2 _ 2 _ 2 v 13.5 ad 15 _ 2.5 _ 2.5 _ 2.5 Input high voltage 0.5, 4.5 _ 5 3.5 _- 3.5 _ 3.5 _ Vin min. - a) _ 10 7 7 7 v Buffered (B) 1.5, 13.5 ad 15 an] _ 11 _ ah] - 0.5,4.5 - 5 4 4 _ 4 _ Unbuffered (UB) 1,9 10 8 _ 8 - 8 - Vv 15,135} 15 12.5 _ 12.5 - 125 _ Input current _ 0,20 20 _ 0.1 _ +01 _ +1 pA 1 t 3-state output leakage current 0,20 0,20 20 _ +04 _ +0.4 _ +12 BA 1,3 lout * These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. NOTES: 1. At-55C test is performed with Vpp of 18V. 2. CD4047B - Maximum DC supply voltage Vpp ia 13V for radiation hardened version of this type when operating with RC network. 3. For applicable devices only. 4. At 25C Viyy = 0 ~ 20V, Vpp = 20V; 125C Vixqy = 0 - 18V, Von = 18V; and at -559C Viy = 0 - 3V, Vpp = 3V. 12-222High Reliability CD4000B-Series CMOS ICs Non-Standard DC Electrical Characteristics Non-Standard B Series Devices The table below indicates all devices which are consid- ered to be non-standard. Non-standard devices are types such as bilateral switches (CD40668), multiplexers (CD40518), special sink or source currents (CD4049UB, CD4050B), and open drain buffer/drivers (CD40107B) which exhibit non-standard outputs or special parameters. This table shows the 100% electrical tests that are performed on these spe- cialized devices. These tests take the place of corresponding parameters in the Standard Electrical Characteristics table. For the types listed with RON tests, drive current and output voltage tests should be deleted from the Standard Electrica! Characteristics table. Limits at Indicated Temperatures Static Conditions Electrical -55C +259C +1250C Units Parameters . . . Vo Vin Vpp Min./Max. Min. Max. Min./Max. CD4009UB, CD4010B Output low drive 0.4 0,5 45 3.28 2.6 _ 1.8 current 0.4 0,5 5 3.750 3 _ 2.1 mA lot min. 0.5 0,10 10 10.0 8 =_ 5.6 1.5 0,15 16 30.00 24 = 16.06 Output high drive 46 0,5 5 -0.25 0.2 _ -0.15 current 25 0,5 5 -1.0 -0.8 _ -0.58 mA Jon min. 95 0,10 10 -0.55 -0.45 - -6.33 13.5 0,15 15 -1.65 15 = 1.19 CD4016B Control Vis=Vss, Vos = Voo 5 0.9 _ 0.7 0.4 Input voltage low Vis = Vpo, Vos = Vss 10 0.90 _ 0.7 0.40 Vv Vin max. | hig | <10pA 15 0.9 _ 0.7 04 Control 5 3.5 3.5 - 3.5 Input voltage high _ 10 70 7.0 _ 7.0 Vv Vin min. 15 11.0 11.0 _ 11.0 On-state resistance Vis = Vop or Vss 10 600 _ 660 960 Ron max. Vis = 4.75 or 5.75 10 1870 _ 2000 2600 ohms Ri = 10k returned Vis = Vpp or Vss 16 360 _ 400 600 to Vpo-Vss/2 Vis = 7.25 or 7.75 15 775 - 850 1230 CbD4031B Output low drive 0.4 0,5 5 2.56 2.04 _ 1.440 current 0.5 0,10 10 64 5.2 _ 3.60 mA lo. min. Q 1.5 0,15 15 16.8 13.6 _ 9.66 _ 0.4 0,5 5 0.64 0.51 _ 0.36 Q, Q', CLd 0.5 0,10 10 1.6 1.3 _ 0.9 mA 1.5 0,15 15 4.2 3.4 _ 240 Output high drive 46 0,5 5 -0.640 -0.51 _ -0.36 current lon min. 25 0,5 5 -2.0 -1.6 - -1.150 mA _ 9.5 0,10 10 -1.6 -1.3 - -0.9 Q, Q, Q, CLd 13.5 0,15 15 -4.2 3.4 _ -2.40 CD4041UB Output low drive 0.4 0,5 5 2.1 1.6 _ 1.20 current 0.5 0,10 10 6.25 5 _ 3.5 mA lo. min. 15 0,15 15 a4e 19 _ 13 Output high drive 46 0,5 5 -2,1 -1.6 _ -1.2 current 2.5 05 5 8.40 -6.4 _ 466 mA lon min. 9.5 0,10 10 -6.25 5.0 _ -3.5 13.5 0,15 15 -246e -19 _ -136 Limits with black dots () are tested 100%. @ These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initia! design release and upon design changes which would affect these characteristics. 12-223 LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Non-Standard DC Electrical Characteristics (Continued) Limits at Indicated Temperatures Static Conditions Electrical -55C 4+259C +125C Units Parameters Vo Vin Voo Min./Max. Min. Max. Min./Max. CD4046B Zener diode = voltage (Vz) Iz = 50 uA 4.45 6.50 Vv Quiescent leakage _ 0,5 5 0.2 _ 0.2 phase comparator _- 0,10 10 4.0 - 1.0 - mA pin 14 open _- 0,15 15 15 _ 15 - pin 5 = Vop - 0,20 20 40 - 4.00 _ Quiescent leakage _ 0,5 5 20 _ 20 - phase comparator - 0,10 10 40 _ 40 - A pin 14 = Vsg or Vop 0,15 15 80 80 M pin 5 = Vpo - 0,20 20 160 _ 1600 _ CD4049UB, CD4050B Output low drive 0.4 0,5 45 3.3 2.60 _ 18 current 0.4 0,5 40 3.20 - 24 mA lor min. 0.5 0,10 10 10 8.00 _ 5.6 15 0,15 15 26 240 _ 18 Output high drive 46 05 5 0.81 0.80 - 0.48 current 2.5 05 -2.6 -3.20 _ -4.55 mA low min. 95 0,10 10 -2.0 -1.80 _ -4.18 13.5 0,15 15 5.2 6.00 - -3.1 CD4051B, CD4052B, CD4053B, CD40678, CD4097B On-state Ry, = 10k returned 5 800 _ 105060 130060 resistance to Voo-Vss/2 10 310 _ 4006 50060 ohms Ron max. Vis = Vss to Vop 15 200 _ 2400 32060 input voltage low Vee = Vss 5 150 _ 1.50 1.56 Vit max. Ri = 1k to Vss 10 3.0 _ 3.0 3.0 Volts | lis] <2 HA 15 4.0. _ 4.00 4.060 Input voltage high Vee = Vss 5 3.5 3.50 _ 3.5e Vin min. FR, = 1k to Vss 10 7.0 7.0 _ 7.0 Volts | is] <2 HA 15 11.00 11.060 _ 11.00 Off channel leakage Vss-V Vee-V current Any channel off max. 0 0 18 + 1006 - +100e | + 10006 nA Ail channels (common out/in) off max. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which wouid affect these characteristics. 12-224High Reliability CD4000B-Series CMOS ICs Non-Standard DC Electrical Characteristics (Continued) LOGIC CIRCUITS Limits at Indicated Temperatures Static Conditions Electrical -559C +259C +125C Units Parameters Vo Vin Vpp Min./Max. Min. Max. Min./Max. CD4066B On-state Rx = 10k returned 5 80060 _ 105060 13000 resistance to Vpp-Vss/2 10 31066 _ 40060 55060 ohms Ron max. Vis = Vss to Vpop 15 20066 _ 2400 32060 Control Input Voltage Low Vis = Vss, Vos = Voo 5 1.060 _ 1.00 1.06 Volt Vince max. Vis = Voo, Vos = Vss 10 2.0 _ 2.0 2.0 ous | lis |<10 uA 15 2.0 _ 2.00 2.060 Control Input Voltage High 5 3.5 3.5 - 3.50 Ving min. ~~ 10 7.0 7.0 _ 7.0 Volts 15 11.00 11.0 _ 11.00 input output leakage current (switch off) Effective off resistance 9 9 18 +100 ~~ + 100 + 1000 na Vc = Vss CD4093B Positive Trigger _ a 5 2.20 2.20 _ 2.20 Threshold Voltage _ a 10 46 46 _ 46 Vp min. _ a 15 6.8e 6.80 _ 6.860 Vv _ b 5 2.60 2.60 _ 2.60 - b 10 56 5.6 - 56 - b 15 6.3 6.3 - 63 Vp max. _ a 5 3.60 _ 3.60 3.66 _ a 10 7.1 _ 7A 7.1 _ a 15 10.80 _ 10.86 10.80 Vv - b 5 4e _ 4e 4e _ b 10 8.2 - 8.2 8.2 _ b 15 12.7 _ 12.7 12.7 Negative Trigger _ a 5 0.9 0.9e _ 0.90 Threshold Voltage _ a 10 25 2.5 _ 25 Vn min. _ a 16 4e 4e _ 4e Vv ~ b 5 1.40 1.40 _ 1.40 _ b 10 3.4 3.4 _ 3.4 = b 15 48 48 - 48 Vu max. - a 5 2.86 - 2.80 2,80 _ a 10 5.2 _ 5.2 5.2 - a 15 74e 7.40 7.40 v _ b 5 3.20 _ 3.20 3.20 _ b 10 66 _ 6.6 6.6 _ b 15 9.6 - 9.6 9.6 Hysteresis Voltage - a 0.30 0.30 - 0.30 Vi min. _ a 10 1.2 1.2 _ 1.2 . _ a 15 1.60 1.60 -_ 1.66 Vv _ b 5 0.30 0.30 _ 0.30 _ b 10 1.2 1.2 _ 12 _ b 15 16 1.6 - 16 Vi max. _ a 5 1.6 od 1.60 1.660 _ a 10 3.4 - 3.4 3.4 _- a 15 Se - 5e Se Vv - b 5 16 - - 1.60 1.60 - b 10 3.4 3.4 3.4 _- b 15 5 - 5 5 * Input on terminals 1, 5, 8, 12, or 2, 6, 9, 13; other inputs to Vpo. input on terminals 1 and 2, 5 and 6, 8 and 9, or 12 and 13; other inputs to Voo. * These parameters are controlled via design or process parameters and are not directly tested. Thesa parameters are characterized upon initia! design release and upon design changes which would affect these characteristics. 12-225High Reliability CD4Q000B-Series CMOS ICs Non-Standard DC Electrical Characteristics (Continued) Limits at indicated Temperatures Static Conditions Electrical ~550C +259C +1259C Units P; arameters Vo | Vin | Voo | Min/Max. | Min. Max. | Min./Max. CD4502B Output low drive 0.4 0,5 5 3.84 3.060 _ 2.16 current 0.5 0,10 10 9.6 7.80 _ 5.4 mA lot min. 15 0,15 15 25.2 20.4e _ 14.4 CD4503B Output low drive 0.4 0 5 2.6 2.10 _ 13 current 0.5 0 10 6.5 5.50 _ 3.8 mA lot min. 15 0 15 19.2 16.10 11.2 Output high drive 46 5 5 -1.2 -1.020 _ 0.7 current 2.5 5 5 5.8 4.80 _ -3.0 mA lon min. 95 10 10 -3.1 -2.60 _ -1.8 13.5 15 15 -8.2 6.80 _ 4.8 CD4504B Vec Input low TTL-CMOS 5 1 - 10 0.8 _- 0.8 0.8 voltage TTL-CMOS 5 1 _ 15 0.80 _ 0.80 0.8 Va max. CMOS-CMOS 5 1 _ 10 1.50 _ 1.5 1.5 CMOS-CMOS 5 15 _ 15 1.5 _ 15 1.5 CMOS-CMOS | 10 15 - 15 3e - 3e 3e y Input high TTL-CMOS 5 9 _ 10 2 2 _ 2 voltage TTL-CMOS 5 13.5 _ 15 2 Qe _ 20 Vin min. CMOS-CMOS 5 9 _ 10 3.50 3.50 _ 3.50 CMOS-CMOS 5 13.5 _- 15 3.5 3.5 _ 3.5 CMOS-CMOS | 10 13.5 - 15 7e Te _ 7e CD4511B Output voltage _- 0,5 5 4 4] _ 42 high-level _ 0, 10 10 9 91 _ 9.2 Vv Vou min. _ 0, 15 15 140 14.106 _ 14.20 lou (mA) 0 _ _ 5 40 4.10 _ 4.20 5 _ _ 5 _ _ _ _ 10 _ _ 5 3.80 3.90 _ 3.90 Vv 15 _ - 5 - _ _ 3.50 20 - - 5 3.55 3.400 _ _ 25 _ _ 5 3.40 3.10 _ _ 0 _ _ 10 9.0 9.10 _ 9.20 Output drive 5 _ _ 10 _ _ _ _ voltage 10 _ _ 10 8.85 9.0 _ 9.0 v high level 15 _ _ 10 _ _ _ _ Von min. 20 - - 10 8.70 8.6060 _ 8.40 25 _- - 10 8.60 8.30 - - 0 - - 15 14.0 14.10 _ 14.20 5 _ - 15 - _ _ 10 _ _ 15 13.90 14.0 _ 14.0 v 15 = 15 _ - _ 20 _ _ 15 13.75 13.700 _ 13.50 25 - - 15 13.65 13.50 _ _ * These parameters are controlled via design or process parameters and are not directly tested. These parameters ara characterized upon initial design release and upon design changes which would affect these characteristics. 12-226High Reliability CD4000B-Series CMOS ICs Non-Standard DC Electrical Characteristics (Continued) Limits at Indicated Temperatures Static Conditions. Electrical -559C +259C +125C Units Parameters . . Vo Vin Voo Min./Max. Min. Max. Min./Max. CD40106B Positive trigger _ _ 5 2.20 2.26 _ 2.20 threshold voltage _ 10 460 4.66< _ 4.60 Vv Vp min. _ _ 15 6.80 6.80 _ 6.80 _ _ 5 3.60 _ 3.60 3.60 Vp max. _ _ 10 7.10 _ 710 7.10 Vv _ _ 15 10.8 _- 10.80 10.8 Negative trigger _ _ 0.90 0.96 _ 0.90 threshold voltage _ _ 10 2.50 2.5 _ 250 v Vn min. _ _ 15 4e 4e de _ _ 5 2.80 _ 2.80 280 Vn max. _ _ 10 5.20 _ 5.20 5.20 Vv _ 15 74Ae _ 74e 7Ae Hysteresis _ _ 5 0.30 0.30 _ 0.30 voltage _ _ 10 1.20 1.20 _ 1.20 v Vu min. _ _ 15 1.60 1.66 _ 1.60 _ _ 5 1.60 _ 1.6 1.60 Vi max. _ _ 10 3.40 _ 3.40 3.40 Vv _ 15 Se _ 5e Se CD40107B 0.4 05 5 241 160 _ 12 Output low 1 0.5 44 S4e ~~ 2 P . 05 0,10 10 49 37 _ 28 mA in 1 0,10 10 89 680 _ 51 oL min. 05 0,15 15 66 500 38 Output high current NO INTERNAL PULL-UP DEVICE Jou min. Input low volt 45 - 5 1.50 _ 150 150 ee nu . age 9 _ 10 3 _ 3 3 Vv m max. 13.5 = 15 4s - 40 4s . 0.5, 4.5 _ 3.50 3.56 _ 3.50 Input high voltage 19 _ 10 7 7 _ 7 Vv w min. 1.5, 13.5 15 te 110 110 * Measured with external pull-up resistor, Ry = 10k2 to Vop * These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which wauld affect these characteristics. + At-55C test is performad with Vpp of 18V 12-227 LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Non-Standard DC Electrical Characteristics (Continued) Limits at Indicated Temperatures Static Conditions Electrical -55C +25C +125C Units P: ters aramele Vo Vec | Voo | Min/Max. | Min. Max. | Min./Max. CD40109B Input low voltage 1,9 5 10 1.5e _ 1.50 1.50 Vv Vir max. 1.5, 13.5 10 15 Se _ Se 3e Input high voltage 1,9 10 3.56 3.50 _ 3.50 Vv Vin max. 1.5, 13.5 10 15 Te Te _ Te CD401108 lon Vou Vin Voo Output Voltage _ _ 0,5 5 0.05 _ 0.05 0.05 Low-Level _ 0,10 10 0.05 _ 0.05 0.05 Vv Vo. max. _ _ 0,15 15 0.05 _ 0.05 0.05 . 0,5 5 - High-Level _ 0,10 10 _ _ Vv oN _ _ 0,15 15 _ a _ _ 5 3.9 3.9 _ 4 5 _ _ 3.65 3.7 3.7 -10 - _ 3.55 3.65 _ 3.65 Vv -15 _ 5 3.5 3.6 _ 3.5 -20 _ _ 5 3.45 3.450 _ 3.35 -26 _ - 5 3.4 3.4 _- 3.3 a 10 8.75 8.75 8.85 7-Segment Outputs 5 - _ 10 8.45 8.55 =_ 8.55 Output Drive -10 _ _ 10 8.42 8.5 _ 8.5 Vv Voltage, High -15 _ 10 8.4 8.47 8.47 Vou min. -20 _ _ 10 8.4 8.450 _ 8.40 -25 _- _ 10 8.3 8.3 _ 8.25 = 15 13.8 13.8 _ 13.9 5 _ 15 13.65 13.75 13.75 -10 _ 15 13.6 13,72 13,72 V -15 _ 15 13.6 13.7 13.7 -20 ~ 15 13.6 13.650 13.6 -25 _ 15 13.3 13.3 - 13.25 7-Segment Outputs 0.4 05 5 1.28 te 0.72 Sink C trent 05 0,10 10 3.2 2.6e _ 18 mA (Sink) Cu ~ 15 0,15 15 8.4 6.86 - 48 Jo. min. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design ralease and upon design changes which would affect these characteristics. m0 (10pA) 12-228High Reliability CD4000B-Series CMOS ICs Switching Characteristics at 250C The chart below lists all Harris high reliability CD4000B- series devices and shows which switching parameters are 100% tested at final electrical and Group A. In gener- al, Harris tests propagation delay, transition time, and maximum clock frequency at 5V where applicable. Harris warrants all other switching parameters shown in the appropriate commercial data sheet. Harris high relia- bility switching tests are performed on a one-input to one-output basis only. MAX MAX CLOCK CLOCK PROP |TRANS.| INPUT PROP |TRANS. | INPUT CONDITIONS* DELAY] TIME | FREQ. CONDITIONS* DELAY] TIME | FREQ. TYPE Vpp = 5V, CL = 50pF (ns) | (ns) | (MHz) TYPE Vop = 8V, CL = 50pF (ns) | (ns) | (MHz) CD4000B - 250 200 - CD4024B otoQi 360 200 3.5 CD4001B - 250 200 - QntoQn+1 330 - - CD4002B - 250 200 - Reset to @ 2804 - ~ CD4006B - 400 200 2.5 CD4025B - 250 200 - CD4007UB - 116 200 - CD4026B Clock to Carry Out 500 200 2.5 CD4008B Sum In toe Sum Out 800 200 - Clock to Decode Out 700 - - Carry In to Sum Out 740 - ~ Reset to Carry Out 550* - - Sum In to Carry Out 400 - - Reset to Decode Out 600 - - Carry In to Carry Out 200 - - CD4027B Clock to QorQ 300 200 3.5 CD4009UB - 140* | 350* - Set to Q or Reset to 300* - - - 604 | 70a - Set to OF or Reset to Q 400a | - - CD4010B - 200* | 350* - CD4028B - 350 200 - ~ 1304 | 704 - CD4029B | Q Output 500 200 2 CD4011B - 250 200 - Carry Output 560 - - CD4012B - 250 200 - Preset Enable to Q 470 - - CD4013B Clock to Q orQ 300 200 3.5 Preset Enable to Carry Out 640 - - Set to Q or Reset toQ 300* - - Carry Input to Carry Out 340 - - Set to or Reset to 400a | - - CD4030B - 280 | 200 - C04014B - 320 200 3 CD4031B | ClocktoQ 500 200 2 CD4015B_ | Clock to Q 320 200 3 Clock to Q 500* - - ResettoQ 4004 - - Clock toQ 3804 - - CD4016B Sig. Input to Sig. Output 100 - Clock to Q 380 - - Turn On 70 - - Clock to CL 200 - - CD4017B Clock to Out 650 200 2.5 CD4033B Clock to Carry Out 500 200 2.5 Clock to Carry Out 600 - - Clock to Decode Out 700 - - Reset to Out 530 - - Reset to Carry Out 550* - - CD4018B Clock to Q 400 200 3 Reset to Decode Out 600 - - Preset/Reset toQ 550 - - CD4034B Parallel In to Parallet Out 700 200 2 CD4019B - 300 200 - AE to A Out tp_z, tpzL, 400 - - cp4o208 | toat 360 | 200 | 35 tPHZ,tPZH QntoQn+1 330 _ . CD4035B Clock to Q 500 200 2 Reset to Q 2804 - - Reset to Q 460 = = CD4021B _ 320 200 3 CD4040B_ | 6toQ1 360 200 3.5 cp40228 | Clock to Carry Out 600 | 200 | 25 QntoQn +1 330_| - Clock to Decode Out eso | - - Reset to Q 2804 | - = Reset to Output 530 | - - CD4041UB - 120 | 80 - CD4023B - 250 200 - *trLH Or tpLH 4 OTHE OF tPHL 12-229 LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Switching Characteristics at 25C MAX. MAX. CLOCK CLOCK PROP. |TRANS.| INPUT PROP. |TRANS.| INPUT CONDITIONS* DELAY| TIME | FREQ. CONDITIONS* IDELAY| TIME | FREQ. TYPE Vpp = 5V, CL = SOpF (ns) | (nap | (MHz) TYPE Vpp = 5V, CL = 50pF (ns) | (ns) | (MHz) CD4042B DataIntoQ 220 200 - CD4071B, - 250 200 - a 72B, 73B. DatalntoQ 300 - - ' , 2 75B Clock to Q 450 - - = CD4076B Clock toQ 600 200 - lock t 500 - - Clock to @ 5 0040778 - 280 | 200 | - CD4043B, { Setor Resetto 300 200 - CD4078B - 300 200 3 44B Enable to Q - t yt 230 - - = Q=1PHZ,1PZH CD40818, - 250 | 200 | - Enable to Q - tp.z, tPZL 180 - - 82B CD4046B | AC Coupled Signal Input 360mV Max CD4085B, | Data 4504 | 200 - Voltage Sensitivity (Peak 86B 620* - - to Peak) fj = 100kKHz vs Sine Wave Inhibit 3004 - - cp40478 | tRtoa,a 4000 } 200 - S00" | = - Astable to Q, a 700 _ _ CD4089B Clack to Out 300 200 1.2 Retrigger to Q, a 600 _ _ Clear to Out 760 - - Astable to Oscillator 400 | - - Cascade to Out 180 | - = Reset to Q, Oo 500 _ _ CD40938 - 380 200 - CD4048B Ka to Output 600 200 _ CD40948 Clock to Serial Out Qs 600 200 1.25 CD4049UB _ 120* 160* _ Clock to Serial Out Qs 460 - - _ 65a 60a _ Clock to Parallel Out 840 - - cb40508 _ 140* | 160* - Strobe to Parallel Out 580 - - _ 4104 | 60a _ Out Enable to Parallel Out, 280 - - PHZ: 'PZH CD4051B, | Add to Signal Out 720 - - Out Enable to Parallel Out, 200 - - 52B, 53B inhibit to Signal Out - 720 - - tpLz, tpzL Channel On CD4095B, | Clock to Output 500 200 3.5 Inhibit to Signal Out - 450 - - 8 Channel Off 96 Set or Reset 300 - - CD4060B _| Input Pulse Operation 740 | 200 | 35 D40978 {Address or Inhibit to Sig. 650) - - 61 1004 Out ~ Channet On QntoQn=1 200 _ _ Signai In to Out 60 - - Reset Operation 3604 _ Z CD4098B Trigger to Q,Q 500 200 - CD4063B | Comparator Input to Output | 1250 | 200 - CD40908 | Data to Output 400_| 200 Cascade Input to Output 1000 _ _ CD4502B Data or Inhibit Delay Time 380* 200* CD40668 __| Signal input to Signal 40 - - 2704 | 1204 | = Output Ry = 200k, Disable Delay Time - tpz 120 - - Vc = VpD: Vss = GND, Disable Delay Time - t 220 - - Vis = Square Wave = 5V ye P2H and t,, t?= 20ns Disable Delay Time - 250 - - tpLz. tPZL tode 70 - - > ~ tro tie = 20ns, RL = 1k & CD4503B - 150 90 - Vis < 5V - 1104 | 70a - CD4067B | Addorinhibit to Signal 650 - - tpHz. tpzH 140 - - Out Channel On - tpLZ tpzL 180 - - Signal In to Out 60 - - CD4068B - 300 200 - CD4070B - 280 200 - tTLH OF tpLH 4 tTHL OF PHL 12-230High Reliability CD4000B-Series CMOS ICs Switching Characteristics at 259C MAX. MAX. CLOCK CLOCK PROP. |TRANS.| INPUT PROP. |TRANS. | INPUT CONDITIONS* DELAY] TIME | FREQ. CONDITIONS* DELAY| Time | FREQ. TYPE Vpp = 5V, CL = 50pF (ns) (ns) | (MHz) TYPE Vop = 5V, CL = 5O0pF (ns) ] (ns) | (MHz) CD4504B SHIFT CD4536B_ } Clock to Q1 8 Bypass High | 2000 | 200 0.5 MODE Voc| CG |"dD Ciock to Q1 8 Bypass Low 5000 - - TILto CMOS | 5 j 10 | 2804 - - Clock to Q16 8000 - - Voo> Veco cmMoStocmMos| 5 | 10 |2aoa] - - Resetto Qn 60004 | - - Vop>Vcec CD45558, | Select to Any Output 440 | 200 - CMOS to CMOS] 10 5 | 5504 - - 568 Enable to Any Output 400 - - Vec>Vob CD4585B | Comparator Inputs to 600 | 200 - TILtocMos | 5 | 10 | 280* - - Outputs Voo> Vcc Cascade Inputs to Outputs | 400 - - CMOSto CMOS} 5 | 10 | 240% | - - cD4724B__| Datato Outputs 4co | 200 - Vop>Vec Write Disable to Output 400 - - CMOStoCMOS| 10 | 5 | 400* - - Vec> Yop Reset to Output 3504 - - All Modes - 5 200 - - Address to Output 450 - - trot tTLH = [10 { 100 = = CD1438B_ | Trigger toQ,Q 600 200 - CD4508B_{ Strobe In to Data Out 260 | 200 - Reset to QorQ 500 - - CD4516B Clock to Q Output 400 200 2 CD401008 - 720 200 1 Preset or Reset to Q 420 = = CD40101B | Data in to Output 70a | 200 - Clock to Carry Out 480 = = Inhibit in to Output 280 - - Carry In to Carry Out 250 = = CD401028, | Clock to Output 600 200 7 Preset or Reset to Carry Out | 640 = = 1038 Carry In/Counter Enabteto | 400 - - CD4511B | Datato Output 10404 | 3104 - Output - 1320* | Bo* - Asynchronous Preset 1300* - - "has Enable to Output CD4512B | Inhibit to Output 280 | 200 - Clear to Output 750A - - A Select to Output 400 - - CD40104B8 | Clock toQ 440 | 200 3 Data to Output 360 - - 'pzH, tpLz. tpze 160 = - tpHz, tpZH 120 = = tpHz 90 = - CD45148, | Strobe or Data 970 200 - CD40105B | Shift Out or Reset to 3704 | 200 1.5 15B Inhibit 500 ~ ~ Data Out Ready CD4516B | Clock to Q Output 400 | 200 2 Shift In to Data In Ready 3204 ~ Preset or Reset to Q 420 _ = 3-State Control to Data 280 - - Clock to Carry Out 480 - - Out tpzH Carry In to Carry Out 250 - - Ripple Thru Delay Input to 4000* - - Preset or Reset to Carry Out | 640 - - Out tpLy CD4517B_ | Clock 10 Q16 400 | 200 3 D401068 280 | 200 - cD4518B, | Clock to Output 560 | 200 | 15 b401078 | RL = 1202 200_|_ 100 - 20B Reset to Output G50 7 _ CD40108B | Clock or WriteEnabletoQ | 720 | 200 15 CD45278 | Clock to Out 300 | 200 | 12 Read or Write Address toQ | 600 - - Clear to Out 760 _ _ Disable Delay Time 200 - - Cascade to Out 180 PZH APHZ eoe Disable Delay Time 260 | - - CD4532B | E| to Eg, Ej toGs 220 | 200 - tpzL tpLz Dn to Qm 440 - - Dn to Gs, Ey to Qm 340 - - * tTLH OF (PLH 4 THE OF (PHL 12-231 LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Switching Characteristics at 259C MAX. MAX. CLOCK CLOCK PROP. |TRANS.| INPUT PROP. |TRANS. | INPUT CONDITIONS* DELAY| TIME | FREQ. CONDITIONS* IDELAY| TIME | FREQ. TYPE Vpp = SV, CL = 50pF (ns) | (ns) | (MHz) TYPE Vpp = 5V, CL = 50pF (ns) | (ns) | (MHz) CD40109B | Data Input to Output CD40181B | AorB to F (Logic Mode) 800 | 200 - SHIFT AorBtoGorP MODE Vcc } Ypo AorBtoF,Cn+4,orA=B8 | 1000 - - L-H 5V | 10V | 6004 | 100 - Cn to F 640 - - L-H 5V | 10v | 260* - - CntoCn+4 400 - - H-L 1ov | 5V | 5004 | 200 - CD40182B | P, Gin toP, Goyr and 400 | 200 - H-L jov | sv | asox J - - Carry Outs 3-State Disable Delay Ry = 1k Cn to Carry Outs aso | - = CD40192B, | Clock Up or Clock Down 500 | 200 2 SHIFT MODE | Vcc | Vpp 193B 10Q, Reset Q tpuz | L-H | sv [tov] 120 | - - PEO 400 | = - Clock Up to Carry, Clock 320 - - t H-L | tov] 5v | 4 - - PHZ v 00 Down to Borrow t L-H | 5v | 10V | 740 - - PLZ Reset or PE to Borrow 600 - - tptz }] H-L | 10V] 5V 500 - - or Carry tpzH | LH | 5V | 10V{ - = = CD40194B | Clock toQ 440 | 200 3 tpzH | H-L_ | 10V | 5V_| 600 = = Reset to Q 4604 - - fpz_ | _L-H | 5V_j 10V | 200 = = CD40208B | Clock orWriteEnabletoQ | 720 {| 200 15 tpz_ | H-L {| 10V | SV | 400 = = Read or Write Address toQ | 600 - - CD40110B }j Clock to Carry or Borrow 600 - 1.0 3-State Disable Delay Time | 200 - - CD40147B | in-Phase Output g00 | 200 - 1pZH) tPHZ CD401608, | Ciock toQ 400 | 200 2 {pzL. tPpLz 260 = = 161B, 1628, | Clock to Cour 450 - - CD40257B | Data input to Gutput 300 200 - 163B Te to Cour 250 - - Select to Output 380 - - Clear to Q (CD40160B & 5004 - - Output Disable to Output - = = CD 40161B only) tpzu. PHZ 190 - - CD40174B | Clock to Output 300 | 200 3.5 tpzL. tpLz 190 - - Clear to Output 2004 - - CD40175B | Clock to Q Output 400 | 200 2.0 Clear to Q Output 5004 - - *tTLH OF tel 4 tTHL OF tPHL 42-232High Reliability CD4000B-Series CMOS ICs Functional Diagrams Ne K=DHEtF . NC H=AtBt+C 92CS-24757 Dual 3-Input NOR Gate Plus Inverter 92CS-24762 Quad 2-Input NOR Gate 14 [ Yoo 3g Hey Hg io nc 8 19_ Vg6-4 K=E+FeG+H [8 92CS- 24758 Dual 4-Input NOR Gate < 92c5 2scaoR: ss 18-Stage Static Shift Dual Complementary Pair 4-Bit Full Adder with Hex Buffer/Converter Register CbD4000B (File No. 985) | CD4001B (File No. 985) | CD4002B (File No. 985) (File No. 945) CD4006B (Fite No. 1033} 14 2 4i A 2 A A +> GA 8 2-4 a B > a P| P, P| ? 61. ? 6 a 5 a? 9 5 o 2 5 o 2 > 10 ip ew 2 ne el 2 ee 7 4 9 Yss7 9208-25035 8 F 6 8 uF rs 8 LF Vpot!4 U aoe Yeo 1 Veo L Vgg 2 Yop" !6 Veg 2 Von i6 C : . {CARRY IN) Me vest No nts 9258-4140R2 secnamee 3 Hex Butter/Converter Pius Inverter Parallel Carry Out lnverting Type Non-inverting Type CD4007UB (File No. 977) | CD4008B (File No. 951) | CD4009UB (File No. 940) | CD40108 (File No. 940) JeRB | ABD a parn.in. OO A I [ po 12345678 a4y 13k afelslelebalsli| fe s4 2 gar. _3| CONT. k 4 6 SER, 5 IN. 2a, 3 5 19 c o F crock 2978 ne2J 19 [3_@9 3 vss4 KrE-F-GH fe _ ne 92cS-25047 te 92c$-25046 Vs5 ss 92CS- 24759 8-State Synchronous Shiit Quad 2-Input NAND Gate Dual 4-Input NAND Gate Dual D Flip-Flop with Register with Parallel or Sel/Resei Capabiii Serial input/Seriat Output cD4011B (File No. 986) | CD4012B (File No. 986) eset Capability np wipe CD4013B (File No. 936) | CD4014B (File No. 1043) File No. = commercial data sheet 12-233 LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Functional Diagrams Yop 16 z 5 DATA, Qa cLock 4g A 4 28 sTace| |3 RESETA a3a 10 94a DATA g {3 ip ' 12 CLOCK, 4 Q28 STAGE RESET, * Nase 2 Gap 8 gecs-26048 Vss Dual 4-Stage Static Shift Register with Serial Input/Parallel Output invout 4 LA von SIG A sy outin-24 Lbs CONT ouT/IN 4 12. CONT sig B A invout 4 UH! NvouT sis 0 coNT 5 | UO our vin * LA CONT 8 13 ouTviN sw sig Cc z c 8 ss 4 18 in vouT 92CS$-21627 Quad Bilateral Switch crock 4 crock _!3 INHIBIT reseT 34 DECODED DECIMAL OUT. Vpn =16 Vgg =8 92CS- 25072R2 Decade Counter/Divider with 10 Decoded Decimal Outputs JAM. inputs 2 2 wpe aight ge tt afizhe PRESET - ENABLE LS a, 14 azd.. crock 4 + Ge} & o - lo pata If asta oc wd 15 wes [te RESET 4 Gal S a 13 as je 9208-25074 vss Presettable Divide-by-N Counter Fixed or Programmable 92CS-25053R3 8-Stage Static Shift Register Asynchronous Parallel or CDB40158 (File No. 1024) | CD4016B (File No. 953) | CD4017B (File No. 1113) | CD4018B (File No. 1034) Vec par.in. od 4 > ee pe f crock 4 9 [14 16 12345678 clock _'3] ! Aa INHIBIT . to 2 or 5 3 5 3 INPUT rea lf 7\6|s{4k Lats] 16 RESET 3 Ba t2-e4 | 5 7 if PULSES 5 2 fe ! lz ra 88 5 1 i a3] | b+o6 | 3] par. g 8 3 S 3 ari " L6 oz 1a] ser| F 8 Ag PartAgKaltgXe) Foe, vastace LS og | # | CONT. w eA | counter tag fu | seRuw K 5 Ss; 1 14 i iN. 1 2 5 A) au Dy aio} 3 a6 3 VoneI6 10 ai Ps ou | @ 5 | Yo yo Lt gio] crock li2_O7 & Vsg=8 12 vss 12 ons CARRY tu 3 ola %6 5 ouT meesraso8e eee 92CS-25073R2 RESET ; ts GND 92CS25047 ss Triple 3-Input NAND Gate CD4023B {File No. 986) 92CS-25051R4 7-Stage Ripple-Carry Binary Counter/Divider 040246 (File No. 1063) Triple 3-Input NOR Gate CD4025B (File No. 985) Synchronous Serial Input/ Divide-by-8 Counter/Divider with Quad AND/OR Seleci Gate 14-Stage Binary Ripple Counter Serial Output 8 Decoded Decimal Outputs CD4019B (File No. 1045) | CD4020B (File No. 1063) | CD4021B (Fite No. 1043) | CD4022B (Fite No. 1113) Vbo Yoo I4y, or D fs ; isf oye 9 13 CLOCK > s 12 2 be al, 5 12 INPUT | u 5 2] 3 6/2 rH t+ Q2 a PULSES FE TNRielT L9 Lo I P 93/ 15 n 18 "| aeser2| gate Lo a,fe very te 10 RESET COUNTER bed ia [& |* jlo 5 t fF 12 UNGATED"C tL? 9. 9 SEGMENT 5 CARRY OUT 9 4 p 4 agit 3 KK 3 DISPLAY DISPLAY VssJ [8 a7 vss ENABLE ] ENABLE eRe Js Bae " \ Vss 928- 24761 NC=8,10,13 y 92c8 - 24760 92C8-25070R2 S$ Decade Counter/Divider with 7- Segment Display Output and Display Enable CD4026B (File No. 1118) File No. = commercial data sheet 12-234High Reliability CD4000B-Series CMOS ICs Functional Diagrams SET 90 PRESET t 6 INPUTS Yop ! BUFFERED ENABLE 3-@IT of OCTAL BUFFERED BINARY oO}, Ls DECODED CARRY IN OUTPUTS s7 UTPUTS (Lock J, 10) 2 (10F 8) Saaeces 5 Kia a fe = I BINARY/ cLock, + BUFFERED DECADE 9 INPUTS st&_| f pecma RESET, 216 6 DECODED SETp 7(4_| | outputs UP/DOWN. 10 5) Wy al? (1OF 10) . Jo fs CLOCK 15 Ko 9 chock 1 CLOCK capRY ] Yss 92CS~ 19151 9208-17190R3 Vg RESET, __4] ) Vss 92CcS-ITI87RI Duai J-K Master-Siave Flip-Flop with Set-Reset Presettabie Up/Down Counter, Capability BCD-to-Decimal Decoder Binary or BCD-Decade CD4027B (File No. 942) CbD4028B (File No. 1016) CD4029B (File No. 1028) \ 14 pare 18 16 vee aan Lv, 8 2| 13 | MODE 10}conrRoL] 64 ] [Og ay ot CONT. LOGIC [|STAGES| DATA CLOCK e 3 RECIRC pour 12 a | & DATA2 4 6 rhle x bt 'N BATA 2 3../2 cy HO | cock 2 | cul | eS clock tle 9 IN clock - INHIBIT 9 w o-9 9 cosic | &L] oats ? 8 Vg5"4 jee !5 | woot 172, | @ RESET p15 STAGE [5 K J*A@B L= E@E 9 [8 K:C@D Me G@H DELAYED 14 CLOCK Lame [7 9 Yoo = '6 TEST CARRY Vgg= 8 5 ouT 92C8-IT410RI NC = 3,4,11,12,15,14 92cg- 200391 >] RIPPLE RIPPLE BLK. 8) ak. IN Vgg OUT. 92CS~-25076RI Decade Counter/Divider 64-Stage Static Shift with 7-Segment Display Quad Exclusive-OR Gate Register Outputs and Ripple Bianking CD4030B (File No. 1055) | CD4031B (File No. 1073) CD4033B {File No. 1118) sI PARALLEL itt Yee ao ' E Ae | sreenin 1 2 3 4 fis Esa ABT | oGic a ol if el F A/S 4 \ 29 FeA P/s f 10 | | 2 pe fal Aes toe | y rc 4, 6 ree 15 6=8 cLK | 5 2 1 aa | 5 q L505 | 3 3" ++ Pes \2-STAGE 2 S HB 1, ) owe RIPPLE [4% L& >+ sr ioe =f 5 couNTER fo? [& (2 8, > RESET 4 Pos |e KC ig f] sTAGES al Yoor* |! is 4 ida Ha? 2 a. 5 Pee t] vcs 28 a0 | ut 3 = 2 HS on a Lp Q,/5, Q/O2 03/03 O4/q u i 13 = < _ tai2 Se = Loe & Ter out RESET D M <> e : 9208-I9966Rt Je _*, ne pe Gnd Vgg=7 ep - Vpo2t4 - 9268-29108 4-Stage Parallel In/Parallel 92CS-29066R2 S20S-20034R 8-Stage Static Bidirectional Out Shift Register with Parallel/Serial Input/Output J-K Serial Inputs and True/ 12-Stage Ripple-Carry Binary Quad True/Complement Bus Register Complement Outputs Counter/Divider Buffer CD4034B (File No. 1062) | CD4035B (File No. 1101) | CD4040B (File No. 1063) | CD4041UB (File No. 934) File No. = commercial data sheet 12-235 LOGIC CIRCUITSHigh Reliability CD4 Functional Diagrams O00OO0B-Series CMOS ICs 92cs~- 29172 Micropower Phase-Locked Loop lAGRAM yn e CD4043A TERMINAL DIAGRAM CD4044A TERMINAL DI 4O_,_} +02 0 | Sis . m, 2. LATCH 70 25 10 ' LATCH a S: } a Be R D3 fLw,. * 9 B3O T+ 20 So LATCH LATCH a 5 2 2 04 +} 0 i2 Re = 4 oO ' S3 LATCH LATCH Bq 3 Q3 3 | }-_ |5 Ry cLock 5 ck Sa LATCH 4 R POLARITY 4 6 16 VoO DDS 928-2019! VssO ENABLE ENABLE 928-2022If1 s2es- 20222 Quad 3-State NOR R/S Quad 3-State NAND R/S Quad Clocked D Latch Latch Latch CD4042B (File No. 954) | CD4043B {File No. 956) CD4044B (File No. 956) * SIGNAL 1 TIMING R- TIMING rT Re OSCILLATOR OUT come I OUT | COMMON | COMP IL OUT 3) ASTABLE > ASTABLE FREQUENCY (8) GATE TOWER GIVIDER _ asvasce |_| CONTROL MULTIVIBRATOR (+2) > | @ vo a ASTABLE | | I cl S - TRIGGER | MONOSTAaLEL, | | Yss @tInssee CONTROL | Vss @ RETRISGER | RETRIGGER } | CONTROL EXTERNAL | RESET I 92cs-z29071 Low-Power Monostable/Astable Multivibrator CD4046B (File No. 1099) CD40478 (File No. 1123) BINARY CONTROL INPUTS *__,, A 2-2 GA A 21> GA FUNCTION CONTROL 3-STATE Kg Ky Ke "e COnTROL B 2) >o4 HB B + HB L ! 4 4 CHANNELS ; c INfouT | 3 Aa c 1) 0 Ist c 7/>+ I-c 5 B-{13 mpurs ah o 2 0 4.5 D a4 > ued A 8 _] a " 2 = " 2 conro.{ EXPAND I5 ' GUTPUT E KeE E K=E TAHT ros rp 4 SF rp 4 5 or 92cs - 26372 INPUTS 4 dy nls Veo L Veo L 8 +8 Vss Vss 35 ie NC =13 NC 213, 00 NC #16 NC =16 92C8-22249 92c5-27806 secs-27507 Multi-Function Expandable Hex Buffer/Converter Hex Butter/Converter Single 8-Channel Analog 8-input Gate inverting Type Non-Inverting Type Multipfexer/Demultiplexer CD4048B (File No. 1124) | CD4049UB (File No. 926) | CD4050B (File No. 926) | CD4051B (File No. 902) File No. = commercial data sheet 12-236High Reliability CD4000B-Series CMOS ICs Functional Diagrams ayn CHANNELS IN/OUT nye CHANNELS: IN/OUT CONTROL nye COMMON OUT/IN COMMON OUT/IN 92CS - 26373 Differential 4-Channel Analog ox OR ay OUT/IN bx OR by OUT/IN ex OR cy OUT/IN 92CS - 2270BRI Tripte 2-Channel 12-237 Multiplexer/Demultiplexer Multiplexer/Demultiplexer CD4052B (File No. 902) CD4053B (File No. 902) a4 ao 10 as oe far 4 WORDS 4 no 13] G6_(4) a3 15 14-ST. R RIPPLE, 87 6) ey re COUNTER reece (4) ciapors wee ae AND 22443) loscILLATOR| gio 0 4 #10) rae wORD"B. eB 4] Vgg78 a3.) as oon 846 Vpp"16 Vgg=8 + @ 920S-24516R! Fo 92CS8-29073RI 14-Stage Ripple-Carry Binary Counter/Divider and Oscillator 4-Bit Magnitude Comparator CD4060B (File No. 1120) CD4063B (File No. 805) LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Functional Diagrams ! 14 IN/OUT J t*Vpp NH. 2 2. - = Thy =] Petes outsin 24 pS. CONT 1 c ay te ao tu-5 O | 94S 3 5 Pe: 67.8 o_____+ TC ouT/in 2 }2 conT ! | E 2S ) . . 1 9 > 8 25 SIG B | 1 Oe 14 OUT/IN a i JsABODEFGH vee insoutT 4 LL insouT iwour ! \ ro 42 K=A-B-C-D-E-F-G-H el! 10. aE SIG 0 | Vpp #14 3 12 oF conT 8 33 HO. out iN 1S oL__+r me ot Vgg <7 Vpo7!4 vee #2 S20S- 2492481 6 ,8=NO CONNECTION V8S"7 sees-ea737K2 conT 8 LS. ouT/IN sw SIG 92cS-234874R3 7 c 8 Vss 1 1N/OUT 92CS-21627 16-Channel Quad Bilateral Switch Multiptexer/Demultiplexer 8-Input NAND/AND Gate Hex inverter CD40668 (File No. 1114) CD4067B (File No. 909) CD4068B (File No. 809) CD4069UB (File No. 804) Yoo Vpo pp ' ad ls lua 21) 7 A at eX 4 8 2 9 pst) >>" A J ef Tt 8] 8 rot) >t o 04 6 Lt ny . e e+ | 4, 6 sl) > F H F K F s| AJ AGB 3H e \ Par K=c@D : Vs *7 y 2 | Wy lou Voo*!4 sacs. 2as6eRz 6 7 6 wf pt Vss 928-27686 [7 Vss Vss 9208-27685 92CS-27571 Quad Exclusive-OR Gate Quad 2-Input OR Gate Duai 4-Input OR Gate Triple 3-Input AND Gate CD4070B (File No. 910) D40718 (File No. 807) CD4072B (File No. 807} CD4073B (File No. 806) Yoo DATA INPUT OUTPUT DISABLE DISABLE ; 14 A 3 B al) Pe 5 > =| J) D>y** 8 Ss] 4D-TYPE e& 10 A at) eye F ANDUOR 6% " e K LOGIC 4 o! ) >t M D _ ___ J=Aa@e M=G@H I K 383 L EF K RESET yss fs s o2e8-2ae05R 920$- 2449 7R3 55 92CS-27687 Tripte 3-Input OR Gate 4-Bit D-Type Register Quad Exclusive-NOR Gate CD4075B (File No. 807) CD40768: (File No. 903) Cb4077B (File No. 910) Fite No. = commercial data sheet 12-238High Reliability CD4000B-Series CMOS ICs Functional Diagrams oom, 2 3 4 5 9 ES A+BECHDFEtF+G+H KeAt+BtC+DtE+F+G+H 6,8=NC Voo=l4 mroum Vss = 7 920S - 23877R4 ss 9208-27583 xroOnmPrOaoro 7 Vss, 928-27570 INHIBIT] 10 E = INHIBIT +AB+CD LOGIC 1= HIGH LOGIC OFLOW 92CS- 23890R2 Dual 2-Wide, 2-input AND-OR-INVERT (AO!) 8-Input NOR/OR Gate Quad 2-Input AND Gate Dual 4-Input AND Gate Gate CD4078B (File No. 810) | CD4081B (File No. 806) | CD4082B (File No. 806) | CD4085B (File No. 811) 10 INHIBIT/ Exe -_] BINARY RATE A ! cLOck a2 9 INHIBIT {CARRY} IN 12 7 15 setro | 78IT 3 15 | BinaRY RATE 5 , 4 OUTPUTS E COUNTER -& CLEAR 8 LOGIC t= HIGH hs" our LOGIC 0 =LOW 7 = Van 214 L, INHIBIT(CARRY) OUT H 5D Vpp< t6 Veg *7 ENABLE/EXP NCE4 Vsg78 9208-25004R) J= INH + ENABLE + AB+CD+ EF +GH 920$-238 7ORI Expandable 4-Wide, 2-Input AND-OR-INVERT (AOI) Gate Binary Rate Multiplier CD4086B (File No. 812) CD4089B (File No. 1003) J2RB OUTPUTS SET 13 ser 13 DAA _20"e-stace [2-os at $ a2 5 SHIFT Ls Ls CLOCK 3) Register o's o2{ aQta oe} obk=o w cLock 2 _ cL CLOCK 2 cL 8-BIT KI 6 I _l6 = STROBE 1) vO PAGE Ko 10 kK af&a x2 10 K aa REGISTER 32 R xa 2 R kK M 2 2 = u RESET Yop = 14 RESET Yoo " OUTPUT Vpp = 16 Vss = 7 Vss * c L ENABLE |S] 3-STATE | yoo 2g NG =I NC =I OUTPUTS 92CS 24427RI 92C8- 24430R1 F PARALLEL OUTPUTS QI-O8 M=6-H E (TERMINALS 4,5, 6, 7,14, 13, (2,1, RESPECTIVELY) 92CS 24564R1 92CS-23880 Gated J-K Master-Slave Gated J-K Master-Slave Quad 2-Input NAND 8-Stage Shift-and-Store Flip-Flop, Non-Inverting Flip-Flop, inverting and Schmitt Trigger Bus Register Inputs Non-inverting Inputs CD4093B (File No. 836) | CD4094B (File No. 869) | CD40958 (File No. 879) | CD4096B (File No. 879) File No. = commercial data sheet 12-239 LOGIC CIRCUITSHigh Reliability CD4000B8-Series CMOS ICs Functional Diagrams 1NH 3 1 OF & DECODERS cx Rx Voo Rx Cy (1) Yop7'6 vss-8 8-Bit Addressable Latch g2csz2292IR1 Strobed Hex Inverter/Buffer Q5 06 o ot o | +TR x ~~ i} -TR x I | OUT/IN iwrouT ~ | RESET 7 ot! oo6 +TR ' TH ty -TR Y l OUT/IN RESET InvouT+] | ~| t 7 i Vpp 724 Vsg 712 9208 -24980R2 Vpp =!6 VbDD Vgs=8 Cx2 Rxe 92CS-24253R1 Differential 8-Channei Dual Monostable Multiplexer/Demultiplexer Multivibrator C04097B (File No. 909) CD4098B (File No. 979} 4 THREE~STATE ' WRITE DISABLE ] ao OUTPUT DISABLE DATA 3 a DISABLE a L a2 SNHIBIT 5ID, A Q3 ot Ql ol AOE, 6} T fs 6 aq a1 FS [sos a2 oz + E ney RI | & [Pos RESET s a7 03 6 Vop 716 b3 Vggr8 gacs-24425R1 04 D4 DS 12 D 15 16*Vpp 8*Vss g2cs-32392R1 Hex Buffer Non-Inverting Type Vee PIN | SELECT TTL /CMOS Vop 7 PIN 16 3 MODE SELECT Vgg * PIN 8 92S-39309 Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation CD4504B (File No. 1846) CD4099B (File No. 948) | CD4502B (Fite No. 1002) CD4503B (File No. 1224) vec oo 4- Bit [| 3-sTATE LATCH our IN LEVEL (3,5,7,9)1,141 SHIFTER (2,4,6,10,12,15) 92cs-27494R1 Dual 4-Bit Latch CD4508B (File No. 1009) File No. = commercial data sheet 12-240High Reliability CD4000B-Series CMOS ICs Functional Diagrams x BLE 4 : 6 Fi } 1 p22 92 pS Sos 2 D p4 p a4 e 6 Vpn 116 1s oD sto Vss@ e up/pown !2) 7 R CARRY INCl CARRY OUT 9 RESET ] Vgg"8 92CS- 25083R2 9208-24624 Vpp*!6 BCD Presettable Up/Down BCD-to-7-Segment Counter Latch Decoder Driver CD4510B (File No. 899) CD4511B (File No. 901) 3-STATE DISABLE Vpn 24 DD* it INHIBIT Ly io} Is) Vgg#l2 <= = oo -1 +o $2 o1-2 HS 83 o2-3 tte s4 CHANNEL (03-4 J ata 1 2 A H-&-ss INPUTS )D4-5 t4 SELECT 5 3 B Tra 86 05-6 [ ouTpuT patazS1 route] 4 7016 Hig 87 oe~ 7 pata 3-2! nn 738 o7-9 ~ 4 $9 22 20 sevect a-I \e DATA4 ==44 22 s10 8~-12 Vop* 1h t+ sil CONTROL (rH ves" 8 STROBE H's sia co4si2e Lis Sig 5. = sis 92CS- 28929 innieit 23 __] B2CS - 24597 4-Bit Latch/4-to-16 8-Channel Daia Select Line O . innel Data lor . CD4514B (File No. 814) CD4515B {File No. 814) CD4512B (File No. 1032) Output High on Select Output Low on Select PRESET CLOCK a-pit CLOCK A 0 2 ola - + Enaete DATADID SHIFT | his taza Pl WRITE REGISTER 2 c 5 aaa ENAI ENABLE A 6 gaa 2 tisy] etoy} 20e)] 5010) R x WE = 0-- 016---032---048---064 resera P WE= |----DI7---D33---D49-HiZ clock 8 \OF 2 SHIFT REGISTERS. TERM.Nos. a +10, [aae cLocK IN PARENTHESES ARE FOR 2 NO HALF 10 16 fo UP/DOWN Yop" 16 Vs" 8 ENABLE 8 CARRY IN 9208-3037) RESET 8 RESET 8 925-24506R1 92CS- 24824 Dual Up Counter CD4518B (File No. 808) Binary Presettable Up/Down BCD Counter Duai 64-Bit Shift Register D4520B (File No. 808) CD4516B (File Na. 899) CD4517B (File No. 1148) Binary File No. = commercial data sheet 12-241 LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Functional Diagrams Sif SELECT Q2 INPUTS srmoae ENCODER Ql CLocK a 152 3 f CASCADE PRIORITY 90 2 Liti fe SELECT INHIBIT RATE. (CARRY TINH} = 19 RATE OUTPUTS SETTO, | secect [607 NINE 4.) 0 LOGIC u ouT crear 3] 5 E R rat "9" ouT 7 INHIBIT [CARRY) OUT Yop: 16 92CS -24913R1 Vpp='6 Vss=8 Vss-8 92CS-26360RI BCD Rate Multiplier 8-Bit Priority Encoder CD4527B (File No. 1006) CD4532B (File No. 876) 8 BYPASS O A 8 E A gr [SIRCES 9:24 2 STAGES z t-8 | Losic] log - goal td : ea so AG . 92CS-229i0R 92cS229198% R 4 ELECT e O-L vecove fECODE CLOCK MONO oS] . WHIT Ypp*'6 ss"8 9208-30375 Dual Binary-4o-1-of-4 Dual Binary-to-1-of-4 Decoder/Demuittiplexer Decoder/Demuttipiexer Programmabie Timer Output High on Select Output Low on Select CD4536B (File No. 1186) CD4555B (File No. 858) | CD4556B (File No. 858) File No. = commercial data sheet 12-242High Reliability CD4000B-Series CMOS ICs Functional Diagrams 10 14 4 ex! Rx! ao WRITE DISABLE |_ ao I ANA oo age | Al pata _5} 5a) " worD"a"4 no 6 1) 2] Rxext az 8 ! A 7 4 13 A070 03 wf 2 paws | azl'e, Lal fee vm-$ Ea CASEADIN ae [t2 sep a2 oO. u O85 -1R 3 MONO) x > R s as RESET +O) ra og RESET 8 a7 woros" | 8! 7 82 74 Yor -sasT2 a3 Vgg*8 secs etrl2 }1!0 92 pp"! Vg578 -TR-l! MONOg 5 92CS-30375 RESET |413 a3 iS] 14] Rx Cx (2) Vpp 26 tt ANA- VDD Vgg28 Cx2 Rx2 92CS- 24253R1 Dual Precision + 8-Bit Magnitude Comparator 8-Bit Addressable Latch Monostable Multivibrator CD4585B (File No. 1146) | CD4724B8 (File No. 1111) CD14538 (File No. 2098) INHIBIT QUTPUT SON ROL 3 15 SFE ENABLE \ 13 Voor!4 oAFE vo 2 15 a9 SHIFT SHIFT . I in RISHT RIGHT oy, | OF 1 Vss7 Sauce o 4 14 ay tt 12 f cLR 02-3 13 os LOCK | oe? EVEN vAM 03 6 2_ os 3 8 2 clock SHIFT os sof Ds r 42 leet 7 INHIBIT LEFT ouTPU | LEFT __ 7] =I 3 out | paf>ey cc ) | e-stace SHIFT SHIFT RIGHT 2 LEFT D510 > 1 DOWN n " 6 Vop=!6 ari | COUNTER | coyz0 i NCo1.5,7, SD Vgg28 06 Ii | > con aOGK a om { 10) REGIRCULATE v7 2 Pe /-f >~6 T CONTROL OUTPUT 92CS- 266IRI CLOCK DBS 4 > 92CS- 27567 Vpp #16 os 5 [>e- Veg" 8 sece-o7s07 8-Si Pp; bie 92CS- 24 BIGRZ Synchronous Down Counter 32-Stage Static CD40102B (File No. 984) 4-Bit Bidirectional Left/Right Shift 2-Decade BCD Universal Shift Register Register 9-Bit Parity Generator/Checker es iy | CD40103B (File. No. 984) CD40104B, CD40194B CD40100B (File No. 980) CD40101B (File No. 1000) 8-Bit Binary (File No. 1220) Fite No. = commercial data sheet 12-243 LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Functional Diagrams 3-STATE 2 _ CONTROL ] A ok vo -44 3 a0 oF 2s HZ oo) B 3 4 HB p2 8] ! oe D> b3 4 [HO a3 c 5 i 6 be SHIFT IN 24 [4 BATA-OUT > : SHIFT ouT!S] [2 oATA-IN D 323 READY 9 Yoo = 16 Ub a 10 MASTER & KE RESET Vss- 8 92CS27282R2 ->!3 a> > 2a Yoo" 4 Vsg*7 92CS- 28662 FIFO Register . Hex i 4-Bits Wide by 16-Bits Long Schmitt Trigger j CD40106B it CD40105B (File No. 1044) (Fite No. 1017) es WRITE -_ ENABLE 3-STATE A waiFk 8 5 {s 2(4) 20 a v: bpo F 20 $s 19 5 pata | [?! | word a INPUTS} g28 [8.2 [ ouTPuT os [7 os 5(9) DE 8 pre wRITE 0 4 rane 2 Ee ry write | J 6 (tO) 22 Vss READ 1A 4 a 13 a1 92cs-29434R2 READ OA 2 oe WORD 8 Ves 74(7) reap ip 2 og NOTE : nea } NUMBERS IN PARENTHESES 0 08 a FOR CD40107BF, OTHERS 16 FOR CD40I07BE. Ypo=24 cr oeK S-STATE B Vgg =12 Dual 2-Input NAND 92CS- 24819R2 Buffer/Driver 4-by-4 Multiport Register CD40107B (Fite No. 1015) CD40108B (File No. 1011) Vee Yoo la E CLK UP 9 Is b ja Ieee [rE tNPUT CLK ON 7 B 8 & 3,6,10,14 LEVEL - B Voc | SHIFT ourpuT, 3 RESET _5 3 t | O 4,5,1, g 6 | ERASLE 4 Vss 00 11 BORROW OF 4 | LATCH }-_ [T INDEPENDENTLY ENABLED Vs ENABLE 6 10 CARRY LEVEL SHIFTERS Vpnt'6 ENABLE Vgg*8 2,7,9,15 9205-31375 Vee 7 ss NC#I2 Vop=!6 Vsg578 Yss Vec=! 92CS 26669RI Quad Low-to-High Voltage Level Shifter CD40109B (File No. 1018} Decade Up-Down Counter/ Decoder/Latch/Driver CD40110B (File No. 1125) File No. = commercial data sheet 12-244High Reliability CD4000B-Series CMOS ICs Functional Diagrams 9 to 23 | | PRIORITY eco [+c 22 | | SELECT ENCODER | 2! ol A 2 92CS-30552 10-Line-to-4-Line BCD Priority Encoder CD40147B (File No. 1117) PE } al te 0 CLEAR d 3 a2 Toan 2q clock 24 [2 os Pr 4 p2 4 Jt og p3 54 eat] fe cage Vpp?!6 Vss5 =8 92CS - 28626RI Synchronous 4-Bit Counter D40160B (File No. 1047) Decade with Asynchronous Clear CD40161B (File No. 1047) Binary with Asynchronous Clear CD40162B (File No. 1047) Decade with Synchronous Clear CD40163B. {File No. 1047) Binary with Synchronous Clear o1 Qi Vsg 8 Vpp = 16 92cS~29231 Hex D Type Flip-Flop CD401748 (File No. 1031) DI qi as 4 b2 03 D4 ae as cLock CLEAR Vgg *8 Vop7!6 9208-34508 Quad D-Type Flip-Flop CD40175B (File No. 1326) FUNCTION SELECT INPUTS | SO[SI|$2]s3 645) 4)3 AO 2 9 FO =O = word) AL 2y bo FL | oureur 71m 21 FB | FUNCTION Be ps Fs mB 13 FS Bg 5 fo | \4_A=B COMPARE med oe [ our wor | =O S| B20 16 Cn 4.4 RIPPLE ==9 |} CARRY Beg OUT c x CARRY IN = pi? Sy LooK = + AKEAD move = M 8 bP | carry CONTROL. OUTPUTS Vpp =24 92CS-24825Ri Vgg = #2 Active-Low Data CD40181B FUNCTION SELECT INPUTS $l 83 OUTPUT WORD FUNCTION 14 A=8 COMPARE OUT WORD, RIPPLE 8 n+4 cARRY OUT c CARRY IN i bem MODE 15 CARRY CONTROL OUTPUTS Vpp 24 Veg +12 9208-26387R2 4-Bit Arithmetic Logic Unit Active-High Data (File No. 989) File No. = commercial data sheet LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Functional Diagrams = 3 PRESET RESET s9 9 ENABLE |: 3{aa is ui. po 2. 5 oo wtg 2 wT > pi 4 4 gy a89 ra Ca+x 0 le os oz 4 12 oe gl > 6 12 Pod 9 a aad wa 2 04 es He 93 _lm 29 ntZ clock up -% 3 BORROW weeFT_7 Py 5 IS. clock own 4 L2 CARRY suet pq be z nESET | 14 Vopr na Co 10 Vgg78 move |S0___9] CARRY IN p & ss sevect 340 Yop * 16 Vpp= '6 92CS- 2756IR) oo] Vg 8 Vss=8 92CS-24826R1 I" CLOCK 92CS-24822R2 Presettable Up/Down Counter (Dual Clock with Reset) Cp401928 (File No. 993) 4-Bit Universal Bidirectional Shift Look-Ahead Carry Generator BCD Register with Asynchronous Master Reset CD40193B (File No. 993) CD40182B (File No. 1008) Binary CD40194B (File No. 1220) WRITE ENABLE ENABLE A gage lis Is a po ~29) +20 ar2 Ig Ea 81 4 4 ny pata | 1 ol | woro a 5 INPUTS] 2/8 | [8 g2 [ output az 7 7 az & tne D 2 93 aa! WRITE O 83 12] 953 wriTe 1 aq 4 la Ea ea 13 24 READ 1A 23 T READ 0A4-~+ WORD B Vop #6 }2o2 | OUTPUT geitct Vss*8 u 1 READ iB ] p_ 3 92s-27320 READ op% 16 ai Vpp*24 crock ENABLE B Vgg 12 92CS-28549RI Quad 2-Line-to-1-Line 4-by-4 Multiport Register Data Selector/Multiplexer CD40208B {File No. 1007) CD40257B (File No. 982) File No. = commercial data sheet 12-246Static Burn-in Test Circuit Connections For Type A devices, use Vo NOTE: Each pin except Voo and Vss must (of 16-pin) or pin 12 (of 24-pin), while Vpo is at the highest- p = 12.5V. For Type B and UB devices, use Von = 18V. have resistors of 2-47 kilohms. In most cases, Vss is at pin 7 {of 14-pin IC), pin & numbered pin; exceptions are noted by an asterisk (*). High Reliability CD4000B-Series CMOS ICs STATIC BURN-IN | STATIC BURN-IN II TYPE OPEN GROUND Voo OPEN GROUND Vop CD4000 1,2,6,9,10 3-5,7,B,11-13 14 1,2,6,9,10 7 3-5,8,11-14 CD4001 3,4,10,11 1,2,5-9,12,13 14 3,4,10,11 7 1,2,5,6,8,9, 12-14 cD4002 1,6,8,13 2-5,7,9-12 14 1,6,8,13 7 2-5,9-12,14 CD4006 28-13 1,3-7 14 2,8-13 7 1,3-6,14 GD4007 1,5,8,12,13 3,4,6,7,9,10 2,11,14 1,5,8,12,13 4,79 2,3,6,10,11,14 cbD4008 10-14 1-9,15 16 10-14 8 1-7,9,15,16 CD4009* 2,4,6,10,12, 3,5,7-9,11,14 10,160 2,4,6,10,12,13,15 8 1,3,5,7,9,11, 13,15 14,160 CD4010* 2,4,6,10,12, 3,5,7-9,11,14 10,160 2,4,6,10,12,13,15 8 1,3,5,7,9,11, 13,15 14,160 cb4011 3,4,10,11 1,2,5-9,12,13 14 3,4,10,11 7 1,2,5,6,8,9,12-14 cp4012 1,6,8,13 2-5,7,9-12 14 1,6,8,13 7 2-5,9-12,14 cp4013 1,2,12,13 3-11 14 1,2,12,13 7 3-6,8-11,14 cp4014 23,12 1,4-11,13-15 16 23,12 8 1,4-7,9-11,13-16 C04015 2-5,10-13 1,6-9,14,15 16 2-5,10-13 8 1,6,7,9,14-16 CD4016 2,3,9,10 1,4-B,11-13 14 2,3,9,10 7 1,4-6,8,11-14 cD4017 1-7,9-12 8,13,15 14,16 1-7,9-12 8,14 13,15,16 CD4018 4-6,11,13 1-3,7-9,59),12, 16 4-6,11,13 8 1-3,7,9,10,12 14,15 14-16 CD4019 10-13 4-9,14,15 16 10-13 8 1-7,9,14-16 CbD4020 1-7.9,12-15 8,10,11 16 1-7,9,12-15 8 10,11,16 cD4021 2,3,12 4,4-11,13-15 16 2,3,12 8 4. 4,4-7,9-11,13-16 cpae22 1-79-12 8,13,15 14,16 1-7,9-12 8,1 13,15, 16 : Cb4023 6,9,10 4-5,7,8,11-13 14 6,9,10 7 1-5,8,11-14 Cp4024 3-68-13 1,2,7 14 3-68-13 7 1,2,14 CD4025 6,9,10 1-5,7,8,11-13 14 6,9,10 7 1-5,8,11-14 CD4026 4-7,9-14 1-3;8,15 16 4-7,9-14 8 1-3,15,16 CD4027 1,2,14,15 3-13 16 1,2,14,15 8 3-7,9-13,16 Cb4028 1-7,9,14,15 8,10-13 16 1-7,9,14,15 8 10-13,16 CbD4029 2,6,7,11,14 1,3-5,8-10,12, 16 2,6,7,11,14 8 1,3-5,9,10,12,13 13,15 15,16 CD4030 3,4,10,11 1,2,5-9,12,13 14 3,4,10,11 7 1,2,5,6,8,9,12-14 CD4031 3-7,9,11-14 1,2,8,10,15 16 3-7,9,11-14 8 1,2,10,15,16 cD4033 4-7,9-13 1-3,8,14,15 16 4-7,9-13 8 1-3,14-16 CD4034 1-8 12,15-23 9-11,13,14,24 1-8 12 9-11,13-24 CD4035 1,13-15 2-12 16 1,13-15 8 2-7,9-12,16 cp4040 1-7,9,12-15 8,10,11 16 1-7,9,12-15 8 10,11,16 cp4041 1,2,4,5,8,9,11,12 3,6,7,10,13 14 1,2,4,5,8,9,11,12 7 3,6,10,13,14 cp4042 1-3,9-12,15 4-8,13,14 16 1-3,9-12,15 8 4-7,13,14,16 CD4043 1,2,9,10,13 3-B8,11,12,14,15 16 1,2,9,10,13 8 3-7,11,12,14-16 cpa4a44 1,2,9,10,13 3-8,11,12,14,15 16 1,2,9,10,13 8 3-7,11,12,14-16 CD4046 1,2,4,6,7,10,11, 3,5,8,9,14 12,16 1,2,4,6,7,40,11, 8 3,5,9,12,14,16 13,15 13,15 CbD4047 1,2,10,11,13 3-9,12 14 1,2,10,11,13 7 3-6,8,9,12,14 *Non-standard pin arrangement, or multiple supply pins; connect pins marked () without using resistor. 12-247 LOGIC CIRCUITSStatic Burn-In Test Circuit Connections High Reliability CD4000B-Series CMOS ICs STATIC BURN-IN I STATIC BURN-IN II TYPE OPEN GROUND Vop OPEN GROUND Voo cD4048 1 2-15 16 1 8 2-7,9-16 CD4049* 2,4,6,10,12, 3,5,7-9,11,14 10,166 2,4,6,10,12, 8 10,3,5,7,.9.11, 13,15 13,15 14,166 CD4050" 2,4,6,10,12, 3,5,7-9,11,14 10,160 2,4,6,10,12, 8 10,3,5,7,9,11, 13,15 13,15 14,166 CD4051" 3 1,2,4-6,70,86, 16 3 7,80 1,2,4-6,9-16 9-15 CD4052* 3,13 1,2,4-6,7,8, 16 3,13 7e,Be 1,2,4-6,9-12, 9-12,14,15 14-16 CD4053* 4,14,15 4-3,5,6,70,80, 16 414,15 7o8e 1-3,5,6,9-13,16 4 a3 _ _ / | ~cba4060 1-7,9,10,13-15 8,11,12 16 4-7,9,10,13-15 8 11,12,16 CD4063 5-7 1,2,4,8-15 3,16 5-7 3,8 1,2,4,9-16 CD4066 2,3,9,10 1,4-8,11-13 14 2,3,9,10 7 1,4-6,8,11-14 CD4067 1 2-23 24 1 12 2-11,13-23 cD4068 1,6,8,13 2-5,7,9-12 14 1,6,8,13 7 2-5,9-12,14 CD4069 2,4,6,8,10,12 1,3,5,7,9,11,13 14 2,4,6,8,10,12 7 1,3,5,9,11,13,14 cD4070 3,4,10,11 1,2,5-9,12,13 14 3,4,10,11 7 4,2,5,6,8,9,12-14 cp4o71 3,4,10,11 1,2,5-9,12,13 14 3,4,10,11 7 1,2,5,6,8,9,12-14 cD4072 1,6,8,13 2-5,7,9-12 14 1,6,8,13 7 2-5,9-12,14 CD4073 6,9,10 1-5,7,8,11-13 14 6,9,10 7 1-5,8,11-14 cD4075 6,9,10 1-5,7,8,11-13 14 6,9,10 7 4-5,8,11-14 CD4076 3-6 1,2,7-15 16 3-6 8 4,2,7,9-16 CD4077 3,4,10,11 1,2,5-9,12,13 14 3,4,10,11 7 4,2,5,6,8,9,12-14 cD4078 1,6,8,13 2-5,7,9-12 14 1,6,8,13 7 2-5,9-12,14 CD4081 3,4,10,11 1,2,5-9,12,13 14 3,4,10,11 7 4,2,5,6,8,9,12-14 cD4082 1,6,8,13 2-5,7,9-12 14 1,6,8,13 7 2-5,9-12,14 CD4085 3.4 1,2,5-13 14 3,4 7 +,2,5,6,8-14 cD4086 3,4 1,2,5-13 14 3,4 7 4,2,5,6,8-14 cD4089 15-7 2-48-15 16 1,5-7 8 2-49-16 cD4093 3,4,10,11 1,2,5-9,12,13 14 3,4,10,11 7 1,2,5,6,8,9,12-14 cD4094 4-7,9-14 1-3,8,15 16 4-7,9-14 8 1-3,15,16 CD4095 1,68 2-5,7,9-13 14 1,68 7 2-5,9-14 CD4096 1,68 2-5,7,9-13 14 1,68 7 2-5,9-14 CD4097 417 2-16,18-23 24 1,17 12 2-11,13-24 cD4098 2,6,7,9,10,14 4,3-5,8,11-13,15 16 2.6,7,9,10,14 1,8,15 3-5,11-13,16 cp4099 1,9-15 2-8 16 1,915 8 2-7,16 cD4502 2,5,7,9,11,14 1,3,4,6,8, 10,12, 16 2,5,7,9,11,14 8 1,3,4,6,10,12,13 13,15 15,16 cD4503 3,5,7,9,11,13 1,2,4,6,8,10,12, 16 3,5,7,9,11,13 8 1,2,4,6,10,12, 14,15 14-16 CD4504 2,4,6,10,12,15 3,5,7-9,11,14 16 (16,13)! 2,4,6,10,12,15 8 16 (1,3,5,7,9, 11,13,14)! CD4508 5,7,9,11,17,19, 1-4,6,8,10, 24 5,7,9,11,17,19, 12 1-4,6,8,10,13-16, 21,23 12-16,18,20,22 21,23 18,20,22,24 CD4510 2,6,7,11,14 1,3-5,8-10,12, 16 2,6,7,11,14 8 1,3-5,9,10,12, 13,15 13,15,16 cp4511 9-15 1-8 16 9-15 8 1-7,16 CD4512 14 1-13,15 16 14 8 1-7,9-13,15,16 *Non-standard pin arrangement, or multiple supply pins; connect pins marked () without using resistor. 1Pin voltage is Von/2 for pins inside parentheses. 12-248High Reliability CD4000B-Series CMOS ICs Static Burn-in Test Circuit Connections STATIC BURN-IN I STATIC BURN-IN It TYPE OPEN GROUND Vop OPEN GROUND Voo cD4514 4-11,13-20 1-3,12,21-23 24 4-11,13-20 12 1-3,21-24 CD4515 4-11,13-20 1-3,12,21-23 24 4-11,13-20 12 1-3,21-24 CD4516 2,6,7,11,14 4,3-5,8-10, 12, 16 2,6,7,11,14 8 1,3-5,9,10,12, 13,15 13,15,16 CD4517 1,2,5,6,10,11, 3,4,7-9,12,13 16 1,2,5,6,10,11, 8 3,4,7,9,12, 14,15 14,15 13,16 CD4518 3-6,11-14 1,2,7-10,15 16 3-6,11-14 8 1,2,7,9,10, 15,16 D4520 3-6,11-14 1,2,7-10,15 16 3-6,11-14 8 1,2,7,9,10, 15,16 CD4527 15-7 2-4,8-15 16 15-7 8 2-4,9-16 CD4532 6,7,9,14,15 1-5,8,10-13 16 6,7,9,14,15 8 1-5,10-13,16 CD4536 45,13 1-3,6-12,14,15 16 45,13 8 1-3,6,7,9-12, 14-16 CD4555 4-7,9-12 1-3,8,13-15 16 4-7,9-12 8 1-3,13-16 CD4556 4-7,9-12 1-3,8,13-15 16 4-7,9-12 8 1-3,13-16 CD4585 3,12,13 1,2,4-11,14,15 16 3,12,13 8 1,2,4-7,9-11, 14-16 cp4724 4-7,9-12 1-3,8,13-15 16 4-7,9-12 a 1,3,13-16 CD14538 2,6,7,9,10,14 1,3-5,8,11-13,15 16 2,6,7,9,10,14 1,8,15 3-5,11-13,16 CD40100 1,4,5,7,10,12,14 2,3,6,8,9,11,13 16 1,4,5,7,10,12, 8 2,3,6,9,11, 15 14,15 13,16 CD40101 69 1-5,7,8,10-13 14 69 7 1-5,8,10-14 CD40102 14 1-13,15 16 14 8 1-7,9-13,15,16 CD40103 14 1-13,15 16 14 8 1-7,9-13,15,16 CD40104 12-15 1-14 16 12-15 8 1-7,9-11,16 CD40105 2,10-14 1,3-9,15 16 2,10-14 8 1,3-7,9,15,16 CD40106 2,4,6,8,10,12 1,3,5,7,9,11,13 14 2,4,6,8,10,12 7 1,3,5,9,11, 13,14 CD40107 1,2,5,6,8,9, 3,4,7,10,11 14 1,2,5,6,8,9,12,13 7 3,4,10,11,14 42,13 CD40108 1,2,4-7,22,23 3,8-21 24 1,2,4-7,22,23 12 3,8-11,13-21, 24 cp4oi0g* | 4,5,11-13 2,3,6-10,14,15 10,16 4.5,11-13 8 (1,2,3,6,7,9,10, 14,15)'16 CD40110 1-3,10-15 4-9 16 4-3,10-15 8 4-7,9,16. CD40147 67,914 1-5,8,10-13,15 16 6,7,9,14 8 1-5,10-13,15,16 CD40160 11-15 1-10 16 11-15 8 1-7,9,10,16 CD40161 11-15 1-10 16 11-15 8 1-7,9,10,16 CD40162 11-15 1-10 16 11-15 8 1-7,9,10,16 CD40163 11-15 1-10 16 11-15 8 1-7,9,10,16 CD40174 2,5,7,10,12,15 1,3,4,6,8,9,11, 16 2,5,7,10,12,15 8 1,3,4,6,9,11,13, 43,14 14,16 *Non-standard pin arrangement, or multiple supply pins; connect pins marked (e) without using resistor. 1Pin voltage is Voo/2 for pins inside parentheses. 2Vpp = 11.5 volts; Vcc = 6.5 volts; use 300 2 resistors at pins 10,13-21. 12-249 LOGIC CIRCUITSStatic Burn-in Test Circuit Connections High Reliability CD4000B-Series CMOS ICs STATIC BURN-IN | STATIC BURN-IN II TYPE OPEN GROUND Voo OPEN GROUND Voo Cb40175 2,3,6,7,10,11, 1,4,5,8,9,12,13 16 2,3,6,7,10,11, 8 1,4,5,9,12,13,16 14,15 14,15 cp40181 9-11,13-17 1-8,12,18-23 24 9-11,13-17 12 1-8,18-24 cD40182 7,912 1-6,8,13-15 16 7,9-12 8 1-6,13-16 CD40192 2,3,6,7,12,13 1,4,5,8-11,14,15 16 2,3,6,7,12,13 8 1,4,5,9-11, 14-16 cD40193 2,3,6,7,12,13 1,4,5,8-11,14,15 16 2,3,6,7,12,13 8 1,4,5,9-11, 14-16 cp40194 12-15 1-11 16 12-15 8 1-7,9-11,16 CD40208 1,2,4-7,22,23 3,8-21 24 1,2,4-7,22,23 12 38-1 1,13-21, 2 CD40257 4,7,9,12 1-3,5,.6,8,10,11, 16 4,7,9,12 8,15 1-3,5,6,10,11, 13-15 13,14,16 Dynamic Burn-in Test Circuit Connections TYPE OPEN GROUND 1/2 Von Voo OSCILLATOR 50 kHz 25 KHz CD4000 1,2 7 69.10 14 3-5,8,11-13 cD4001 = 7 3,4,10,11 14 1,2,5,6,8,9,12,13 CD4002 68 7 1,13 14 2-5,9-12 = CD4006 2 7 8-13 14 3 1,46 CD4007 _ 47,9 1,5,8,12,13 2,11,14 36,10 = cD4008 8 10-14 16 2,4,6,15 1,3,5,7,9 CD4009" 13 8 2,4,6,10,12,15 10,160 3,5,7.9,11,14 CD4010* 13 8 2,4,6,10,12,15 10,160 35,7,9,11,14 cb4011 7 3,4,10,11 14 1,2,5.6,8,9,12,13 cD4012 68 7 1,13 14 2-6,9-12 cb4013 4,6-8,10 1,2,12,13 14 3,11 59 cD4014 1,4-9,13-15 23,12 16 10 1 cD4015 68,14 2-5,10-13 16 19 7,15 cb4016 7 2,3,9,10 14 5,6,12,13 14,811 CD4017 8,13,15 1-7,9-12 16 14 cb4018 2,8,9,15 4-6,11,13 1,3,12,16 7,14 10 cb4019 8 10-13 16 1-7,9,14,15 cb4020 811 1-7,9,12-15 16 10 cb4021 1,4-9,13-15 2,3,12 16 10 11 cb4022 8,13,15 1-7,9-12 16 14 CD4023 7 69,10 14 15,8,11-13 ~ cp4024 8,10,13 27 3-6,9,11,12 14 1 _ cD4025 7 69,10 14 1-5,8,11-13 ~ cD4026 2,B,15 4-7,9-14 3,16 1 CD4027 47-912 1,2,14,15 5,6,10,11,16 3,13 cD4028 8 1-7,9,14,15 16 10,12,13 11 cD4029 _ 1,3-5,8,12,13 2,6,7,11,14 9,10,16 15 CD4030 7 3,4,10,11 14 2,6,9,13 1,5,8,12 CbD4031 3-5,11-14 8,15 67,9 1,16 2 10 *Non-standard pin arrangment, or muitiple supply pins; connect pins marked (#) without using a resistor. 12-250Dynamic Burn-in Test Circuit Connections High Reliability CD4000B-Series CMOS ICs TYPE OPEN GROUND 1/2 Vop Voo OSCILLATOR 50 kHz 25 kHz CD4033 ~ 2,3,8,14.15 4-79-13 16 1 CD4034 _ 1-8,11-14 16-23 9,24 15 10 CD4035 1,3,4 2,5,7-12 13-15 16 6 _ cp4040 811 1-7,9,12-15 16 10 cpaoa1 7 1,2,4,5,8,9,11,12 14 3,6,10,13 cpao42 8 4-3,9-12,15 6,16 5 4,7,13,14 Cp4043 13 8 1,2,9,12 5,16 46,1214 3,7,11,15 cp4044 2 8 1,9,10,13 5,16 4,6,12,14 3,7,11,15 CD4046 1,4,6,7,10,11, 89 2 3.5,12,16 14 43,15 p4047 7,9,12 4,2,10,11,13 45,14 68 3 CD4048 815 1 2,16 9-14 37 D4049* 13 & 2,4,6,10,12,15 10,16 3,5,7,9,11,14 - D4050* 13 8 2,4,6,10,12,15 10,16 3,5,7,9,11,14 _ cp4051* 4-6,70,809, 3 1,2,13,15,16 "W 10 12,14 CD4052* _ 4-6,70,80,12,15 3,13 1,2,11,14,16 10 9g CD4083" 1,5,6,7,80,12 414,15 2,3,13,16 on _ CD4054 708 36 1,10,12,14 2 9.11,13,15 CD4085 708 1,915 16 6 2-5 CD4056 708 15 1,16 6 25 CD4060 8,12 4-7,9,10,13-15 16 " = CD4063 = 1,2,4,8,10,11,13 | 57 3,16 12,15 914 CD4066 ? 2,3,9,10 14 56,12,13 148,11 CD4067 = 12,15 1 24 2-9,16-23 (10,11,13,14) cD4068 68 7 1,13 14 2-59-12 CD4069 7 2,4,6,8,10,12 14 13,5.9,11,13 _ cD4070 7 3,4,10,11 14 1,5,8,12 2.6,9,13 CD4071 7 3,4,10,11 14 1,2,5,6,8,9,12,13 | cD4072 68 7 1,13 14 2-59-12 D4073 7 69,10 14 4-5,8,11-13 cp4075 7 69,10 14 _ 15,8,11-13 CD4076 1,2,8-10,15 36 16 7 14-14 CD4077 7 3,4,10,11 14 1,5,8,12 2,6,9,13 Cb4078 68 7 1,13 14 2-59-12 Cp4081 7 3,4,10,11 14 1,2,5,6,8,9,12,13 | cD4082 68 7 1,13 14 2-5,9-12 cp4085 7 3,4 14 1,2,5,68,9,12,13 | 10,11 CD4086 4 7 3 14 1,2,5,68,9,11-13 | 10 CD4089 2,4,8,10,12-15 157 3,16 9 11 CD4083 7 3,4,10,11 14 4,2,5,689,12,13 | cp4094 8 4-79-14 1,15,16 3 2 CD4095 1 27,13 68 3-5,9-11,14 12 CD4096 1 25,7,9,13 68 3,4,10,11,14 12 CD4097 _ 12,13 1,17 24 2-9,15,16,18-23 | (10,11,14)2 CD4098 1,4,8,12,15 67,9,10 2,14,16 5,11 3,13 *Non-standard pin arrangement, or multiple supply pins; connect pins marked () without using a resistor. Pin 10 is @ 14 kHz; pin 11 is @ 7 kHz; pin 13 is @ 1.7 kHz; pin 14 is @ 3.5 kHz. 2Pin 10 is @ 14 kHz; pin 11 is @ 7 kHz; pin 14 is @ 3.5 kHz. 12-251 LOGIC CIRCUITSDynamic Burn-In Test Circuit Connections High Reliability CD4000B-Series CMOS ICs TYPE OPEN GROUND 1/2 Voo Voo OSCILLATOR 50 kHz 25 kHz CD4099 - 5-8 19-15 16 2,4 3 CD4502 8 2,5,7,9,11,14 16 4 1,3,6,10,12,13,15 CD4503 = 48,15 3,5,7,9,11,13 16 2,4,6,10,12,14 _ CD4504 = 8 10,2,4,6,10,12,15 16 (3,5,7.9,11,14)3 | 13 CD4508 1,3,12,13,15 5,7,9,11,17,19, 2,14,24 46.8,10,16,18, | 24,23 20,22 CD4510 _ 1,3,4,8,9,12,13 26,7,11,14 10,16 15 5 CD4511 O15 58 34,16 127 6 CD4512 = 8,10,15 14 16 1-7,9,11,12 3 CD4514 23,12 4-11,13-20 21,22,24 1 23 CD4515 23,12 4-11,13-20 21,22,24 1 23 CD4516 = 1,3,4,8,9,12,13 2.6,7,11,14 10,16 15 5 CD4517 _ 38,13 1,2,5.6,10,11 14,15 16 4,12 79 CD4518 _ 7,815 3-6,11-14 2,10,16 19 C4520 7,815 3-6,11-14 2,10,16 19 CD4527 2,4,8,10,12-15 157 3,16 9 14 CD4532 = 8 67,9,14,15 5.16 7-4,10-13 CD4536 1,2,6-8,14,15 45,13 312.16 3 _ CD4541 Ait 57 128 9,10,12-14 3 CD4543 68 O15 14,16 2.35 _ CD4555 18,15 47.912 16 2,14 3,13 CD4556 1,8,15 479-12 16 2,14 3,13 CD4585 5-9,11,14,15 3,12,13 1,4,16 2 40 cp4724 1-38 479-12 16 44,15 13 CD14538 14,812.15 67,9,10 2,14,16 51 3,13 CD22100 8 10,11,14,15 7,16 1,3,9,12,13 (2,4-6)4 CD22101 _ 12 45,89,16, 24 3,6,7,10,15 (1,2,11,14,23)5 17,20,21 18,19,22 GD40100 1,5,7,10,14,15 28,13 412 9,16 3 611 CD40101 47 69 12,14 2,3,5,8,10 4,11,13 GD40102 38,15 14 2,16 1,4,6,11,13 5,7,9,10,12 CD40103 38,15 14 2,16 146,11,13 5,7.9,10,12 GD40104 7,8,10 12-15 1,3-6,9,16 rn 2 GD40105 189 2,10-14 16 3,15 47 GD40106 _ 7 2,4,6,8,10,12 14 1,35,9,11,13 _ CD40107 1,2,6,8,12,13 7 59 14 3,4,10,11 CD40108 _ 12 1,2,4-7,22,23 3,15,16,21,24 8,11,14,19,20 9,10,13,17,18 CD40109 12 8 10,4,5,11,13 16 (3,6,10,14)5 (2,7,9,15)3 D40110 _ 48 4-3,10-15 16 9 cp40116" _ = D40117 7 368-11 14 42,13 12 D40147 8 67,9,14 16 1,3,11,13 2,45, 10,12,15 CD40160 8 11-15 1,7,9,10,16 2-6 = CD40161 8 11-15 4,7,9,10,16 26 cp40162 _ 8 11-15 1,7,9,10,16 2-6 _ CD40163 _ 8 11-15 1,7,9,10,16 26 cp40174 _ 8 2,5,7,10,12,15 1,16 9 3,4.6,11,13,14 3Pin Voltage is Vpo/2. Pin is @ 14 kHz; Pin 6 is @ 7 kHz; Pin 2 is @ 3.5 kHz. 5Pin 2 is @ 14 kHz; Pin 1 is @ 7 kHz; Pins 14, 23 are @ 3.5 kHz. Non-standard pin arrangement, or multiple supply pins; connect pins marked (#) without using a resistor. 12-252Dynamic Burn-in Test Circuit Connections High Reliability CD4000B~-Series CMOS ICs OSCILLATOR TYPE - OPEN GROUND 1/2 Voo Vop kn 35 KH CD40175 _ 8 2,3,6,7,10,11 14,15 1,16 9 4,5,12,13 CD40181 _ 4-6,8,12 911,13-17 3,24 1,2,18-23 7 D40182 _ 8 7,9-12 16 1-6,14,15 13 040192 _ 8,14 2,3,6,7,12,13 1,5,9-11,15,16 4 _ D40193 _ 8,14 2,3,6,7,12,13 1,5,9-11,15,16 4 _ CD40194 _ 7,8,10 12-15 1,3-6,9,16 1 2 CD40208 _ 12 1,2,4-7,22,23 3,15, 16,2124 8,10,14,19,20 9,11,13,17,18 CD40257 _ 8,15 4,7,9,12 16 F388.10.1 1, 1 13,1 Guide to Burn-in Delta Limits for Level /MS CD4000B-Series CMOS ICs Delta Parameters For the /MS level devices, certain parameters are data- logged and deltas are calculated from pre to post burn-in. These parameters are shown below. aa; Test Conditions Parameters Symbols Vo Vin Voo rma ) (Vv) (Vv) {V) Quiescent Device Current Gates loo _ 0,20 20 0.1HA MSI-1 Types too _ 0,20 20 +Q0.2uA MSI-2 Types loo - 0,20 20 +1.04A Output Low (Sink) Current lou 0.4 05 5 + 20% of initial value Output High (Source) Current lon 46 0,5 5 + 20% of initial value Types with Ron limits Ron _ _ 10V + 20% of instead of lo. and tou initial value 12-253 LOGIC CIRCUITSHigh Reliability CD4000B-Series CMOS ICs Leadless Chip Carrier Pinouts The following table and diagrams show JEDEC standard pinout conversions from 14, 16, 22 and 24 pin leaded FP/DIL packages to 20 and 28 terminal leadless chip carriers. Harris CD4000B-series products offered in leadiess chip carriers are shown below. Pinout Conversion From Leaded Package to Leadless-Chip Carrier FP/DIL Pin 1/;2/3)4/5/6)7 14849 (10111 )12) 13114 [15 | 16/17) 18) 19 | 20) 21) 22 | 23 | 24 Leadiess 2731416] 8 | 9 |10]/12]13]14 | 16 {18} 19 | 20 Chip 27/3 1/4/)5]7 [8 | 9 |10]12[13] 14 |15] 17] 18119 | 20 Carrier 2131/41/51] 6 |] 8 |10}111]12]13] 14 [16] 17 | 18 | 19 | 20 | 22 | 24 | 25 | 26 | 27 | 28 Terminal 213)4/15]6]7 | 9 110111312113] 14} 16/17 118119] 20 | 21 | 23 | 24 | 25 | 26 | 27 | 28 CD4000B-Series Conversion Diagrams Top Views Shown 20-Terminal Leadless-Chip Carriers OO INDEX 20 - TERMINAL CONVERSION FROM 9 10 HW $2 13. O OO 92CS-35333 28-Terminai Leadless-Chip Carriers @ @& INDEX G3) G) | 4 3 2 | 26 27 26 26-TERMINAL CONVERSION FROM 22-PIN CO_ CORCHOS 1 @1@ 92CS-35335 12-254 INDEX QQ) @5) 20-TERMINAL CONVERSION FROM 16-PIN G 9 10 Wl 12 13 OO O 92CS- 35334 4 3 2 | 28 27 26 28-TERMINAL CONVERSION FROM 24-PIN COO COO GQ GOO 12 13 14 15 16 17 16 Ol O1 QO 92C8- 35336