2007-2018 Microchip Technology Inc. DS60001145W- page 1
PIC32
1.0 DEVICE OVERVIEW
This document defines the Flash programming
specification for the PIC32 family of 32-bit
microcontrollers.
This programming specification is designed to guide
developers of external programmer tools. Customers
who are developing applications for PIC32 devices
should use development tools that already provide
support for device programming.
The major topics of discussion include:
•Section 1.0 “Device Overview”
•Section 2.0 “Programming Overview”
•Section 3.0 “Programming Steps”
•Section 4.0 “Connecting to the Device”
•Section 5.0 “EJTAG vs. ICSP”
•Section 6.0 “Pseudo Operations”
•Section 7.0 “Entering 2-Wire Enhanced ICSP
Mode”
•Section 8.0 “Check Device Status”
•Section 9.0 “Erasing the Device”
•Section 10.0 “Entering Serial Execution Mode”
•Section 11.0 “Downloading the Programming
Executive (PE)”
•Section 12.0 “Downloading a Data Block”
•Section 13.0 “Initiating a Page Erase”
•Section 14.0 “Initiating a Flash Row Write”
•Section “”
•Section 16.0 “Exiting Programming Mode”
•Section 17.0 “The Programming Executive”
•Section 18.0 “Checksum”
•Section 19.0 “Con figurat ion Memory and Device
ID”
•Section 20.0 “TAP Controllers”
•Section 21.0 “AC /DC Char acterist ics and Timing
Requirements”
•Appendix A: “PIC32 Flash Memory Map”
•Appendix B: “Hex File Format”
•Appendix C: “Device IDs”
•Appendix D: “Revision History”
2.0 PROGRAMMING OVERVIEW
When in development of a programming tool, it is
necessary to understand the internal Flash program
operations of the target device and the Special
Function Registers (SFRs) used to control Flash
programming, as these same operations and registers
are used by an external programming tool and its
software. These operations and control registers are
describ ed in the “Flash Program Memory” chapter i n
the specific device data sheet, and the related “PIC32
Family Reference Manual” section. It is highly
recommended that these documents be used in
conjunction with this programming specification.
An external tool programming setup consists of an
external programmer tool and a target PIC32 device.
Figure 2-1 illustrate s a typi cal prog rammi ng setup. Th e
programmer tool is responsible for executing
necessary programming steps and completing the
programming operation.
FIGURE 2-1: PROGRAMMING SYSTEM
SETUP
Target PIC32 Device
CPU
On-Chip Memory
External
Programmer
PIC32 Flash Programming Specification
PIC32
DS60001145W-page 2 2007-2018 Microchip Technology Inc.
2.1 Devices with Dual Flash Panel and
Dual Boot Regions
The PIC32MKXXXXXXD/E/F/K/L/M and PIC32MZ
families of devices incorporate several features useful
for field (self) programming of the device. These
features include dual Flash panels with dual boot
regions, an aliasing scheme for the boot regions
allowing automatic selection of boot code at start-up
and a panel swap feature for Program Flash. The two
Flash panels and their associated boot regions can be
erased and programmed separately. Refer to the
Section 48. “Memory Organization and
Permissions” (DS60001214) of the “PIC32 Family
Refe renc e Manua l” for a detailed explanation of these
features.
A development tool used for production programming
will not be con cerned about most of these fea tures with
the following exceptions:
• Ensuring the SWAP bit (NVM CON<7>) is in t he
proper setting. The default setting is ‘0’ for no swap
of pane ls. T he developm ent tool should as sume the
default setting when generating source files for the
programming tool.
• Proper handling of the aliasing of the boot memory
in the checksum calculation. The aliased sections
will be duplicates of the fixed sections. See
Section 18.0 “Che cks um” for mo re inf orm ati on on
checksum calculations with aliased regions
• For PIC32MK devices, using the Erase/Retry
featur e when an attem pt to era se a Fla sh page fai ls
and needs to be r etried. See Section 13.0
“Initiating a Page Erase” for more information.
2.2 Programming Interfaces
All PIC32 devices provide two physical interf aces to the
external programmer tool:
• 2-wire In-Circuit Serial Programming™ (ICSP™)
• 4-wire Joint Test Action Group (JTAG)
See Section 4.0 “Connecting to the Device” for
more information.
Either of these methods may use a downloadable
Programming Executive (PE). The PE executes from
the target device RAM and hides device programming
details from the prog rammer. It also remov es overhea d
associated with data transfer and improves overall data
throughput. Microchip has developed a PE that is
available for use with any external programmer, see
Section 17.0 “The Programming Executive” for
more information.
Section 3.0 “Programming Steps” describes high-
level programming steps, followed by a brief
explanation of each step. Detailed explanations are
available in corresponding sections of this document.
More info rmation on p rogramming c ommands, EJTAG,
and DC specifications are available in the following
sections:
•Section 19.0 “Configuration Memory and
Device ID”
•Section 20.0 “TAP Controllers”
•Section 21.0 “AC/DC Characteristics and
Timi ng Requiremen ts”
2.3 Enhanced JTAG (EJTAG )
The 2-wire and 4-wire interfaces use the EJTAG
protocol to exchange data with the programmer. While
this document provides a working description of this
protocol as needed, advanced users are advised to
refer to the Imagination Technologies Limited web site
(www.imgtec.com) for more information.
2.4 Data Sizes
Data sizes are defined as follows:
• One word: 32 bits
• One-half word: 16 bits
• One -qua rter word: 8 bits
• One Byte: 8 bits
2007-2018 Microchip Technology Inc. DS60001145W- page 3
PIC32
3.0 PROGRAMMING STEPS
All tool programmers must perform a common set of
steps, regardless of the actual method being used.
Figure 3-1 shows the set of steps to program PIC32
devices.
FIGURE 3-1: PROGRAMMING FLOW
The following sequence lists the programming steps
with a brief explanation of each step. More detailed
information about these steps is available in the
subsequent sections.
1. Connect to the target device.
To ensure suc cessful programmin g, all required
pins must be connected to appropriate signals.
See Section 4.0 “Connecting to the Device”
for more information.
2. Place the target device in programming mode.
For 2-wire programming methods, the target
device must be p laced in a s pecial progra mming
mode (Enha nced ICSP™) befo re exec uting an y
other steps .
See Section 7.0 “Entering 2-Wire Enhanced
ICSP Mode” for more information.
3. Check the status of the device.
Checks the status of the device to ensure it is
ready to receive information from the
programmer.
See Section 8.0 “Check Device Status” for
more information.
4. Erase the target device.
If the target memory block in the device is not
blank, or if the device is code-protected, an
erase step must be performed before
programming any new data.
See Section 9.0 “Erasing the Device” for
more information.
5. Enter programming mode.
Verifies that the device is not code-protected
and boots the TAP controller to start sending
and rec eiv in g d ata to and from th e PIC32 CP U.
See Section 10.0 “Entering Serial Execution
Mode” for more information.
Done
Exit Programming Mode
Verify Device
Done
Initiate Flash Write
Download a Data Block
Download the PE
(Optional)
Enter Serial Exec Mode
Erase Device
Check Device Status
Start
Enter Enhanced ICSP™
(Only required for 2-wire)
No
Yes
Note: For the 4-wire programming methods,
Step 2 is not applicable.
PIC32
DS60001145W-page 4 2007-2018 Microchip Technology Inc.
6. Download the Programming Executive (PE).
The PE is a small block of executable code that
is downloaded into the RAM of the target device.
It will receive and program the actual data.
See Section 11.0 “Downloading the
Programming Executive (PE)” for more
information.
7. Download the block of data to program.
All methods, with or without the PE, must
download the desired programming data into a
block of memor y in RAM.
See Section 12.0 “Downloading a Data
Block” for more information.
8. Initiate F lash Write.
After down loa din g eac h bl oc k of dat a into RAM ,
the programming sequence must be started to
program it into the target device’s Flash
memory.
See Section 14.0 “Initiating a Flash Row
Write” for more information.
9. Repeat Step 7 and Step 8 until all data blocks
are downloaded and programmed.
10. Verify the progr am memo ry.
After all programming data and Configuration
bits are programmed, th e target device memory
should be read back and verified for the
matchi ng con ten t.
See Section “” for more information.
11. Exit the programming mode.
The newly programmed data is not effective unti l
either power is removed and reapplied to the
target device or an exit programming sequence
is pe rformed.
See Section 16.0 “Exiting Programming
Mode” for more information.
Note: If the programming method being used
does not require the PE, Step 6 is not
applicable.
2007-2018 Microchip Technology Inc. DS60001145W- page 5
PIC32
4.0 CONNECTING TO THE DEVICE
The PIC32 family provides two possible physical
interfaces for connecting and programming the
memory conten ts, se e Figure 4-1. For all programming
interfaces, the target device must be powered and all
required signals must be connected. In addition, the
interface must be enabled, either through its
Configuration bit, as in the case of the JTAG 4-wire
interface, or though a special init ialization sequence, as
is the case for the 2-wire ICSP interface.
The JTAG interface is enabled by default in blank
devices shipped from the factory.
Enabling ICSP is described in Section 7.0 “Entering
2-Wire Enhanced ICSP Mode”.
FIGURE 4-1: PROGRAMMING
INTERF ACES
4.1 4-wire Interface
One possible interface is the 4-wire JTAG (IEEE
1149.1) port. Table 4-1 lists the required pin
connections. This interface uses the following four
communication lines to transfer data to and from the
PIC32 device being programmed:
• Test Clock Input (TCK)
• Test Mode Select Input (TMS)
• Test Data Input (TDI)
• Test Data Output (TDO)
Refer to the specific device data sheet for the
connection of the signals to the device pins.
4.1.1 TEST CLOCK INPUT (TCK)
TCK is the clock that controls the updating of the TAP
controller and the shifting of data through the Instruc-
tion or selected Data registers. TCK is independent of
the proc es so r c lo ck with respec t t o both frequ enc y an d
phase.
4.1.2 TEST MODE SELECT INPUT (TMS)
TMS is the control signal for the TAP controller. This
signal is sampled on the rising edge of TCK.
4.1.3 TEST DATA INPUT (TDI)
TDI is the test data input to the Instruction or selected
Data re gister. This signa l is s ampl ed on t he risi ng edg e
of TCK for some TAP controller states.
4.1.4 TEST DATA OUTPUT (TDO)
TDO is the t est d ata ou tput fro m the Inst ruction or Da ta
registers. This signal changes on the falling edge of
TCK. TDO is only driven when data is shifted out,
otherwise the TDO is tri-stated.
TABLE 4-1: 4-WIRE INTERFACE PINS
Programmer
2-wire
ICSP™
OR
4-wire
JTAG
+
MCLR, V
DD
CORE
(1)
, V
DDR
1
V
8
(1)
,
PIC32
V
DDIO
, V
SS
, V
SS
1
V
8
(1)
Note 1: This pin is not available on all devices.
Re fe r to th e “Pin Diagrams” or “Pin
Tables” section in the specific device data
sheet to determine availability.
Device Pin Name Pin
Type Pin Desc ription
MCLR I Program mi ng Enab le
ENVREG
(2)
I Enable for On-Chip Voltage Regulator
V
DD
, V
DD
IO
, V
DD
CORE
(2)
, V
DDR
1
V
8
(2)
, V
BAT(2)
,
and AV
DD(1)
P Pow er Supply
V
SS
, V
SS
1
V
8
(2)
, and AV
SS(1)
P Ground
V
CAP(2)
P CPU logic filter capacitor connection
TDI I Test Data In
TDO O Test Data Out
TCK I Test Clock
TMS I Test Mode State
Legend: I = Input O = Output P = Power
Note 1: All power supply and ground pins must be con nected, inc luding ana log suppl ies (AV
DD
) and ground (AV
SS
).
2: This pin is not avail able on all devices. R efer to the “Pin Di agrams” or “Pi n Tables” section in the specific
device data sheet to determine availability.
PIC32
DS60001145W-page 6 2007-2018 Microchip Technology Inc.
4.2 2-wire Interface
Another possible interface is the 2-wire ICSP port.
Table 4-2 lists the required pin connections. This
interface uses the following two communication lines to
transfer data to and from the PIC32 device being
programmed:
• Serial Program Clock (PGECx)
• Serial Program Data (PGEDx)
These signals are described in the following two
sectio ns. Refe r to th e spec ific devic e dat a she et for th e
connection of the signals to the chip pins.
4.2.1 SERI AL PROGRAM CLOCK
(PGEC
X
)
PGECx is the clock that controls the updating of the
TAP controller and the shifting of data through the
Instruction or selected Data registers. PGECx is
independent of the processor clock, with respect to
both frequency and phase.
4.2.2 SERIAL PROGRAM DATA (PGED
X
)
PGEDx is the data input/output to the Instruction or
selected Data Registers, it is also the control signal f or
the TAP c ontr oller. This si gnal is sam pl ed on the fal ling
edge of PGECx for some TAP controller states.
TABLE 4-2: 2-WIRE INTERFACE PINS
Device
Pin Name Programmer
Pin Name Pin Type Pin Description
MCLR MCLR P Programming Enable
ENVREG
(2)
N/A I Enable for On-Chip Voltage Regulator
V
DD
, V
DD
IO
, V
BAT(2)
, and AV
DD(1)
V
DD
P Power Supply
V
DD
CORE
(2)
and V
DDR
1
V
8
(2)
N/A P Power Supply for DDR Interface
V
SS
, V
SS
1
V
8
(2)
, and AV
SS(1)
V
SS
PGround
V
CAP(2)
N/A P CPU Logic Fil ter Capac ito r Con nec tion
PGECx PGEC I Primary Programming Pin Pair: Serial Clock
PGEDx PGED I/O Primary Programming Pin Pair: Serial Data
Legend: I = Input O = Output P = Power
Note 1: All power supply and ground pins must be connec ted, includ ing analog supplies (AV
DD
) and ground (AV
SS
).
2: This pin is not available on all devices. Refer to either the “Pin Diagrams” or “Pin Tables” section in the
specific device data sheet to determine availability.
2007-2018 Microchip Technology Inc. DS60001145W- page 7
PIC32
4.3 PIC32MX Power Requirements
Devices in the PIC32MX family are dual voltage
supply designs. There is one supply for the core and
another for peripherals and I/O pins. All devices
contain an on-chip regulator for the lower voltage
core supply to eliminate the need for an additional
external regulator. There are three implementations
of the on board regulator:
• The first version has an internal regulator that can
be dis abled usin g the ENVREG pin. W hen disabled,
an external pow er supply must be used to pow er the
core. If enabled, a low-ESR filter capacitor must be
connected to the V
CAP
pin, see Figure 4-2.
• The second version has an internal regulator th at
cannot be disabled. A low-ESR filter capacitor must
always be connected to the V
CAP
pin.
• The third version has an internal regulator that
cannot be disabled and does not require a filter
capacitor
Refer to Section 21.0 “AC/DC Characteristics and
Timing Requirements” and the “Electrical
Characteristics” chapter in the specific device data
sheet for the power requirements for your device.
FIGURE 4-2: INTERNAL REGULATOR
ENABLE/DISABLE
OPTIONS
4.4 PIC32MX With V
BAT
Pin Power
Requirements
Some devices in the PIC32MX family provide a V
BAT
pin which can be connected to the V
DD
power supply
during programming. See Figure 4-3.
FIGURE 4-3: PIC32MX WITH V
BAT
PIN
POWER CONNECTIONS
4.5 PIC32MZ EC and PIC32MZ EF
Power Requirements
Devices in the PIC32MZ EC an d PIC32 MZ EF fam ilie s
are also dual voltage supply designs like PIC32MX
devices. However, the internal regulator does not
require the externa l filte r capacitor, and there is no cor-
respondi ng V
CAP
or ENVREG pins. See Figure 4-4.
Refer to Section 21.0 “AC/DC Characteristics and
Timing Requirements” and the “Electrical
Characteristics” chapter in the specific device data
sheet for the power requirements for your device.
FIGURE 4-4: PIC32MZ EC/EF POWER
CONNECTIONS
V
DD
ENVREG
V
CAP
V
SS
PIC32MX
3.3V
(1)
1.8V
(1)
V
DD
ENVREG
V
CAP
V
SS
PIC32MX
C
EFC
3.3V
Regulator Enabled
(2)
Regul ator Disabled
(2)
(10 F typical)
Note 1: These are typical operating voltages. Refer to
Section 21.0 “AC/DC Characteristics and Timing
Requirements”
for the full operating ranges of V
DD
and V
CAP
.
2:
Regulator Enabled and Regulator Disabled mode
are no t av ai labl e o n all de vic es. R efe r t o th e spe ci fic
device data sheet to determine availability.
(ENVREG tied to V
DD
)
(ENVREG tied to ground)
Note 1:
This is typical operating voltage. Refer to
Section 21.0 “AC/DC Characteristics and Timing
Requirements”
for the full operating range of V
DD
.
V
DD
V
BAT
V
CAP
V
SS
PIC32MX XLP
3.3V
(1)
V
DD
V
SS
PIC32MZ EC/EF
3.3V
(1)
Note 1:
This is typical operating voltage. Refer to
Section 21.0 “AC/DC Characteristics and Timing
Requirements”
for the full operating range of V
DD
.
PIC32
DS60001145W-page 8 2007-2018 Microchip Technology Inc.
4.6 PIC32MZ DA Power Requirements
Devices in the PIC32MZ DA family are quadruple
voltage supply d esigns. Two of the voltag e supplies a re
identic al to th e PIC32 MZ EC and PIC32 MZ EF vo ltag e
supplies. The third voltage supply is for the DDR
memory interface, and requires a 1.8 volt supply. The
fourth voltage supply is for the V
BAT
pin, but it can be
connected to the V
DD
power supply. See Figure 4-5.
Refer to Section 21.0 “AC/DC Characteristics and
Timing Requirements” and the “Electrical
Characteristics” chapter in the specific device data
sheet for the power requirements for your device.
FIGURE 4-5: PIC32MZ DA POWER
CONNECTIONS
4.7 PIC32MK Power Requirements
Devices in the PIC32MK family are triple voltage supply
design s. T wo of the voltag e supplies are identical to th e
PIC32MZ EC and PIC32MZ EF voltage supplies. The
third voltage supply is for the V
BAT
pin, but it can be
connec ted to the V
DD
power supply. See Figure 4-6.
FIGURE 4-6: PIC32M K POWER
CONNECTIONS
5.0 EJTAG vs. IC SP
Programming is accomplished through the EJTAG
module in the CPU c ore. EJTAG is connect ed to either
the full set of JTAG pins, or a reduced 2-wire to 4-wire
EJTAG interface for ICSP mode. In both modes,
programming of the PIC32 Flash memory is
accomplished through the ETAP controller. The TAP
Cont roll er us es th e TMS pin to de term ine if Instr uct ion
or Data registers should be accessed in the shift path
betwee n TDI and TDO, see Figure 5-1.
The basic concept of EJTAG that is used for
programming is the use of a special memory area
called DMSEG (0xFF200000 to 0xFF2FFFFF), which
is only available when the processor is running in
Debug m ode. All ins tructions ar e serially shi fted into an
internal buffer, and then loaded into the Instruction
register and executed by the CPU. Instructions are fed
through the ETAP state machine in 32-bit groups.
FIGURE 5-1: TAP CONTROLLER
V
DD
IO
V
BAT
V
DD
CORE
and V
DDR
1
V
8
V
SS
PIC32MZ DA
3.3V
(1)
1.8V
(1)
Note 1:
These are typical operating voltages. Refer to
Section 21.0 “AC/DC Characteristics and Timing
Requirements”
for the full operating ranges of
V
DD
IO
, V
BAT
, V
DD
CORE,
and V
DDR
1
V
8
.
V
SS
1
V
8
V
DD
V
BAT
V
SS
PIC32MK
3.3V
(1)
Note 1:
These are typical operating voltages. Refer to
Section 21.0 “AC/DC Characteristics and Timing
Requirements”
for the full operating ranges of V
DD
and VBAT.
TMS
TCK
TDO
TDI
Tap Controller
Instruction, D a ta,
and Control Registers
2007-2018 Microchip Technology Inc. DS60001145W- page 9
PIC32
5.1 Programming Interface
Figure 5-2 shows the basic programming interface in
PIC32 devices. Descriptions of each interface block are
provided in subsequent sections.
FIGURE 5-2: BASIC PIC32 PROGRAMMING INTERFACE BLOCK DIAGRAM
5.1.1 ETAP
This block serially feeds instructions and data into the
CPU.
5.1.2 MTAP
In addition to the EJTAG TAP (ETAP) controller, the
PIC32 devic e uses a sec ond pro prietary TAP cont roller
for additional operations. The Microchip TAP (MTAP)
controller supports two instructions relevant to
programming: MTAP_COMMAND and TAP switch
Instructions. See Table 20-1 for a complete list of
Instructions. The MTAP_COMMAND instruction provides
a mechanism for a JTAG probe to send commands to
the device through its Data register.
The programmer sends commands by shifting in the
MTAP_COMMAND instruc tion through t he SendCommand
pseudo operation, and then sending the MTAP_COM-
MAND DR commands through the XferData pseudo
operation, see Table 20-2 for specific commands.
The probe does not need to issue a MTAP_COMMAND
instruction for every command shifted into the Data
register.
5.1. 3 2-W IR E TO 4-WI R E
This block converts the 2-wire ICSP interface to the
4-wire JTAG interface.
5.1.4 CPU
The CPU executes instructions at 8 MHz through the
internal oscillator.
5. 1.5 FLASH CONTROLLER
The Flas h control ler contro ls erasi ng and programmin g
of the Flash memory on the device.
5.1.6 FLASH MEMORY
The PIC32 device Flash memory is divided into two
logical Flash partitions consisting of the Boot Flash
Memory (BFM) and Program Flash Memory (PFM).
The BFM b egins at address 0x1FC00000, and the PFM
begins at add ress 0x1D 00000 0. Each Flas h parti tion i s
divided into pages, which represent the smallest block
of memory that can be erased. Depending on the
device, page sizes are 256 words (1024 bytes), 1024
words (4096 bytes), or 4096 words (16,384 bytes).
Row size indicates the number of words that are
programmed with the row program command. There
are always 8 rows within a page; therefore, devices
with 256, 1024, and 4096 word page sizes have 32,
128, and 512 word row sizes, respectively. Table 5-1
shows the PFM, BFM, row, and page size of each
device family.
Memory locations of the BFM are reserved for the
device Configuration registers, see Section 19.0
“Configuration Memory and Device ID” for more
information.
TMS
TCK
TDI
TDO
or
PGECx
PGEDx
ETAP CPU
MTAP
2-wire
Flash
Flash
to
4-wire
Controller
Memory
Common
V
DD
/V
DD
IO/V
DD
1
V
8
CORE
V
SS
/V
SS
1
V
8
MCLR
V
BAT
/V
DDR
1
V
8
PIC32
DS60001145W-page 10 2007-2018 Microchip Technology Inc.
TABLE 5-1: CODE MEMORY SIZE
PIC32 Device Row Size
(Words) Page Size
(Words) Boot Flash Mem ory Address
(Bytes) (See Note 1) Program m ing Executive
(See N ote s 2 and 3)
PIC32MX
110/120/130/150/170
210/220/230/350/270
(28/36/4 4-pin device s O nly)
32 256
0x1FC 00000-0x1F C 00BFF (3 KB)
RIPE_11_aabbcc.hex
PIC32MX
120/130/150/170/230/250/
270/530/550/570
(64/100- pin devices Only)
PIC32MX
15X/17X/25X/27X
(28/4 4- pi n devices Onl y) 0x1FC 00000-0x1F C 02FFF (12 KB)
PIC32MX
330/350/370/430/450/470
128 1024 0x1F C 00000-0x1F C 02FFF (12 KB)
RIPE_06_aabbcc.hex
PIC32MX
320/340/360/420/440/460
PIC32MX
534/564/664/764
PIC32MX
575/675/695/795
PIC32MK
0512/1024XXD/E/F/K/L/M 128 1024 0x1FC000 00-0x1FC 04FFF (20 KB)
0x1FC 20000-0x1F C 24FFF (20 KB)
RIPE_15a_aabbcc.hex
PIC32MK
0256/0512XXG/H 1 28 1024 0x 1FC00000 -0 x1FC04FFF (20 KB)
RIPE_15a_aabbcc.hex
PIC32MZ
05XX/10XX/20XX 512 4096 0x 1FC00000 -0 x1FC13FFF ( 80 KB)
0x1FC 20000-0x1F C 33FFF (80 KB)
RIPE_15_aabbcc.hex
Note 1: Program Flash M emory address ranges ar e based on Progra m Fla sh s iz e ar e as given below:
• 0x1D 00 0000-0x1D 00 3FFF (16 KB)
• 0x1D 00 0000-0x1D 00 7FFF (32 KB)
• 0x1D000000-0x1 D 00FFFF (64 KB)
• 0x1D000000-0x1 D 01FFFF (128 KB)
• 0x1D000000-0x1 D 03FFFF (256 KB)
• 0x1D000000-0x1 D 07FFFF (512 KB)
• 0x1D000000-0x1D0FFFFF (1024 KB)
• 0x1D000000-0x1D1FFFFF (2048 KB)
All P r ogra m Fl ash memory sizes are no t suppor t ed by each family.
2: The Programmin g Ex ecutive can be obtained from th e re l at ed pr oduct page o n th e M i cr ochip web site, or it can
be located in the following MPLAB
®
X IDE instal lation fo lder s :
…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\REALICE.jar
…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\ICD3.jar
…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\PICKIT3.jar
3: The las t ch aracters of the file name, aabbcc, vary based on t he r evision of the file.
2007-2018 Microchip Technology Inc. DS60001145W-page 11
PIC32
5.2 4-wire JTAG Details
The 4-wire interface uses standard JTAG (IEEE
1149.1-2001) interface signals.
• TCK: Test Clock – drives data in/out
• TMS: Test Mode Select – selects operational mode
• TDI: Test Data Input – data into the device
• TDO: Test Data Output – data out of the device
Since only one data line is available, the protocol is
necessarily serial (like SPI). The clock input is at the
TCK pin. Conf iguration is perfo r me d by ma ni pul ati ng a
state ma chine bit by bit throu gh the TMS pin. One bit of
data is transferred in and o ut per TCK clock pu lse at the
TDI and TDO pins. Different instruction modes can be
loaded to read the chip ID or mani pulate chip fun ctions.
Data presented to TDI must be valid for a chip-specific
setup time before, and hold time, after the rising edge
of TCK. TDO data is valid for a chip-specific time after
the falling edge of TCK, refer to Figure 5-3.
FIGURE 5-3: 4-WIRE JTAG INTERF ACE
TMS
TDI
TDO
iMSb
iLSb
‘1’
TCK
oLSb oMSb
‘1’‘1’‘1’
‘0’‘0’‘0’
PIC32
DS60001145W-page 12 2007-2018 Microchip Technology Inc.
5.3 2 -w ire ICSP Det a il s
In ICSP mode, the 2-wire ICSP signals are time
multiplexed into the 2-wire to 4-wire block. The 2-wire
to 4-wire block then converts the signals to look like a
4-wire JTAG port to the TAP controller. The following
are two possible modes of operation:
• 4-phase ICSP
• 2-phase ICSP
5.3.1 4-PHASE ICSP
In 4-phase ICSP mode, the T DI , T DO and TMS devic e
pins are multiplexed onto PGEDx in four clocks, see
Figure 5-4. The Least Significant bit (LSb) is shifted
first; and TDI and TMS are sampled o n the fall ing edg e
of PGECx, while TDO is driven on the falling edge of
PGECx. The 4-p hase ICSP mode is used fo r bot h read
and write data transfers.
5.3.2 2-PHASE ICSP
In 2-phase ICSP mode, the TMS and TDI device pins
are multiplexed into PGEDx in two clocks, see
Figure 5-5. The LSb is shifted first; and TDI and TMS
are sam pled on the fallin g edge of PGEC x. There is no
TDO ou tput pr ovid ed in thi s mode . The 2-ph ase ICS P
mode was designed to accelerate 2-wire, write-only
transactions.
FI GU R E 5 -4: 2-WIRE, 4-PHASE
Note: The packet is not actually executed until
the first clock of the next packet. To enter
2-wire, 2-phase ICSP mode, the TDOEN
bit (DDPCON<0> or CFGCON<0>) must
be set to ‘0’.
TMS
TDI
TDO
IR4
IR0
‘1’
TCK
‘1’‘1’‘1’
‘0’‘0’‘0’
X
1
PGECx
PGEDx pTDO = 1
TDI = IR0
TMS = 0nTDO = 0
2007-2018 Microchip Technology Inc. DS60001145W-page 13
PIC32
FIGURE 5-5: 2-WIRE, 2-PHASE
5.3.3 SYNCHRONIZATION
Some PIC32 devices can Reset the internal EJTAG
state machine if the attached programmer loses syn-
chroniz ation with it. This ca n occur when noi se is pres-
ent on the PGCx signal.
To achieve resynchronization, the PGEDx pin is held
high for 24 PGECx clock cycles. This forces five TMS
events into the EJTAG controller and will place the
EJTAG state machine into a Test Idle Reset. See
Figure 5-6 for an example of how to achieve
resynchronization.
When asserting the PGEDx pin high, there may be
contention on the pin as the device may attempt to
drive TDO out o nto th e pi n w hil e the in-c irc uit emu lat or
is driving in. This will only occur for a maximum of one
cycle as TMS high will advance the EJTAG state
machine out of a Shift-IR or Shift-DR state.
Synchronization in 2-wire, 2-phase mode is not
supported.
FIGURE 5-6: ACHIEVING RESYNCHRONIZATION
TMS
TDI
TDO
IR4
IR0
‘1’
TCK
‘1’‘1’‘1’
‘0’‘0’‘0’
X
1
PGECx
PGEDx
TDI = IR0
TMS = 0
PGECx
PGEDx
§§
12345 24232221
Synchronization achieved
TDO Contention
PIC32
DS60001145W-page 14 2007-2018 Microchip Technology Inc.
6.0 PSEUDO OPERATIONS
To simplify the description of programming details, all
operations will be described using pseudo operations.
There are several functions used in the pseudo-code
descriptions. These are used either to make the
pseudo-code more readable, to abstract
implementation-specific behavior, or both. When
passing parameters with pseudo operation, the
following syntax will be used:
• 5’h0x03 – send 5-bit hexadecimal value of 3
•6’b011111 – send 6-bit binary value of 31
These fu nctions are defined in this s ection, a nd include
the following operations:
•SetMode (mode)
•SendCommand (command)
•oData = XferData (iData)
•oData = XferFastData (iData)
•oData = XferInstruction (instruction)
6.1 SetMode Pseudo Operation
Format:
SetMode (mode)
Purpose:
To set the EJTAG state machine to a specific state.
Description:
The value of mode is clocked into the device on
signal TMS. TDI is set to a ‘0’ and TDO is igno red .
Restrictions:
None.
Example:
SetMode (6’b011111)
FIGURE 6-1: SetMode 4-WIRE
FIGURE 6-2: SetMode 2-WIRE
TMS
TDI
TDO
‘1’
TCK
‘1’‘1’
‘1’‘1’‘0’
Mode = 6’b011111
PGEDx
PGECx
TDI = 0TDO = 1
TMS = 1TDI = 0TMS = 0TDO = x
Mode = 6’b011111
2007-2018 Microchip Technology Inc. DS60001145W-page 15
PIC32
6.2 SendCommand Pseudo Operation
Format:
SendCommand (command)
Purpose:
To send a command to select a s pecific TAP register.
Description (in sequence):
1. The TMS Header is clocked into the device to
select the Shift IR state
2. The command is clocked into the device on
TDI while holding signal TMS low.
3. The last Most Significant bit (MSb) of the
command is clocked in while setting TMS
high.
4. The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
Restrictions:
None.
Example:
SendCommand (5’h0x07 )
FIGURE 6-3: SendCommand 4-WIRE
FIGURE 6-4: SendCommand 2-WIRE (4-PHASE)
TMS
TDI
TDO
iMSb
‘1’
TCK
‘1’ ‘1’‘1’‘0’‘0’ ‘0’
x
1
iLSb
TMS Header = 1100 Command = 5’h0x07 Command (MSb)
+ TMS = 1TMS Footer = 10
TDI =
0
TMS =
1
TMS =
1
TDI =
0
TDO =
x
TDO =
x
TDI = iMS b
TDO =
x
TMS =
0
TDI = iLS b
TDO =
x
TMS =
1
TMS Header = 1100 Command (5’h0x07) + TMS = 0Command (MSb) + TMS = 1TMS Footer = 10
PGECx
PGEDx
PIC32
DS60001145W-page 16 2007-2018 Microchip Technology Inc.
6.3 XferData Pseudo Operation
Format:
oData = XferData (iData)
Purpose:
To clock data to and fro m the register s elected b y the
command.
Description (in sequence):
1. The TMS Header is clocked into the device to
select the Shift DR state.
2. The data is clocked in/out of the device on
TDI/TDO while holding signal TMS low.
3. The last MSb of the data is clocked in/out
while setting TMS high.
4. The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
Restrictions:
None.
Example:
oData = XferData (32’h0x12)
FIGURE 6-5: XferData 4-WIRE
FIGURE 6-6: XferData 2-WIRE (4-PHASE)
TMS
TDI
TDO
iMSb
‘1’
TCK
‘1’‘1’
‘0’‘0’‘0’
iLSb
TMS Header = 100 Data (32’h0x12) Data (MSb) + TMS = 1TMS Footer = 10
oMSb
oLSb
TDI = 0TMS = 0
TDO = o LS bTDI =
0
TDO =
X
TMS =
0
TDI =
0
TDO =
X
TMS =
1
PGEC
PGED
TMS Header =
100
TDI =
0
TMS =
0
TDO =
X
TDI =
0
TDO =
X
TMS =
1
TMS =
1
TDO =
X
TMS =
0
TDI = iLSb TDO = o LS b+1 TDI = iMSb
Data (31’h0x12) + TMS =
0
Data (MSb) + T MS Footer =
1
TMS Fo oter =
10
...
2007-2018 Microchip Technology Inc. DS60001145W-page 17
PIC32
6.4 XferFastData Pseudo Operation
Format:
oData = XferFastData (iData)
Purpose:
To quickly send 32 bits of data in/out of the device.
Description (in sequence):
1. The TMS Header is clocked into the device to
select the Shift DR state.
2. The input value of the PrAcc bit, which is ‘0’, is
clocked in.
3. TMS Foote r = 10 i s cloc k ed i n to retu rn th e TAP
controller to the Run/Test Idle state.
Restrictions:
The SendCommand (ETAP_FASTDATA) must be sent
first to select the Fastdata register, as shown in
Example 6-1. See Table 20-4 for a de tailed descri ptions
of comman ds.
EXAMPL E 6-1:
SendCommand
FIGURE 6-7: XferFastData 4-WIRE
F IGU RE 6-8 : Xfer Fa s tDa t a 2-WIRE (2-phase )
Note: For 2-wire (4-phase) – on the last clock,
the oPrAcc bi t is shi fted out on TDO while
clock ing in the TMS H eader . If the valu e of
oPrAcc is not ‘1’, the whole operation
must be repeated.
Note: For 2-wir e (4-phase) – the T DO during this
operation will be the LSb of output data.
The rest of the 31 bit s of the input data are
clocked in and the 31 bits of output data
are clo cked out. For the last bit of the input
data, th e TM S Footer = 1 is set.
Note: The 2-phase XferData is only used when
talking to the PE. See Section 17.0 “The
Programming Executive” for more
information.
// Select the Fastdata Register
SendCommand(ETAP_FASTDATA)
// Send/Receive 32-bit Data
oData = XferFastData(32’h0x12)
TMS
TDI
TDO
iMSb
iLSb
‘
1
’
TCK
oLSb oMSb
‘
1
’‘
1
’
‘
0
’‘
0
’‘
0
’
‘
0
’
‘
1
’
TMS Header =
100
PrAcc Data (32’h0x12) Data (MSb) + TMS =
1
TMS Fo oter =
10
TDI =
X
TMS =
1
TDI =
X
TDI =
TMS =
0
TDI =
TMS =
0
TDI =
0
TMS =
1
TMS Header =
100
Data (32’h0x12) TMS Footer =
10
iLSb
PGEDx
PGECx
PrAcc
TMS =
1
MSb
Da ta (MS b) TMS =
1
PIC32
DS60001145W-page 18 2007-2018 Microchip Technology Inc.
FIGURE 6-9: Xfe rFastData 2-WIRE (4-PHASE)
TDI =
0
TMS =
0
TDO = oPrAccTDI =
0
TDO =
X
TMS =
0
TDI =
0
TDO =
X
TMS =
1
PGECx
PGEDx
TMS Header =
100
TDI =
0
TMS =
0
TDO =
X
TDI =
0
TDO =
X
TMS =
1
TMS =
1
TDO =
X
TMS =
0
TDI = iLSb TDO = oLSb+1 TDI = iMSb
Data (31’h12) + TMS =
0
Data (MSb) + TMS Footer =
1
TMS Footer =
10
TMS =
0
TDI =
0
TDO = oLSb
PrAcc
2007-2018 Microchip Technology Inc. DS60001145W-page 19
PIC32
6.5 XferInstruction Pseudo
Operation
Format:
XferInstruction (instruction)
Purpose:
To send 32 bits of data for the device to execute.
Description:
The instruction is clocked into the device and then
executed by CPU.
Restrictions:
The device must be in Debug mode.
EXAMPL E 6-2: XferInstruction
XferInstruction (instruction)
{// Select Control Register
SendCommand(ETAP_CONTROL);
// Wait until CPU is ready
// Check if Processor Access bit (bit 18) is set
do {
controlVal = XferData(32’h0x0004C000);
} while( PrAcc(contorlVal<18>) is not ‘1’ );
// Select Data Register
SendCommand(ETAP_DATA);
// Send the instruction
XferData(instruction);
// Tell CPU to execute instruction
SendCommand(ETAP_CONTROL);
XferData(32’h0x0000C000);
}
PIC32
DS60001145W-page 20 2007-2018 Microchip Technology Inc.
6.6 ReadFromAddress Pseudo
Operation
Format:
oData = ReadFromAddress (address)
Purpose:
To send 32 bits of data to the device memory.
Description:
The 32-bit data is read from the memory at the
address specified in the “address” parameter.
Restrictions:
The device must be in Debug mode.
EXAMPL E 6-3: ReadFromAddress FOR PIC32MX, PIC32MZ, AND PIC32MK DEVICES
ReadFromAddress (address)
{
// Load Fast Data register address to s3
instruction = 0x3c130000;
instruction |= (0xff200000>>16)&0x0000ffff;
XferInstruction(instruction); // lui s3, <FAST_DATA_REG_ADDRESS(31:16)> - set address of fast
data register
// Load memory address to be read into t0
instruction = 0x3c080000;
instruction |= (address>>16)&0x0000ffff;
XferInstruction(instruction); // lui t0, <DATA_ADDRESS(31:16)> - set address of data
instruction = 0x35080000;
instruction |= (address&0x0000ffff);
XferInstruction(instruction); // ori t0, <DATA_ADDRESS(15:0)> - set address of data
// Read data
XferInstruction(0x8d090000); // lw t1, 0(t0)
// Store data into Fast Data register
XferInstruction(0xae690000); // sw t1, 0(s3) - store data to fast data register
XferInstruction(0); // nop
// Shift out the data
SendCommand(ETAP_FASTDATA);
oData = XferFastData(32'h0x00000000);
return oData;
}
2007-2018 Microchip Technology Inc. DS60001145W-page 21
PIC32
6.7 Synchronize Pseudo Operation
Format:
Synchronize ()
Purpose:
To reset the EJTAG state machine into Test Idle
Reset.
Description:
The PGEDx signal is held high for 24 PGECx clock
cycles. All other signals are ignored.
Restrictions:
None.
FIGURE 6-10: ACHIEVING RESYNCHRONIZATION
PGECx
PGEDx
§§
12345 24232221
Synchronization achieved
TDO Contention
PIC32
DS60001145W-page 22 2007-2018 Microchip Technology Inc.
7.0 ENTERING 2-WIRE ENHANCED
ICSP MODE
To use the 2-wire PGEDx and PGECx pins for pro-
gramming, they mu st be enabled . N ote t hat a ny pai r of
programming pins available on a particular device may
be used , however , they must be used as a pair . PG ED1
must be used with PGEC1, and so on.
The following steps are required to enter 2-wire
Enhanced ICSP mode:
1. The MCLR pin is briefly driven high, then low.
2. A 32-bit key sequence is clocked into PGEDx.
3. The MCLR pin is then driven high within a
specified period of time and held.
Refer to Section 21.0 “AC/DC Characteristics and
Timing Requirements” for timing requirements.
The programming voltage applied to the MCLR pin is
V
IH
, which is essentially V
DD
, in PIC32 devices. There
is no minimum time requirement for holding at V
IH
.
After V
IH
is removed, an interval of at least P18 must
elapse before pres enting the ke y sequence on PGEDx.
The key sequence is a specific 32-bit pattern: ‘0100
1101 0100 0011 0100 1000 0101 0000’ (the
acronym ‘MCHP’, in ASCII). The device will enter
Program/Verify mode only if the key sequence is valid.
The MSb of the M os t Si gnificant ni bbl e must be shifted
in first.
Once the key sequence is complete, V
IH
must be
applied to the MCLR pin and held at that level for as
long as the 2-wire Enhanced ICSP interface is to be
maintained. An interval of at least time P19 and P7
must elapse before presentin g data on PGEDx. Signals
appearin g on PGEDx before P7 has elapsed will not be
interpreted as valid.
Upon successful entry, the programming operations
docu mented in su bsequent se ctions can b e performe d.
While in 2-wire Enhanced ICSP mode, all unused I/Os
are placed in the high-impeda nce state .
FIGURE 7-1: EN TERING ENHANCED ICSP™ MODE
Note: If using the 4-wire JTAG interface, the
following procedure is n ot necessary.
Note: Entry i nto ICSP mode plac es the de vice in
Reset to prevent instructions from
executing. To release the Reset, the
MCHP_DE_ASSERT_RST command must
be issued.
MCLR
PGEDx
PGECx
V
DD
P6 P14
b31 b30 b29 b28 b27 b2 b1 b0b3
...
Program/Verify Entry Code = 0x4D434850
P1A
P1B
P18
P19
01001 0000
P7
V
IH
V
IH
P20
2007-2018 Microchip Technology Inc. DS60001145W-page 23
PIC32
8.0 CHECK DEVICE STATUS
Befo re a de vic e c an be pr og ram med, t he p rogr amme r
must check the status of the device to ensure that it is
ready to receive information.
FIGURE 8-1: CHECK DEVICE STATUS
8.1 4-wire Interface
The setup sequence to enter 4-wire JTAG program-
ming should be done while asserting the MCLR pin.
Once th e programmin g mode is entered, th e MCLR pin
can be released to allow the processor to execute
instructions or drive ports.
The following steps are required to check the device
status using the 4-wire interface:
1. Set the MCLR pin low.
2. SetMode (6’b011111) to force the Chip TAP
controller into Run Test/Idle state.
3.
SendCommand
(MTAP_SW_MTAP).
4. SetMode (6’b011111) to force the Chip TAP
controller into Run Test/Idle state.
5. SendCommand (MTAP_COMMAND).
6. statusVal = XferData (MCHP_STATUS).
7. If CFGRDY (statusVal<3>) is not ‘1’ and
FCBUSY (statusVal<2>) is not ‘0’ GOTO step 5.
8.2 2-wire Interface
The following steps are required to check the device
status using the 2-wire interface:
1. SetMode (6’b011111) to force the Chip TAP
controller into Run Test/Idle state.
2. SendCommand (MTAP_SW_MTAP).
3. SetMode (6’b011111) to force the Chip TAP
controller into Run Test/Idle state.
4. SendCommand (MTAP_COMMAND).
5. statusVal = XferData (MCHP_STATUS).
6. If CFGRDY (statusVal<3>) is not ‘1’ and
FCBUSY (statusVal<2>) is not ‘0’, GOTO
step 4.
SetMode (6’b011111)
SendCommand (MTAP_SW_MTAP)
SendCommand (MTAP_COMMAND)
statusVal = XferData (MCHP_STATUS)
FCBU SY = 0
CFGRDY = 1
No
Set MCLR low 4-wire
Done
Yes
SetMode (6’b011111)
Note: If using the 4-wire interface, the oscillator
source, as selected by the Configuration
Words, must be present to access the
Flash memory. In an unprogrammed
device , the oscilla tor source is the internal
FRC allowi ng for F lash memory access. If
the Configuration Words have been
reprogrammed selecting an external
oscillator source then it must be present
for Flash memory access. See the
“Special Features” chapter in the
specific device data sheet for details
regarding oscillator selection using the
Configuration Word settings.
Note: If the CFGRDY and FCBUSY bits do not
come to the prop er state withi n 10 ms, the
sequence may have been executed
incorrectly or the device is damaged.
PIC32
DS60001145W-page 24 2007-2018 Microchip Technology Inc.
9.0 ERASING THE DEVICE
Before a device can be programmed, it must be
erased. The erase operation writes all ‘1s’ to the Flash
memory and prepares it to program a new set of data.
Once a device is erased, it can be verified by
performing a “Blank Check” operation. See
Section 9.1 “Blank Check” for more information.
The proc edu re f or e ras ing pro gram m em ory (Pro gram ,
boot, and Configuration memory) consists of selecting
the MTAP and sending the MCHP_ERASE command.
The programmer must wait for the erase operation to
complete by reading and verifying bits in the
MCHP_STATUS value. Figure 9-1 illustrates the process
for performing a Chip Erase.
The following steps are required to erase a target
device:
1. SendCommand (MTAP_SW_MTAP).
2. SetMode (6’b011111).
3. SendCommand (MTAP_COMMAND).
4. XferData (MCHP_ERASE).
5. XferData (MCHP_DE_ASSERT_RST). This step is
not required for PIC32MX devices.
6. Delay 1 0 ms.
7. statusVal = XferData (MCHP_STATUS).
8. If CFGRDY (statusVal<3>) is not ‘1’ and
FCBUSY (statusV al<2>) is not ‘0’, GOTO to step
5.
FIGURE 9-1: ERASE DEVICE
9.1 Blank Check
The term “Blank Check” implies verifying that the
device has been successfully erased and has no
programmed memory locations. A blank or erased
memory location always reads as ‘1’.
The device Configuration registers are ignored by the
Blank Check. Additionally, all unimplemented memory
space should be ignored from the Blank Check.
Note: The Device ID memory l ocations are read-
only and cannot be erased. Therefore,
Chip Erase h as no ef fect on these m emory
locations.
Note: The Chip Erase operation is a self-timed
operation. If the FCBUSY and CFGRDY
bits do not set properly within the specified
Chip Erase time, the sequence may have
been executed incorrectly or the device is
damaged.
SendCommand (MTAP_COMMAND)
statusVal =
XferData (MCHP_STATUS)
FCBUSY
=
0
CFGRDY
=
1
No
SendCommand (MTAP_SW_MTAP)
Select MTAP
Put MTAP in C ommand Mod e
XferData (MCHP_ERASE)
Issue Chip Erase Command
Read Erase Status
Done
Yes
10 milliseconds Delay
XferData (MCHP_DE_ASSERT_RST)
Not required for P IC32MX Devices
SetMode (6’b011111)
2007-2018 Microchip Technology Inc. DS60001145W-page 25
PIC32
10.0 ENTERING SERIAL
EXECUTION MODE
Before programming a device, it must be placed in
Serial Execution mode. The procedure for entering
Serial Execution mode consists of verifying that the
device is not code-protected. If the device is code-
protected, a Chip Erase must be performed. See
Section 9.0 “Erasing the Device” for details.
FIGURE 10-1: ENTERING SERIAL
EXECUTION MODE
Select MTAP
SendCommand
(
MTAP_SW_MTAP
)
Put MTAP in Command Mode
SendCommand
(
MTAP_COMMAND
)
Read Code-Protect Status
sta tusVal = XferData (
MCHP_STATUS
)
CPS =
1
Cannot Enter
Must Erase First
Select ETAP
SendCommand
(
MTAP_SW_ETAP
)
Put CPU in Serial Exec Mode
SendCommand
(
ETAP_EJTAGBOOT
)
No
2-wire
4-wire
Set MCLR High
Enable Flash
Xfe r D ata (
MCHP_FLASH_EN
)
Release Rese t
XferData (
MCHP_DE_ASSERT_RST
)
Put MTAP in Command Mode
SendCommand
(
MTAP_COMMAND
)
Select MTAP
SendCommand
(
MTAP_SW_MTAP
)
Assert Reset
XferData (
MCHP_ASSERT_RST
)
2-wire
Yes
Select ETAP
SendCommand
(
MCHP_SW_ETAP
)
Required for PIC3 2MX dev ices
SetMode (6’b011111)
SetMode (6’b011111)
SetMode (6’b011111)
SetMode (6’b011111)
PIC32
DS60001145W-page 26 2007-2018 Microchip Technology Inc.
10.1 4-wire Interface
The following steps are required to enter Serial
Executi on mod e:
1. SendCommand (MTAP_SW_MTAP).
2. SetMode (6’b011111).
3. SendCommand (MTAP_COMMAND).
4. statusVal = XferData (MCHP_STATUS).
5. If CPS (statu sVal<7>) is no t ‘1’, the devic e m us t
be erased first.
6. SendCommand (MTAP_SW_ETAP).
7. SetMode (6’b011111).
8. SendCommand (ETAP_EJTAGBOOT).
9. Set the MCLR pin high.
10.2 2-wire Interface
The following steps are required to enter Serial
Execution mode:
1. SendCommand (MTAP_SW_MTAP).
2. SetMode (6’b011111).
3. SendCommand (MTAP_COMMAND).
4. statusVal = XferData (MCHP_STATUS).
5. If CPS (statu sVal<7>) is no t ‘1’, the dev ice m us t
be erased first.
6. XferData (MCHP_ASSERT_RST).
7. SendCommand (MTAP_SW_ETAP).
8. SetMode (6’b011111).
9. SendCommand (ETAP_EJTAGBOOT).
10. SendCommand (MTAP_SW_MTAP).
11. SetMode (6’b011111).
12. SendCommand (MTAP_COMMAND).
13. XferData (MCHP_DE_ASSERT_RST).
14. XferData (MCHP_FLASH_ENABLE). This step is
required for PIC32MX family devices.
15. SendCommand (MTAP_SW_ETAP).
16. SetMode (6’b011111).
Note: It is ass umed that t he MCL R pin h as be en
driven low from the previous Check
Device Status step (see Figure 8-1).
2007-2018 Microchip Technology Inc. DS60001145W-page 27
PIC32
11.0 DOWNLOADING THE
PROGRAMMING EXECUTIVE
(PE)
The PE res ides in RAM mem ory and is exec uted by the
CPU to program the device. The PE provides the
mechanism for the programmer to program and verify
PIC32 devices using a simple command set and
communication protocol. There are several basic
functions provided by the PE:
• Read memory
• Erase memory
• Program memory
• Blank check
• Read executive firmware revision
• Get the Cyclic Redundancy Check (CRC) of Flash
memory locati ons
The PE performs the low-level tasks required for
programming and verifying a device. This allows the
programmer to program the device by issuing the
appropriate commands and data. A detailed
description for each command is provided in
Section 17.2 “The PE Command Set”.
The PE uses the device’s data RAM for variable
storage and program execution. After the PE has run,
no assumptions should be made about the contents of
data RAM.
After the PE is loaded into the data RAM, the PIC32
family can be programmed using the command set
shown in Table 17-1.
FIGURE 11-1: DOWNLOADING THE PE
Loading the PE in the memory is a two step process:
1. Load the PE loader in the data RAM. (The PE
loader loads the PE binary file in the proper
location of the data RAM, and when done,
jumps to the programming exec and starts
executing it.)
2. Feed the PE binary to the PE loader.
Table 11-1 lists the ste ps that are requi red to downloa d
the PE.
Write the PE Loade r to RAM
Load the PE
TABLE 11-1: DOWNLOAD THE PE
OP CODES
Operation Operand
Step 1: PIC32MX devices only: Initialize BMXCON to
0x1F0040. The instruction sequence executed by
the PIC32 core is:
lui a0,0xbf88
ori a0,a0,0x2000 /* address of BMXCON */
lui a1,0x1f
ori a1,a1,0x40 /* a1 has 0x1f0040 */
sw a1,0(a0) /* BMXCON initialized */
XferInstruction 0x3c04bf88
XferInstruction 0x34842000
XferInstruction 0x3c05001f
XferInstruction 0x34a50040
XferInstruction 0xac850000
Step 2: PIC32MX devices only: Initialize BMXDKPBA to
0x800. The instruction sequence executed by the
PIC32 core is:
li a1,0x800
sw a1,16(a0)
XferInstruction 0x34050800
XferInstruction 0xac850010
Step 3: PIC32MX devices only: Initialize BMXDUDBA
and BMXDUPBA to the value of BMXDRMSZ.
The instruction sequence executed by the PIC32
core is:
lw a1,64(a0) /* load BMXDMSZ */
sw a1,32(a0)
sw a1,48(a0)
XferInstruction 0x8C850040
XferInstruction 0xac850020
XferInstruction 0xac850030
Step 4: Set up PIC32 RAM address for PE. The instruc-
tion sequence executed by the PIC32 core is:
lui a0,0xa000
ori a0,a0,0x800
XferInstruction 0x3c04a000
XferInstruction 0x34840800
Step 5: Load the PE_Loader. Repeat this step (Step 5)
until the entire PE_Loader is loaded in the PIC32
memory. In the operands field, “<PE_loader
hi++>” represents the MSbs 31 through 16 of the
PE loader op codes shown in Table 11-2. L ike-
wise, “<PE_loader lo++>” represents the LSbs
15 through 0 of the PE loader op codes shown in
Table 11-2. The “++” sign indicates that when
these operations are performed in succession,
the new word is to be transferred from the list of
op codes of the LPE Loader shown in Table 11-2.
The instruction sequence executed by the PIC32
core is:
lui a2, <PE_loader hi++>
ori a2,a2, <PE_loader lo++>
sw a2,0(a0)
addiu a0,a0,4
XferInstruction (0x3c06 <PE_loader hi++> )
PIC32
DS60001145W-page 28 2007-2018 Microchip Technology Inc.
XferInstruction (0x34c6 <PE_loader lo++> )
XferInstruction 0xac860000
XferInstruction 0x24840004
Step 6: Jump to the PE_Loader. The instruction
sequence executed by the PIC32 core is:
lui t9,0xa000
ori t9,t9,0x800
jr t9
nop
XferInstruction 0x3c19a000
XferInstruction 0x37390800
XferInstruction 0x03200008
XferInstruction 0x00000000
Step 7: Load the PE using the PE_Loader. Repeat the
last instruction of this step (Step 7) until the entire
PE is loaded into the PIC32 memory. In this step,
you are given an Intel
®
Hex format file of the PE
that you will parse and transfer a number of 32-bit
words at a time to the PIC32 memory (refer to
Appendix B: “Hex File Format”). The instruction
sequence executed by the PIC32 is shown in
Table 11-2.
SendCommand ETAP_FASTDATA
XferFastData PE_ADDRESS (Address of PE
program block from PE Hex
file)
XferFastData PE_SIZE (Number of 32-bit
words of the program block
from PE Hex file)
XferFastData PE software op code from PE
Hex file (PE Instructions)
Step 8: Jump to the PE. Magic number (0xDEAD0000)
instructs the PE_Loader that the PE is completely
loaded into the memory. When the PE_Loader
sees the magic number, it jumps to the PE.
XferFastData 0x00000000
XferFastData 0xDEAD0000
TABLE 11-2: PE LOADER OP CODES
Op code Instruction
0x3c07dead lui a3, 0xdead
0x3c06ff20 lui a2, 0xff20
0x3c05ff20 lui al, 0xff20
herel:
0x8cc40000 lw a0, 0 (a2)
0x8cc30000 lw v1, 0 (a2)
0x1067000b beq v1, a3, <here3>
0x00000000 nop
0x1060fffb beqz v1, <here1>
0x00000000 nop
here2:
0x8ca20000 lw v0, 0 (a1)
0x2463ffff addiu v1, v1, -1
0xac820000 sw v0, 0 (a0)
TABLE 11-1: DOWNLOAD THE PE
OP CODES (CONTINUED)
Operation Operand
0x24840004 addiu a0, a0, 4
0x1460fffb bnez v1, <here2>
0x00000000 nop
0x1000fff3 b <here1>
0x00000000 nop
here3:
0x3c02a000 lui v0, 0xa000
0x34420900 ori v0, v0, 0x900
0x00400008 jr v0
0x00000000 nop
TABLE 11-2: PE LOADER OP CODES
Op code Instruction
2007-2018 Microchip Technology Inc. DS60001145W-page 29
PIC32
12.0 DOWNLOADING A DATA
BLOCK
To prog ram a block of da ta to th e PIC32 devic e, it m ust
be loaded into SRAM.
12.1 Wit hout the PE
To program a block of memory without using the PE,
the block of data must first be written to RAM. This
method requires the programmer to transfer the actual
machine instructions with embedded (immediate) data
for wri ting the b lock of data to th e devices internal RAM
memory.
FIGURE 12-1: DOWNLOADING DATA
WITHOUT THE PE
The follo wing steps are requi red to downloa d a block of
data:
1.
XferInstruction
(op code).
2. Repeat Step 1 until the last instruction is
transferred to CPU.
TABLE 12-1: DOWNLOAD DATA OP
CODES
12.2 With the PE
When using the PE, the steps in Section 12.0 “Down-
loading a Data Block” and Section 14.0 “Initiating a
Flash Row Write” are handled in two single commands:
ROW_PROGRAM and PROGRAM.
The ROW_PROGRAM command progra ms a single row of
Flash data, while the PROGRAM command programs
multiple rows of Flash data. Both of these commands
are documented in Section 17.0 “The Programming
Executive”.
Op code Instruction
Step 1: Initialize SRAM Base Addre ss to 0xA0000000.
3c10a000 lui s0, 0xA000;
Step 2: Write the entire row of data to be programmed
into sys te m SRAM.
3c08<DATA>
3508<DATA>
ae08<OFFSET>
lui t0, <DATA(31:16)>;
ori t0, t0, <DATA(15:0)>;
sw t0, <OFFSET>(s0);
// OFFSET increments by 4
Step 3: Repeat Step 2 until one row of data has been
loaded.
bufAddr = RAM Buffer Address
Write 32-bit Immediate
Increment bufAddr
Done
No
Data to bufAddr
PIC32
DS60001145W-page 30 2007-2018 Microchip Technology Inc.
13.0 INITIATING A PAGE ERASE
An individual page may be erased rather than erasing
all of Flash memory. The PE is not used in this case.
PIC32M K fami ly d evice s ca n perf orm an eras e retry on
a page by increasing the internal voltage used to per-
form the erase.
TABLE 13-1: PAGE ERASE
OP CODES
Op Code Instruction
Step 1: All PIC32 devices: Initialize constants. Registers a1, a2, and a3 are set for WREN = 1 or NVMOP<3:0> = 0100, WR = 1
and WREN = 1, respectively. Registers s1 and s2 are set for the unlock data values and s0 is initialized to ‘0’.
34054004 ori a1, $0,0x4004
34068000 ori a2,$0,0x8000
34074000 ori a3,$0,0x4000
3c11aa99 lui s1,0xaa99
36316655 ori s1,s1,0x6655
3c125566 lui s2,0x5566
365299aa ori s2,s2,0x99aa
3c100000 lui s0,0x0000
Step 2: PIC32MX family devices only: Set register a0 to the base address of the NVM register (0xBF80_F400).
3c04bf80 lui a0,0xbf80
3484f400 ori a0,a0,0xf400
Step 3: PIC32MK and PIC32MZ family devices only: Set register a0 to the base address of the NVM register (0xBF80_0600).
Register s3 is set for the value used to disable write protection in NVMBPB.
3c04b480 lui a0,0xbf80
34840600 ori a0,a0,0x0600
34138080 ori s3,$0,0x8080
Step 4: PIC32MK and PIC32MZ family devices only: Unlock and disable Boot Flash write protection.
ac910010 sw s1,16(a0)
ac920010 sw s2,16(a0)
ac930090 sw s3,144(a0)
00000000 nop
Step 5: PIC32MK family devices only: Save the contents of NVMCON 2.
8c9400a0 lw s4,160(a0)
Step 6: PIC32MK family devices only: Set the initial programming voltage level and enable page testing (unlock required).
36953000 ori s5,s4,0x3000
32b5fcff andi s5,s5,0xFCFF
here3:
ac910010 sw s1,16(a0)
ac920010 sw s2,16(a0)
ac860008 sw a2,8(a0)
ac9500a0 sw s5,160(a0)
2007-2018 Microchip Technology Inc. DS60001145W-page 31
PIC32
Step 7: All PIC32 devices: Set the NVMADDR register with the address of the Flash page to be erased.
3c08<ADDR> lui t0,<FLASH_PAGE_ADDR(31:16)>
3508<ADDR> ori t0,t0,<FLASH_PAGE_ADDR(15:0)>
ac880020 sw t0,32(a0)
Step 8: All PIC32 devices: Set up the NVMCON regist er for write operation.
ac850000 sw a1,0(a0)
delay (6 us)
Step 9: PIC32MX devices only: Poll the LVDSTAT register.
here1:
8c880000 lw t0,0(a0)
31080800 andi t0,t0,0x0800
1500fffd bne t0,$0,here1
00000000 nop
Step 10: All PIC32 devices: Unlock the NVMCON register and start the write operation.
ac910010 sw s1,16(a0)
ac920010 sw s2,16(a0)
ac860008 sw a2,8(a0)
Step 11 : All PIC32 devices: Loop until the WR bit (NVMCON<15>) is clear.
here2:
8c880000 lw t0,0(a0)
01064024 and t0,t0,a2
1500fffd bne t0,$0,here2
00000000 nop
Step 12: All PIC32 devices: Wait at least 500 ns after the WR bit (NVMCON<15>) clears before writing to any of t he NVM registers.
This requires inserting a delay in the execution. The programming tools and program executive utilizes the FRC 8 MHz
clock. Therefore four NOP instructions equate to 500 ns (see Note 1).
00000000 nop
00000000 nop
00000000 nop
00000000 nop
Step 13: All PIC32 devices: Clear the WREN bit (NVMCON<14>).
ac870004 sw a3,4(a0)
TABLE 13-1: PAGE ERASE
OP CODES (CONTINUED)
Op Code Instruction
PIC32
DS60001145W-page 32 2007-2018 Microchip Technology Inc.
Step 14: PIC32MK family devices only: Check that all data in the page has been erased. If not, adjust the voltage and try again. If
all voltages levels have been tried, fail, and go to error procedure.
ac870004 sw a3, 4(a0)
20171000 addi s7, $0, 4096
00005020 add t2, $0, $0
8c880020 lw t0, 32(a0)
01194020 add t0, t0, t9
here5:
8d090000 lw t1, 0(t0)
15200005 bne t1, $0, here6
214a0010 addi t2, t2, 16
11570009 beq t2, s7, here7
00000000 nop
1000fffa beq $0, $0, here5
21080010 addi t0, t0, 16
here6:
22b50100 addi s5, s5, 256
32b60300 andi s6, s5, 768
16c0ffde bne s6, $0, here3
00000000 nop
10000005 beq $0, $0, err_proc
00000000 nop
Step 15: PIC32MK family devices only: Restore the NVMCON2 register.
here7:
ac9400a0 sw s4,160(a0)
Step 16: All PIC32 devices: Check the WRERR bit (NVMCON<13>) to ensure that the program sequence has completed success-
fully. If an error occurs, jump to the error processing routine.
8c880000 lw t0,0(a0)
30082000 andi t0,t0,0x2000
1500<ERR_PROC>
bne t0,$0,<err_proc_offset>
00000000 nop
Note 1: F or program ming the Flash at runtime in the users application, the following code is recommended:
while(NVMCON.WR) // waitfor WR bit(NVMCON<15>) to clear
{};
{
unsigned int start_count = _CP0_GET_COUNT();
unsigned int total_count = (.00000025 * SYSCLK); //count for 500 ns and CPU
frequency in MHz
while ((_CP0_GET_COUNT()- start_count) < total_count);
}
TABLE 13-1: PAGE ERASE
OP CODES (CONTINUED)
Op Code Instruction
2007-2018 Microchip Technology Inc. DS60001145W-page 33
PIC32
14.0 INITIATING A FLASH ROW
WRITE
Once a row of data has been downloaded into the
device’s SRAM, the programming sequence must be
initiated to write the block of da ta to the Flash memo ry.
See Table 14-1 for the op code and instructions for
initiating a Flash row write.
14.1 With the PE
When using the PE, the data is immediately written to
the Flash me mo ry from the SR AM. No further ac tion is
required.
14.2 Wit hout the PE
Flash memory write operations are controlled by the
NVMCON register. Programming is performed by
setting the N VMCON re giste r to selec t the type o f wri te
operation and initiating the programming sequence by
setting the WR control bit (N VMCO N<15 >).
FIGURE 14-1: INITIATING FLASH WRITE
WITHOUT THE PE
In the Fla sh w ri te p roc edu re (s ee Table 14-1), the Row
Programming method is used to program the Flash
memory, as it is typ ically the most expedi en t. w o rd an d
Quad Word programming methods are also available,
dependi ng on the devic e, and m ay be us ed or req uired
depending on your application. Refer to the “Flash
Program Me mor y ” cha pte r in the s pecific device da ta
sheet and the related section of the “PIC32 Family
Reference Manual” for more information.
The following steps are required to initiate a Flash
write:
1.
XferInstruction
(op code).
2. Repeat Step 1 until the last instruction is
transferred to the CPU.
Note: Certain PIC32 devices have available
ECC memory. When the ECC feature is
used, the Flash memory must be
programmed in groups of four 32-bit
words using four, 32-bit word alignment. If
ECC is dynamically used, the
programming method determines when
the feature is used. ECC is not enabled
for words programmed with the single
word programming command. ECC is
enabled for words programmed in groups
of four, either with the quad word or row
programming commands. Failure to
adhere to these methods can result in
ECC DED errors during run-time. Refer to
the specific device data sheet for details
regarding ECC use and configuration.
Done
Unprotect Control Registers
Select Write Operation
Load Addresses in NVM Registers
Unlock Flash Controller
Start Operation
PIC32
DS60001145W-page 34 2007-2018 Microchip Technology Inc.
TABLE 14-1: INITIATE FLASH ROW WRITE OP CODES
Op Code Instruction
Step 1: All PIC32 devices: Initialize constants. Registers a1, a2, and a3 are set for WREN = 1 or NVMOP<3:0> = 0011, WR = 1
and WREN = 1, respectively. Registers s1 and s2 are set for the unlock data values and s0 is initialized to ‘0’.
34054003
34068000
34074000
3c11aa99
36316655
3c125566
365299aa
3c100000
ori a1,$0,0x4003
ori a2,$0,0x8000
ori a3,$0,0x4000
lui s1,0xaa99
ori s1,s1,0x6655
lui s2,0x5566
ori s2,s2,0x99aa
lui s0,0x0000
Step 2: PIC32MX devices only: Set register a0 to the base address of the NVM register (0xBF80_F400).
3c04bf80
3484f400
lui a0,0xbf80
ori a0,a0,0xf400
Step 2: PIC32MK and PIC32MZ family devices only: Set register a0 to the base address of the NVM register (0xBF80_0600).
Register s3 is set for the value used to disable write protection in NVMBPB.
3c04bf80
34840600
34138080
lui a0,0xbf80
ori a0,a0,0x0600
ori s3,$0,0x8080
Step 3: PIC32MK and PIC32MZ family devices only: Unlock and disable Boot Flash write protection.
ac910010
ac920010
ac930090
00000000
sw s1,16(a0)
sw s2,16(a0)
sw s3,144(a0)
nop
Step 4: All PIC32 devices: Set the NVMADDR register with the address of the Flash row to be programmed.
3c08<ADDR>
3508<ADDR>
ac880020
lui t0,<FLASH_ROW_ADDR(31:16)>
ori t0,t0,<FLASH_ROW_ADDR(15:0)>
sw t0,32(a0)
Step 5: PIC32MX devices only: Set the NVMSRCADDR register with the physical source SRAM address (offset is 64).
3c10<ADDR>
3610<ADDR>
ac900040
lui s0, <RAM_ADDR(31:16)>
ori s0,s0,<RAM_ADDR(15:0)>
sw s0,64(a0)
Step 5: PIC32MK and PIC32MZ family devices only: Set the NVMSRCADDR register with the physical source SRAM address
(offset is 112) .
3c10<ADDR>
3610<ADDR>
ac900070
lui s0, <RAM_ADDR(31:16)>
ori s0,s0,<RAM_ADDR(15:0)>
sw s0,112(a0)
Step 6: All PIC32 devices: Set up the NVMCON regist er for write operation.
ac850000 sw a1,0(a0)
delay (6 μs)
2007-2018 Microchip Technology Inc. DS60001145W-page 35
PIC32
Step 7: PIC32MX devices only: Poll the LVDSTAT register.
8C880000
31080800
1500fffd
00000000
here1:
lw t0,0(a0)
andi t0,t0,0x0800
bne t0,$0,here1
nop
Step 8: All PIC32 devices: Unlock the NVMCO N register and start the write operation.
ac910010
ac920010
ac860008
sw s1,16(a0)
sw s2,16(a0)
sw a2,8(a0)
Step 9: All PIC32 devices: Loop until the WR bit (NVMCON<15>) is clear.
8c880000
01064024
1500fffd
00000000
here2:
lw t0,0(a0)
and t0,t0,a2
bne t0,$0,here2
nop
Step 10: All PIC32 devices: Wait at least 500 ns after the WR bit (NVMCON<15>) clears before writing to any of the NVM regis -
ters. This requires inserting a delay in the execution. The programming tools and program executive utilizes the FRC 8
MHz clock. Therefore four NOP instructions equate to 500 ns (see Note 1).
00000000
00000000
00000000
00000000
nop
nop
nop
nop
Step 11 : All PIC32 devices: Clear the WREN bit (NVMCONM<14>).
ac870004 sw a3,4(a0)
Step 12: All PIC32 devices: Check the WRERR bit (NVMCON<13>) to ensure that the program sequence has completed
successfully. If an error occurs, jump to the error processing routine.
8c880000
30082000
1500<ERR_PROC>
00000000
lw t0,0(a0)
andi t0,zero,0x2000
bne t0, $0, <err_proc_offset>
nop
Note 1: For programming the Flash at runtime in the users application, the following code is recom-
mended:
while(NVMCON.WR) //Wait for WR bit (NVMCON<15>) to clear
{};
{
unsigned int start_count = _CP0_GET_COUNT();
unsigned int total_count = (.00000025 * SYSCLK); //count for 500 ns and CPU
frequency in MHz
while ((_CP0_GET_COUNT()- start_count) < total_count);
}
TABLE 14-1: INITIATE FLASH ROW WRITE OP CODES (CONTINUED)
Op Code Instruction
PIC32
DS60001145W-page 36 2007-2018 Microchip Technology Inc.
15.0 VERIFY DEVICE MEMORY
The veri fy step invo lves reading back the code memo ry
space and comparing it with the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
15.1 Verifying Memory with th e PE
Memory verify is performed using the GET_CRC
command. Table 17-2 lists the op codes and
instructions.
FIGURE 15-1: VERIF Y ING MEMO RY
WITH THE PE
The foll owing steps are required to verify memory using
the PE:
1. XferF astData (GET_CRC).
2. XferF astData (start_Address).
3. XferF astData (length).
4. valCkSum = XferFast Da ta (32’ h0x00).
Verify that valCkSum matches the checksum of the
copy held in the programmer’s buffer.
15.2 Verifying Memory without the PE
Reading from the Flash memory is performed by exe-
cuting a s eries of read access es from the Fastd ata reg-
ister. Table 20-4 shows the EJTAG programming
details , includi ng the ad dress and op code da ta for p er-
forming processor access operations.
FIGURE 15-2: VERIFYING MEMORY
WITHOUT THE PE
The following steps are required to verify memory:
1.
XferInstruction
(op code).
2. Repeat Step 1 until the last instruction is
transferred to the CPU.
3. V erify that valRe ad matches the cop y held in the
programmer’s buffer.
4. Repeat Steps 1-3 for each memory location.
TABLE 15-1: VERIFY DEVICE OP CODES
Note: Because the Configuration registers
include the device code protection bit,
code memory should be verified immedi-
ately after writing (if code protection is
enabled). This is because the device will
not be readable or verifiable if a device
Reset occurs after the code-protect bit
has been cleared.
Issue Verify Command
Receive Response
Op code Instruction
Step 1: Initialize some constants.
3c13ff20 lui s3, 0xFF20
Step 2: Read memory Location.
3c08<ADDR>
3508<ADDR>
lui t0,<FLASH_WORD_ADDR(31:16)>
ori t0, t0, <FLASH_WORD_ADDR(15:0)>
Step 3: Write to Fastdata location.
8d090000
ae690000
lw t1, 0(t0)
sw t1, 0(s3)
Step 4: Read data from Fastdata register 0xFF200000.
Step 5: Repeat Steps 2-4 until all configuration locations
are read.
Read Memory Location
Verify Location
Done
No
using ReadFromAddress
Pseudo Operation
2007-2018 Microchip Technology Inc. DS60001145W-page 37
PIC32
16.0 EXITING PROGRAMMING
MODE
Once a device is programmed, it must be taken out of
programmin g mode to star t proper e xecu tion of i ts new
program memory contents.
16.1 4-wire Interface
Exiting programming mode is done by removing V
IH
from the MCLR pin, as illustrated in Figure 16-1. The
only re quirement for exit i s that an interval, P16, shoul d
elapse between the last clock and program signals
before removing V
IH
.
FIGURE 16-1: 4-WIRE EXIT
PROGRAMMING MODE
The following steps are required to exit programming
mode:
1. SetMode (5’b11111).
2. Assert the MCLR pin.
3. Remove pow e r (if the devic e is power ed).
16.2 2-wire Interface
Exiting programming mode is done by removing V
IH
from the MCLR pin, as illustrated in Figure 16-2. The
only requi rement for exit is that an interval, P16, sh ould
elapse between the last clock and program signals on
PGECx and PGEDx before removing V
IH
.
FIGURE 16-2: 2-WIRE EXIT
PROGRAMMING MODE
Use the following steps to exit programming mode:
1. SetMode (5’b11111).
2. Assert the MCLR pin.
3. Issue a clock pulse on PGECx.
4. Remove power (if the device is powered).
MCLR
V
DD
/V
DD
IO
TCK
TMS
TDI
TDO
‘1’‘1’‘0’
P16
MCLR
V
DD
/V
DD
IO
PGEDx
PGECx
P16 P17
V
IH
V
IH
PGEDx = Input
PIC32
DS60001145W-page 38 2007-2018 Microchip Technology Inc.
17.0 THE PROGRAMMI NG
EXECUTIVE
17.1 PE Communication
The programmer and the PE have a master-slave
relationship, where the programmer is the master
programming device and the PE is the slave.
All communication is initiated by the programmer in the
form of a co mman d. The PE is able to rece ive o nly on e
command at a time. Correspondingly, after receiving
and processing a command, the PE sends a single
response to the programmer.
17.1.1 2-WIRE ICSP EJTAG RATE
In Enhanced ICSP mode, the PIC32 family devices
operate from the internal Fast RC oscillator, which has
a nominal frequency of 8 MHz.
17.1.2 COMMU NICATIO N OV ERVIEW
The programmer and the PE communicate using the
EJTAG Address, Dat a and Fastdata registers. In parti c-
ular, the programmer transfers the command and data
to the PE us ing th e Fastdata re gi ste r. The programm er
receives a response from the PE using the Address
and Data registers. The pseudo operation of receiving
a response is shown in the GetPEResponse pseudo
operation below:
Format:
response = GetPEResponse()
Purpose:
Enables the programmer to receive the 32-bit
response value from the PE.
EXAMPL E 17-1:
GetPEResponse
EXAMPLE
The typical communication sequence between the
programmer and the PE is shown in Table 17-1.
The seq uence begin s w hen th e progra mmer sends the
command and optional additional data to the PE, and
the PE carries out the command.
When the PE has finished executing the command, it
sends the response back to the programmer.
The response may contain more than one response.
For example, if the programmer sent a READ
command, the response will contain the data read.
TABLE 17-1: COMMUNICATION
SEQUENCE FOR THE PE
Note: The Programming Executive (PE) is
included with your installation of MPLAB X
IDE. To download the appropriate PE file
for your device, please visit the related
product page on the Microchip web site
(www.microchip.com).
Operation Operand
Step 1: Send command and optional data from
programmer to the PE.
XferFastData (Command | data len)
XferFastData.. optional data..
Step 2: Programmer reads the resp onse from the PE.
GetPEResponse response
GetPEResponse... response...
WORD GetPEResponse()
{
WORD response;
// Wait until CPU is ready
SendCommand(ETAP_CONTROL);
// Check if Proc. Access bit (bit 18) is set
do {
controlVal=XferData(32’h0x0004C000 );
} while( PrAcc(contorlVal<18>) is not ‘1’ );
// Select Data Register
SendCommand(ETAP_DATA);
// Receive Response
response = XferData(0);
// Tell CPU to execute instruction
SendCommand(ETAP_CONTROL);
XferData(32’h0x0000C000);
// return 32-bit response
return response;
}
2007-2018 Microchip Technology Inc. DS60001145W-page 39
PIC32
17.2 The PE Command Set
Table 17-2 provides PE command set details, such
as op code, mnemonic, and short description for
each command. Functional details on each
command are provided in Section 17.2.3
“ROW_PROGRAM Command” through
Section 17.2.14 “CHAN GE_CFG Command”.
The PE sends a response to the programmer for each
comma nd that it recei ves. The resp onse indica tes if the
command was processed correctly. It includes any
required response data or error data.
17.2.1 COMMAND FORMAT
All PE commands have a general format consisting of
a 32-bit header and any required data for the
comma nd, see Figure 17-1. The 32-bit hea der consi sts
of a 16-bit op code field, which is used to identify the
command, and a 16-bit command Operand field. Use
of the Operand field varies by command.
The command in the op code field must match one of
the commands in the command set that is listed in
Table 17-2. Any command received that does not
match a command the list returns a NACK response,
as shown in Table 17-3.
The PE uses the c ommand Op erand fie ld to determ ine
the number of bytes to read from or to write to. If the
value of this field is incorrect, the command is not be
properly received by the PE.
TABLE 17-2: PE COMMAND SET
Note: Some commands have no Operand
information; however, the Operand field
must be sent and the programming
executive will ignore the data.
FIGURE 17-1: COMMAND FORMAT
31 16
Op code
15 0
Operand (optional)
31 16
Command Data High (if required)
15 0
Command Data Low (if required)
Op code Mnemonic Description
0x0 ROW_PROGRAM
(1)
Program one row of Flash memory at the specified address.
0x1 READ Read N 32-bit w ords of me mory star ting from t he spe cified a ddress (N < 65,536 ).
0x2 PROGRAM Program Flash memory starting at the specified address.
0x3 WORD_PROGRAM
(3)
Program one word of Flash memory at the specified address.
0x4 CHIP_ERASE Chip Erase of entire chip.
0x5 PAGE_ERASE Erase pages of code memory from the specified address.
0x6 BLANK_CHECK Blank Check code.
0x7 EXEC_VERSION Read the PE software version.
0x8 GET_CRC Get the CRC of Flash memory.
0x9 PROGRAM_CLUSTER Programs the specified number of bytes to the specified address.
0xA GET_DEVICEID Returns the hardware ID of the device.
0xB CHANGE_CFG
(2)
Used by the probe to set various configuration settings for the PE.
0xC GET_CHECKSUM Get the checksum of Flash memory.
0xD QUAD_WORD_PGRM
(4)
Program four words of Flash memory at the specified address.
Note 1: Refer to Table 5-1 for the row size for each device.
2: This command is not available in PIC32MX1XX/2XX devices.
3: On the PIC32MZ fami ly de vices, whic h incorp orate ECC, the WORD_PROGRAM command will not generate
the ECC parity bits. Reading a locat ion programmed with the WORD_PROGRAM command with ECC enabled
will cause a DED fault.
4: This command is available on PIC32MK and PIC32MZ family devices only.
PIC32
DS60001145W-page 40 2007-2018 Microchip Technology Inc.
17.2.2 RESPONSE FORMAT
The PE response set is shown in Table 17-3. All PE
responses have a general format consisting of a 32-bit
header and any required data for the response (see
Figure 17-2).
17.2.2.1 Last_Cmd Fiel d
Last_Cmd is a 16-bit field in the first word of the
response and indicates the command that the PE
processed. It can be used to verify that the PE correctly
received the command that the programmer
transmitted.
17.2.2.2 Response Code
The response code indicates whether the last
command succeeded or failed, or if the command is a
value th at is not recog nized. The res ponse code va lues
are shown in Table 17-3.
17.2.2.3 Optional Data
The resp onse head er may be followed by optional data
in case of certain commands such as read. The
number of 32-bit words of optional data varies
depending on the last command operation and its
parameters.
17.2.3 ROW_PROGRAM COMMAND
The ROW_PROGRAM command instructs the PE to
program a row of data at a specified address.
The data to be programmed to memory, located in
command words Data_1 through Data_N, must be
arranged using the packed instruction word format
provided in Table 17-4 (this command expects an
entire row of data).
Expected Response (1 word):
FIGURE 17-4: ROW_PROGRAM RESPONSE
FIGURE 17-2: RESP ON SE FORMAT
31 16
Last Command
15 0
Response Code
31 16
Data_High_1
15 0
Data_Low_1
31 16
Data_High_N
15 0
Data_Low_N
TABLE 17-3: RESPONSE VALUES
Op code Mnemonic Description
0x0 PASS Command successfully
processed
0x2 FAIL Command unsuccessfully
processed
0x3 NACK Command not known
FIGURE 17-3: ROW_PROGRAM COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
31 16
Data_High_1
15 0
Data_Low_1
31 16
Data_High_N
15 0
Data_Low_N
TABLE 17-4: ROW_PROGRAM FORMAT
Field Description
Op code 0x0
Operand Not used
Addr_High High 16 bits of 32-bit destination
address
Addr_Low Low 16 bits of 32-bit destination
address
Data_High_1 High 16 bits data word 1
Data_Low_1 Low 16 bits data word 1
Data_High_N High 16 bits data word 2 through N
Data_Low_N Low 16 bits data word 2 through N
31 16
Last Command
15 0
Response Code
2007-2018 Microchip Technology Inc. DS60001145W-page 41
PIC32
17.2.4 READ COMMAND
The READ command instructs the PE to read from
memory. The number of 32-bit words specified in the
Operand field s tarting f rom th e 32-bit address sp ecified
by the Addr_Low and Addr_High fields. This command
can be used to read Flash memory and Configuration
Words. All data returned in response to this command
uses the packed data format that is provided in
Table 17-5.
Expected Response:
FIGURE 17-6: READ RESPONSE
17.2.5 PROGRAM COMMAND
The PROGRAM command instructs the PE to program
the Flash memory, including Configuration Words,
starting from the 32-bit address specified in the
Addr_Low and Addr_High fields. A 32-bit length field
specifies the number of bytes to program.
The address must be aligned to a Flash row size
boundary and the length must be a multiple of a Flash
row size. See Table 5-1 for the correct row size for the
device to be programmed.
FIGURE 17-5: READ COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
TABLE 17-5: READ FORMAT
Field Description
Op code 0x1
Operand N number of 32-bit words to read
(maximum of 65,535)
Addr_Low Low 16 bits of 32-bit source address
Addr_High High 16 bits of 32-bit source
address
31 16
Last Command
15 0
Response Code
31 16
Data_High_1
15 0
Data_Low_1
31 16
Data_High_N
15 0
Data_Low_N
Note: Reading unimplemented memory will
cause the PE to Reset. Ensure that only
memory locations present on a particular
device are accessed.
FIGURE 17-7: PROGRAM COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
31 16
Length_High
15 0
Length_Low
31 16
Data_High_1
15 0
Data_Low_1
31 16
Data_High_N
15 0
Data_Low_N
TABLE 17-6: PROGRAM FORMAT
Field Description
Op code 0x2
Operand Not used
Addr_Low Low 16 bits of 32-bit destination
address
Addr_High High 16 bits of 32-bit destination
address
Length_Low Low 16 bits of Length
Length_High High 16 bits Length
Data_Low_N Low 16 bits data word 2 through N
Data_High_N High 16 bits data word 2 through N
PIC32
DS60001145W-page 42 2007-2018 Microchip Technology Inc.
The following are three programming scenarios:
• The length of the data to be programmed is the
size of a single Flash row
• The length of the data to be programmed is the
size of two Flash rows
• The l ength o f the da ta to be program med i s larger
than the size of two Flash rows
When the data length is equal to 512 bytes, the PE
receive s the 51 2-byte block of data fro m the probe an d
immediately sends the response for this command
back to the probe.
The PE will respond for each row of data that it
receives. If the data length of the command is equal to
a sing l e ro w, a si n gle P E r e sp onse i s ge ne ra t ed . I f the
data length is equal to two rows, the PE waits to
receive both rows of data, and then sends back-to-
back responses for each data row. If the data length is
greater than two rows of data, the PE will send the
response for the first row after receiving the first two
rows of data. Subsequent responses are sent after
receiving subsequent data row packets. The
responses will lag the data by one row. When the last
row of data is received, the PE will respond with back-
to-back responses for the second-to-last data row
followed by the last row.
If the PE encounters an error in programming any of
the blocks, it sends a failure status to the probe and
aborts t he PROGRAM co mmand. On receiving the failure
status, the probe must stop sending data. The PE will
not process any other data for this command from the
probe. The process is illustrated in Figure 17-9.
The respons e for this com ma nd is a lit tle di f fe rent than
the respon se for oth er comm ands. The 16 MSb s of the
response contain the 16 LSbs of the destination
address, where the last block is programmed. This
helps the probe and the PE maintain proper
synchronization of sending and receiving data and
responses.
Expected Response (1 word):
FIGURE 17-8: PROGRAM RESPONSE
Note: If the PROGRAM command fails, the
programmer should read the failing row
using the READ command from the Flash
memory. Then the programmer should
compare the row received from the Flash
memory to its local co py , word-b y-word, to
determine the address where Flash
programming fails.
31 16
LSB 16 bits of the destination address of last block
15 0
Response Code
2007-2018 Microchip Technology Inc. DS60001145W-page 43
PIC32
FIGURE 17-9: PROGRAM COMMAND ALGORITHM
Done
Receive status
for Row N
Receive status
for Row N-1
Receive status
for Row 2
Receive status
for Row 2
Receive status
for Row 1
Receive status
(LSB 16 bits of
Destination Address
Status Value)
Send first row
of data
Start
Send one row
of data
Receive status
for Row 1
Data is Data is
equal to a
single row equal to
two rows
Data
is larger than
two rows
Send first row
of data
Send second row
of data Send second row
of data
Send third row
of data
Send Nth row
of data
PIC32
DS60001145W-page 44 2007-2018 Microchip Technology Inc.
17.2.6 WORD_PROGRAM COMMAND
The WORD_PROGRAM command instructs the PE to
program a 32-bit word of data at the specified address.
Expected Response (1 word):
FIGURE 17-11: WORD_PROGRAM
RESPONSE
17.2.7 CHIP_ERASE COMMAND
The CHIP_ERASE command erases the entire chip,
including the configuration block.
After the erase is performed, the entire Flash memory
contains 0xFFFFFFFF.
Expected Response (1 word):
FIGURE 17-13: CHIP_ERASE RESPONSE
FIGURE 17-10 : WORD_PROGRAM
COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
31 16
Data_High
15 0
Data_Low
TABLE 17-7: WORD_PROGRAM FORMAT
Field Description
Op code 0x3
Operand Not used
Addr_High High 16 bits of 32-bit destination
address
Addr_Low Low 16 bits of 32-bit destination
address
Data_High High 16 bits data word
Data_Low Low 16 bits data word
31 16
Last Command
15 0
Response Code
FIGURE 17-12: CHIP_ERASE COMMAND
31 16
Op code
15 0
Operand
TABLE 17-8: CHIP_ERASE FORMAT
Field Description
Op code 0x4
Operand Not used
Addr_Low Low 16 bits of 32-bit destination
address
Addr_High High 16 bits of 32-bit destination
address
31 16
Last Command
15 0
Response Code
2007-2018 Microchip Technology Inc. DS60001145W-page 45
PIC32
17.2.8 PAGE_ERASE COMMAND
The PAGE_ERASE command erases the specified
number of pages of code memory from the specified
base address. Depending on the device, the specified
base address must be a multiple of 0x400 or 0x100.
After the e rase is p erformed, all targete d words of code
memory contain 0xFFFFFFFF.
Expected Response (1 word):
FIGURE 17-15 : PAGE_ERASE RESPONSE
17.2.9 BLANK_CHECK COMMAND
The BLANK_CHECK command queries the PE to
determine whether the contents of code memory and
code-protect Configuration bits (GCP and GWRP) are
blank (contains all ‘1’s).
Expected Response (1 word for blank device):
FIGURE 17-17: BLANK_CHECK RESPONSE
FIGURE 17-14 : PAGE_ERASE COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
TABLE 17-9: PAGE_ERASE FORMAT
Field Description
Op code 0 x 5
Operand Number of pages to erase
Addr_Low Low 16 bits of 32-bit destination
address
Addr_High High 16 bits of 32-bit destination
address
31 16
Last Command
15 0
Response Code
FIGURE 17-16: BLANK_CHECK COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
31 16
Length_High
15 0
Length_Low
TABLE 17-10: BLANK_CHECK FORMAT
Field Description
Op code 0x6
Operand Not used
Address Address where to start the Blank
Check
Length Numbe r of prog ram me mory locatio ns
to check in terms of bytes
31 16
Last Command
15 0
Response Code
PIC32
DS60001145W-page 46 2007-2018 Microchip Technology Inc.
17.2.10 EXEC_VERSION COMMAND
EXEC_VERSION queries for the version of the PE
software stored in RAM.
Expected Response (1 word):
FIGURE 17-19 : EXEC_VERSION
RESPONSE
17.2.11 GET_CRC COMMAND
GET_CRC calculates the CRC of the buffer from the
specified address to the specified length, using the
table look -up method. The CRC deta il s are as foll ows:
• CRC-CCITT, 16-bit
• Polynomial: X^16+X^12+X^5+1, hex 0x00011021
• Se ed: 0xFFFF
• Most Significant Byte (MSB) shifted in first
Expected Response (2 words):
FIGURE 17-21: GET_CRC RESPONSE
FIGURE 17-18 : EXEC_VERSION
COMMAND
31 16
Op code
15 0
Operand
TABLE 17-11: EXEC_VERSION FORMAT
Field Description
Op code 0x7
Operand Not used
31 16
Last C ommand
15 0
Version Number
Note 1: In the response, only the CRC Least
Significant 16 bits are valid.
2: The PE wi ll automa tically det ermine if the
hardware CRC is available and use it by
default. The hardware CRC is not used
on PIC32MX1XX/2XX devices.
FIGURE 17-20: GET_CRC COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
31 16
Length_High
15 0
Length_Low
TABLE 17-12: GET_CRC FORMAT
Field Description
Op code 0x8
Operand Not used
Address Address where to start calculating the
CRC
Length Length of buffer on which to calculate
the CRC, in number of bytes
31 16
Last Command
15 0
Response Code
31 16
CRC_High
15 0
CRC_Low
2007-2018 Microchip Technology Inc. DS60001145W-page 47
PIC32
17.2.12 PROGRAM_CLUSTER COMMAND
PROGRAM_CLUSTER prog rams the spe cified n umber of
bytes to the specified address. The address must be
32-bit aligned, and the number of bytes must be a
multiple of a 32-bit word.
Expected Response (1 word):
FIGURE 17-23 : PROGRAM_CLUSTER
RESPONSE
17.2.13 GET_DEVICEID COMMAND
The GET_DEVICEID command returns the hardware
ID of the device.
Expected Response (1 word):
FIGURE 17-25: GET_DEVICEID
RESPONSE
FIGURE 17-22 : PROGRAM_CLUSTER
COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
31 16
Length_High
15 0
Length_Low
TABLE 17-13: PROGRAM_CLUSTER FO R MAT
Field Description
Op code 0x9
Operand Not used
Address Start address for programming
Length Length of area to program in number
of bytes
Note: If the PROGRAM_CLUSTER command fails,
the programmer s hould read the failing row
using the READ command from the Flash
memory. Then the programmer should
compare the row received from the Flash
memory to its local copy word-by-word to
determine the address where Flash
programming fails.
31 16
Last C ommand
15 0
Response Code
FIGURE 17-24: GET_DEVICEID
COMMAND
31 16
Op code
15 0
Operand
TABLE 17-14: GET_DEVICEID FORMAT
Field Description
Op code 0xA
Operand N ot us ed
31 16
Last Command
15 0
Device ID
PIC32
DS60001145W-page 48 2007-2018 Microchip Technology Inc.
17.2.14 CHANGE_CFG COMMAND
Expected Response (1 word):
FIGURE 17-27 : CHANGE_CFG RESPONSE
17.2.15 GET_CHECKSUM COMMAND
Expected Response (1 word):
FIGURE 17-29: GET_CHECKSUM
RESPONSE
CHANGE_CFG is used by the probe to set various
configuration settings for the PE. Currently, the single
configuration setting determines which of the following
calcul ati on me thod s the PE shoul d use :
• Software CRC calculation method
• Hardware calculation method
FIGURE 17-26 : CHANGE_CFG COMMAND
31 16
Op code
15 0
Operand
31 16
CRCFlag_High
15 0
CRCFlag_Low
TABLE 17-15: CHANGE_CFG FORMAT
Field Description
Op code 0xB
Operand Not used
CRCFlag If the value is ‘0’, the PE uses the
software CRC calculation method.
If the value is ‘1’, the PE uses the
hardware CRC unit to calculate the
CRC.
31 16
Last C ommand
15 0
Response Code
Note: The CHANGE_CFG command is not
available in PIC32MX1XX/2XX devices.
GET_CHECKSUM returns the sum of all the bytes
starting at the address argument up to the length
argumen t. The result is a 32-bit word.
FIGURE 17-28: CHANGE_CFG COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
31 16
Length_High
15 0
Length_Low
TABLE 17-16: GET_CHECKSUM FORMAT
Field Description
Op code 0x0C
Operand Not used
Addr_Hi gh High-ord er 16 bits of the 32-bit starting
address of the data to calculate the
checksum for.
Addr_Low Low-order 1 6 b its o f th e 32-bit sta rtin g
address of the data to calculate the
checksum for.
Length_High High-order 16 bits of the 32-bit length
of data to calculate the checksum for
in bytes.
Length_Low Low-order 16 bits of the 32-bit length
of data to calculate the checksum for
in bytes.
31 16
Last Command
15 0
Response Code
31 16
Checksum_High
15 0
Checksum_Low
2007-2018 Microchip Technology Inc. DS60001145W-page 49
PIC32
17.2.16 QUAD_WORD_PROGRAM COMMAND
Expected Response (1 word):
FIGURE 17-31: QUAD_WORD_PROGRAM
RESPONSE
QUAD_WORD_PROGRAM instructs the PE to program
four, 32-bit words at the specified address. The
address must be an aligned four wo rd boundary (bi ts 0-
1 must be ‘0’). If not, the command will return a FAIL
response value and no data will be programmed.
FIGURE 17-30 : QUAD_WORD_PROGRAM
COMMAND
31 16
Op code
15 0
Operand
31 16
Addr_High
15 0
Addr_Low
31 16
Data0_High
15 0
Data0_Low
31 16
Data1_High
15 0
Data1_Low
31 16
Data2_High
15 0
Data2_Low
31 16
Data3_High
15 0
Data3_Low
TABLE 17-17: QUAD_WORD_PROGRAM
FORMAT
Field Description
Op code 0x0D
Operand Not used
Addr_Hi gh High-order 16 bits of the 32-bit sta rting
address.
Addr_Low Low -order 16 bits of th e 32-bit starting
address.
Data0_High High-order 16 bits of data word 0.
Data0_Low Low-order 16 bits of data word 0.
Data1_High High-order 16 bits of data word 1.
Data1_Low Low-order 16 bits of data word 1.
Data2_High High-order 16 bits of data word 2.
Data2_Low Low-order 16 bits of data word 2.
Data3_High High-order 16 bits of data word 3.
Data3_Low Low-order 16 bits of data word 3.
31 16
Last Command
15 0
Response Code
TABLE 17-17: QUAD_WORD_PROGRAM
FORMAT
PIC32
DS60001145W-page 50 2007-2018 Microchip Technology Inc.
18.0 CHECKSUM
18.1 Theory
The che cksum is c alculate d as the 32 -bit summ ation of
all byte s (8-bi t quanti ties) i n progra m Flas h, Boot Flas h
(except device Configuration Words), the Device ID
register with applicable mask, and the device Configu-
ration Words with applicable masks. Then the 2’s
complement of the summation is calculated. This final
32-bit number is presented as the checksum.
18.2 Mask Values
The mask value of a dev ice Conf igu ration is calcu lated
by setting all the unimplemented bits to ‘0’ and all the
implemented bits to ‘1’.
For example, Register 18-1 shows the DEVCFG0
register of the PIC32MX360F512L device. The mask
value for this register is:
mask_value_devcfg0 = 0x110FF00B
REGISTER 18-1: DEVCFG0 REGISTER OF PIC32MX360F512L
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-0 r-1 r-1 R/P-1 r-1 r-1 r-1 R/P-1
— — —CP— — —BWP
23:16
r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1 R/P-1
— — — — PWP19 PWP18 PWP17 PWP16
15:8
R/P-1 R/P-1 R/P-1 R/P-1 r-1 r-1 r-1 r-1
PWP15 PWP14 PWP13 PWP12 — — — —
7:0
r-1 r-1 r-1 r-1 R/P-1 r-1 R/P-1 R/P-1
— — — — ICESEL — DEBUG<1:0>
Legend: P = Progr ammable bit r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2007-2018 Microchip Technology Inc. DS60001145W-page 51
PIC32
Table 18-1 lists the mask values of the four device Co n-
figuration registers and Device ID registers to be used
in the checksum calculations for PIC32MX, PIC32MZ,
and PIC32MK devices.
TABLE 18-1: DEVICE CONFIGURATION REGISTER MASK VALUES OF CURRENTLY
SUPPORTED PIC32MX, PIC32MZ, AND PIC32MK DEVICES
Device Family Flash
Memory
Sizes (KB) DEVCFG0 DEVCFG1 DEVCFG2 DEVCFG3 DEVCFG4 DEVID
PIC32MX110/120/130/
150F0xx
PIC32MX150F128
(28/36/44-pin devices
only)
16, 32, 64,
128 0x1100FC1F 0x03DFF7A7 0x00070077 0xF000FFFF — 0x0FFFFFFF
PIC32MX130F128/256
PIC32MX150F256
(28/36/44-pin devices
only)
16, 32, 64,
128 0x1100FC1F 0x03DFF7A7 0x00070077 0xF0000000 — 0x0FFFFFFF
PIC32MX 210/220/230/
250 (28/36/44-pin
devices only)
16, 32, 64,
128 0x1100FC1F 0x03DFF7A7 0x00078777 0xF0000000 — 0x0FFFFFFF
PIC32MX 15X/17X (28/
44-pin devices only) 128,256 0x1187F01F 0x03FFF7A7 0xFFB700F7 0x30C00000 — 0x0FFFFFFF
PIC32MX 25X/27X (28/
44-pin devices only) 128,256 0x1187F01F 0x03FFF7A7 0xFFB787F7 0x70C00000 — 0x0FFFFFFF
PIC32MX 320/340/360 32, 64, 128,
256, 512 0x110FF00B 0x009FF7A7 0x00070077 0x0000FFFF — 0x000FF000
PIC32MX
420/440/460 32, 64, 128,
256, 512 0x110FF00B 0x009FF7A7 0x00078777 0x0000FFFF — 0x000FF000
PIC32MX110/120/130/
150F0xx
PIC32MX150F128
PIC32MX170F256
(64/100-pin Devices
only)
64, 128, 256,
512 0x110FFC1F 0x03DFF7A7 0x00070077 0xF000FFFF — 0x0FFFFFFF
PIC32MX130F128/256
PIC32MX150F256
PIC32MX170F512
(64/100-pin Devices
only)
64, 128, 256,
512 0x110FFC1F 0x03DFF7A7 0x00070077 0xF0000000 — 0x0FFFFFFF
PIC32MX230F0xx
PIC32MX250F128
PIC32MX270F256
(64/100-pin Devices
only)
64, 128, 256,
512 0x110FFC1F 0x03DFF7A7 0x00078777 0xF000FFFF — 0x0FFFFFFF
Note 1: Applicable only to PIC32MZ DA family devices.
PIC32
DS60001145W-page 52 2007-2018 Microchip Technology Inc.
PIC32MX230F128
PIC32MX230F256
PIC32MX250F256
PIC32MX270F512
PIC32MX530
PIC32MX550
PIC32MX570
(64/100-pin devices
only)
64, 128, 256,
512 0x110FFC1F 0x03DFF7A7 0x00078777 0xF0000000 — 0x0FFFFFFF
PIC32MX 330/350/370 64, 128, 256,
512 0x110FF01F 0x03DFF7A7 0x00070077 0x3007FFFF — 0x0FFFFFFF
PIC32MX 430/450/470 64, 128, 256,
512 0x110FF01F 0x03DFF7A7 0x00078777 0xF007FFFF — 0x0FFFFFFF
PIC32MX
534/564 64, 128 0x110FF00F 0x009FF7A7 0x00078777 0xC407FFFF — 0x0FFFF000
PIC32MX
664 64, 128 0x110FF00F 0x009FF7A7 0x00078777 0x C307FFFF — 0x0FFFF000
PIC32MK
0512/1024XXD/E/F 512 , 1024 0x7FFFFFFF 0xFFFFFFFF 0xF FFFF FFF 0xFFFF0000 — 0x0FFFFFF F
PIC32MK
[0512/1024XXK/L/M 512, 1024 0x 4BFFF77F 0xFFFFC7FF 0xBFF77FF7 0xF8D0FFFF 0xFF000000 0x0FFFFFFF
PIC32MK
0256/0512XXH/G/J 256 , 512 0x4BFFF77F 0xFFFFC7FF 0x3FF77F F7 0x3810FFFF 0xFF000000 0x0FFFFFFF
PIC32MX
764 128 0x110FF00F 0x009FF7A7 0x00078777 0xC707FFFF — 0x0FFFF000
PIC32MX170F256
(28/36/44-pin devices
only) 256 0x1107FC1F 0x03DFF7A7 0x00070077 0xF000FFFF — 0x0FFFFFFF
PIC32MX170F512
(28/36/44-pin devices
only) 256 0x1107FC1F 0x03DFF7A7 0x00070077 0xF0000000 — 0x0FFFFFFF
PIC32MX270F25 6
(28/36/44-pin devices
only) 256 0x1107FC1F 0x03DFF7A7 0x00078777 0xF000FFFF — 0x0FFFFFFF
PIC32MX270F512
(28/36/44-pin devices
only) 256 0x1107FC1F 0x03DFF7A7 0x00078777 0xF0000000 — 0x0FFFFFFF
PIC32MZ
05XX/10XX/20XX 512, 1024,
2048 0x7FFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFF0000 0xFFFFFFFF
(see Note 1)0x0FFFFFFF
PIC32MX
575 256, 512 0x110FF00F 0x009FF7A7 0x00078777 0xC407F FFF — 0x000FF000
PIC32MX
675/695 256, 512 0x110FF00F 0x009F F7A7 0x00078777 0xC307FFFF — 0x 000FF000
PIC32MX
775/795 256, 512 0x110FF00F 0x009F F7A7 0x00078777 0xC707FFFF — 0x 000FF000
TABLE 18-1: DEVICE CONFIGURATION REGISTER MASK VALUES OF CURRENTLY
SUPPORTED PIC32MX, PIC32MZ, AND PIC32MK DEVICES (CONTINUED)
Device Family Flash
Memory
Sizes (KB) DEVCFG0 DEVCFG1 DEVCFG2 DEVCFG3 DEVCFG4 DEVID
Note 1: Applicable only to PIC32MZ DA family devices.
2007-2018 Microchip Technology Inc. DS60001145W-page 53
PIC32
18.3 Algorithm
Figure 18-1 illustrates an example of a high-level algo-
rithm for calculating the checksum for a PIC32 device to
demonst rate one me thod to de rive a che cksum. This is
merely an example of how the actual calculations can be
accomplished, the method that is ultimately used is left to
the disc reti on of the softwa re de velo per.
As stated earlier, the PIC32 checksum is calculated as
the 32-bit summation of all bytes (8-bit quantities) in
program Flash, Boot Flash (except device
Configuration Words), the Device ID register with
applicable mask, and the device Configuration Words
with applicable masks.
Then the 2’s complement of the summation is
calcul ated. This final 3 2-bit num ber is pres ented a s the
checksum.
The mask values of the device Configuration and
Device ID registers are derived as described in the
previous section, Section 18.2 “Mask Values”.
An arithmetic AND operation of these device
Configuration register values is performed with the
appropriate mask value, before adding their bytes to
the checksum.
Similarly, an arithmetic AND operation of the Device ID
register is performed with the appropriate mask value,
before adding its bytes to the checksum, see
Section 19.0 “Configuration Memory and Device
ID” for more information.
FIGURE 18-1: HIGH-LEVEL ALGORI THM FOR CHECKSUM CALCULATION
pic32_checksum
Read Program Flash, Boot Flash (including DEVCFG
registers) and DEVID register in tmpBuffer
Apply DEVCFG and DEVID masks to appropriate
locations in tmpBuffer
tmpChecksum (32-bit quantity) = 0
Finish processing all
bytes (8-bit quantities) in
tmpBuffer?
tmpChecksum = tmpChecksum + Current Byte Value
(8-bit quantity) in tmpBuffer
Checksum (32-bit quantity) = 2’s complement
of tmpChecksum
Done
No
Yes
PIC32
DS60001145W-page 54 2007-2018 Microchip Technology Inc.
The formula to calculate the checksum for a PIC32
device is provided in Equation 18-1.
EQUATION 18-1: CHECKSUM FORMULA
Checksum 2s complement PF BF DCR DIR++ +=
DCR y
X0=32-bit summation of bytes MASK
DEVCFGX
& DEVCFGx=
DIR 32-bit summation of bytes MASK
DEVID
& DEVID=
Where,
PF = 32-bit summation of all bytes in Program Flash
BF = 32-bit summation of all bytes in Boot Flash, except device Configuration registers (see Note 1)
MASK
DEVCFGX
= mask value from Table 18-1
MASK
DEVID
= mask value from Table 18-1 (see Note 2)
Note 1: For PIC32MZ family devices, the Boot Flash memory that resides at 0x1FCxFF00 through
0x1FCxFFFF is not summed, as these memory locations contain the device configuration and CP
values . For PIC32MK family de vices, the Boot Flash m emory that res ides at 0x1FC 03F0 0 through
0x1FC03FF F is no t summed.
2: For PIC32MZ and PIC32MK family devices, the checksum calculated in MPLAB X IDE only uses
the primary DEVCFGx registers. Neither the alternate nor second Boot Flash (if available)
registers are calculated.
Where,
y = 3 for PIC32MX, PIC32MK, PIC32MZ EC, and PIC32MZ EF family devices
y = 4 for all other PIC32MZ family devices
DEVCP = 32-bit summation of bytes (MASK
DEVCP
& DEVCP)
Where,
MASK
DEVCP
= 0x10000000 for PIC32MK
2007-2018 Microchip Technology Inc. DS60001145W-page 55
PIC32
18.4 Example of Checksum Calculation
The following five sections demonstrate a checksum
calculation for the PIC32MX360F512L device using
Equation 18-1.
The follow ing assump tions are made for the purp ose of
this checksum calculation example:
• Program Flash and Boot Flash are in the erased
state (all bytes are 0xFF)
• Device Configuration is in the default state of the
device (no configuration changes are made)
Each item on the right side of the equation (PF, BF,
DCR, DIR) is individ ually calculated. After deriving the
values, the final value of the checksum can be
calculated.
18.4.1 C ALCULATING FOR “PF” IN THE
CHECKSUM FORM ULA
The size of Program Flash is 512 KB, which equals
524288 bytes. Since the program Flash is assumed to
be in erased state, the value of PF is resolved through
the following calculation:
PF = 0xFF + 0xFF + … 524288 times
PF = 0x7F80000 (32-b it num be r)
18.4.2 CALCULATING FOR “BF” IN THE
CHECKSUM FORMULA
The size of the Boot Flash is 12 KB, which equals
12288 bytes. However, the last 16 bytes are device
Configuration registers, which are treated separately.
Therefore, the number of bytes in Boot Flash that we
consider in this step is 12272. Since the Boot Flash is
assumed to be in erased state, the value of “BF” is
resolved through the following calculation:
BF = 0xFF + 0xFF + … 12272 times
BF = 0x002FC010 (32-bit number)
18.4.3 CALCULATING FOR “DCR” IN THE
CHECKSUM FORMULA
Since the device Configuration registers are left in their
default state, the value of the appropriate DEVCFG
register – as read by the PIC32 core, its respective
mask v alu e, t he v al ue d eriv ed from apply in g the mask,
and the 32-bit summation of bytes (all as shown in
Table 18-2) provide th e tot al of th e 32-bit summ ation of
bytes.
From Table 18-2, the value of “DCR” is:
DCR = 0x000003D6 (32-bit number)
TABLE 18-2: DCR CALCULATION EXAMPLE
Register POR Default Va lue Mask POR Default Value &
Mask 32-Bit Summation of
Bytes
DEVCFG0 0x7FFFFFFF 0x110FF00B 0x110FF00B 0x0000011B
DEVCFG1 0xFFFFFFFF 0x009FF7A7 0x009FF7A7 0x0000023D
DEVCFG2 0xFFFFFFFF 0x00070077 0x00070077 0x0000007E
DEVCFG3 0xFFFFFFFF 0x00000000 0x00000000 0x00000000
Total of the 32-bit Summation of Bytes = 0x000003D6
PIC32
DS60001145W-page 56 2007-2018 Microchip Technology Inc.
18.4.4 CALCULATING FOR “DIR” IN THE
CHECKSUM FORM ULA
The value of Dev ice ID register and i ts ma sk val ue, the
value derived from applying the mask, and the 32-bit
summation of bytes are shown in Table 18-3.
From Table 18-3, the value of “DIR” is:
DIR = 0x00000083 (32-bit number.)
18.4.5 COMPLETING THE PIC32
CHECKSUM CAL CULATION
The values derived in previous sections (PF, BF, DCR,
DIR) are used to calculate the checksum value.
Perform the 32-bit summation of the PF, BF, DCR and
DIR as derived in previous sections and store it in a
variable, called temp, as shown in Example 18-1.
EXAMPLE 18-1: CHECKSUM CALCULATION PROCESS
18.4.6 CHECKSUM VALU ES WHILE
DEVICE IS CODE-PROTECTED
Since the device Confi guration W ords are no t readable
while the PIC32 devices are in code-protected state,
the checksum values are zeros for all devices.
TABLE 18-3: DIR CALCULATION EXAMPLE
Register POR Default Value Mask POR Default Value
& Mask 32-Bit Summation of
Bytes
DEVID 0x00938053 0x000FF000 0x00038000 0x00000083
1. First, temp = PF + BF + DCR + DIR, which translates to:
temp = 0x7F80000 + 0x002FC010 + 0x000003D6 + 0x00000083
2. Adding all four values resul ts in temp being equal to 0x0827 C469
3. Finally, the 2’s complement of temp is the checksum:
Checksum = 2’s complement (temp), which is Checksum = (1’s complement (temp)) + 1, resulting in
0xF7D83B97
2007-2018 Microchip Technology Inc. DS60001145W-page 57
PIC32
19.0 CONFIGURATION MEMORY
AND DEVICE ID
PIC32 devices include several features intended to
maximize application flexibility and reliability, and
minimize cost through elimination of external
components. These features are configurable through
specific Configuration bits for each device.
Refer to the “Spe cial Feature s” chapter in the specifi c
device data sheet for a full list of available features,
Configuration bits, and the Device ID register.
Refer to Appendix C: “Device IDs” to locate the
Device ID for a particular PIC32MX, PIC32MZ, or
PIC32MK family of devices.
For the current silicon revision and revision ID for a
particular device, refer to the related Family Silicon
Errata and Data Sheet Clarification. These
documents are available for download from the
Microchip web site: http://www.microchip.com/PIC32
and navigating to: Documentation > Errata.
19.1 Device Configuration
In PIC32 devices, the Configuration Words select
various device configurations that are set at device
Reset prior to exe cutio n of an y code. The se valu es are
located at the hi ghest loc ations o f the Boot Flas h Mem-
ory (BFM) and since they are part of th e program mem-
ory, are included in the programming file along with
executable code and program constants. The names
and locat ions of these Configuration Words are listed in
Table 19-1 through Table 19-4.
Additionally, Table 19-3 and Table 19-4 include Confi g-
uration Words for PIC32MZ and PIC32MK family
devices, respectively, with dual boot and dual panel
Flash. Refer to Section 48. “Memory Organization
and Permissions” (DS60001214) of the “PIC32
Family Reference Manual” for a detailed description of
the dual boot regions.
TABLE 19-1: DEVCFG LOCATIONS FOR
15X/17X/25X/27X AND
PIC32MX3XX/4XX/5XX/6XX/
7XX DEVICES ONLY
TABLE 19-2: DEVCFG LOCATIONS FOR 28/
36/44-PIN PIC32MX1XX/2XX
AND 64/100-PIN PIC32MX1XX/
2XX/5XX DEVICES ONLY
On Power-on Reset (POR) or any Reset, the
Configuration Words are copied from the Boot Flash
memory to their c orresp ondin g Config urat ion reg isters.
A Configuration bit can only be programmed = 0
(unprogram m ed sta te = 1).
During programming, a Configuration Word can be
programmed a maximum of two times for PIC32MX
device s and o nly one ti me f or P IC32M Z, and PIC32M K
fa mily devices be fore a page era se must be p erformed.
After programming the Configuration Words, a device
Reset will cause the new values to be loaded into the
Configuration registers. Because of this, the programmer
should program the Configuration Words just prior to ver-
ification of t he device. The fina l step is progr amming the
code protection Configuration Word.
These Configuration Words determine the oscillator
source. If using the 2-wire Enhanced ICSP mode the
Configuration Words are ignored and the device will
always use the FRC; however, in 4-wire mode this is
not the case. If an oscillator source is selected by the
Configuration Words that is not present on the device
after Re set, t he prog ramme r will n ot be able to perform
Flash operations on the device after it is Rese t. See the
“Special F eatures” chapter in t he specif ic device da ta
sheet for deta ils regarding os cillator selec tion using the
Configuration Words.
Configuration Word Physical Address
DEVCFG0 0x1FC02FFC
DEVCFG1 0x1FC02FF8
DEVCFG2 0x1FC02FF4
DEVCFG3 0x1FC02FF0
Configuration Word Physical Address
DEVCFG0 0x1FC00BFC
DEVCFG1 0x1FC00BF8
DEVCFG2 0x1FC00BF4
DEVCFG3 0x1FC00BF0
PIC32
DS60001145W-page 58 2007-2018 Microchip Technology Inc.
TABLE 19-3: CONFIGURATION WORD LOCATIONS FOR PIC32MZ FAMILY DEVICES
TABLE 19-4: CONFIGURATION WORD LOCATIONS FOR PIC32MKXXXXXXD/E/FXX FAMILY
DEVICES
Configuration Word
(see Note 1)
Registe r Physical Address
Fixed Boot
Region 1 Fixed Boot
Region 2
Active Boot
Alias Region
(see Note 2)
Inactive Boot
Alias Region
(see Note 2)
Boot Sequence Number 0x1FC4FFF0 0x1FC6FFF0 0x1FC0FFF0 0x1FC2FFF0
Code Protection 0x1FC4FFD0 0x1FC6FFD0 0x1FC0FFD0 0x1FC2FFD0
DEVCFG0 0x1FC4FFCC 0x1FC6FFCC 0x1FC0FFCC 0x1FC2FFCC
DEVCFG1 0x1FC4FFC8 0x1FC6FFC8 0x1FC0FFC8 0x1FC2FFC8
DEVCFG2 0x1FC4FFC4 0x1FC6FFC4 0x1FC0FFC4 0x1FC2FFC4
DEVCFG3 0x1FC4FFC0 0x1FC6FFC0 0x1FC0FFC0 0x1FC2FFC0
DEVCFG4 (see Note 3) 0x1FC4FFBC 0x1FC6FFBC 0x1FC0FFBC 0x1FC2FFBC
Alternate Boot Sequence Number 0x1FC4FF70 0x1FC6FF70 0x1FC0FF70 0x1FC2FF70
Alternate C ode Protection 0x1FC4FF50 0x1FC6FF 50 0x1FC0FF50 0x1F C2FF5 0
Alternate DEVCFG0 0x1FC4FF4 C 0x1FC6FF4C 0x1FC0FF4C 0x1FC2FF4C
Alternate DEVCFG 1 0x1FC4FF48 0x1FC6FF48 0x1FC0FF48 0x1FC2FF48
Alternate DEVCFG 2 0x1FC4FF44 0x1FC6FF44 0x1FC0FF44 0x1FC2FF44
Alternate DEVCFG 3 0x1FC4FF40 0x1FC6FF40 0x1FC0FF40 0x1FC2FF40
Alternate DEVC FG4 (see Note 3) 0x1FC4FF3C 0x1FC6FF3C 0x1FC0FF3C 0x1FC2FF3C
Note 1: All values in the 0x1FCxFF00-0x1FCxFFFF memory regions should be programmed using the
QUAD_WORD_PROGRAM command to ensure proper ECC configuration. Refer to Section 17.2.16
“QUAD_WORD_PROG RAM Command” for details.
2: Active/Inactive boot alias selections are assumed for an unprogrammed device where Fixed Region 1 is
active and Fixed Region 2 is inactive. Refer to Section 48. “Memory Organization and Permissions”
(DS60001214) for a detailed description of the alias boot regions.
3: These Configuration Words are available only on PIC32MZ DA family devices.
Configuration Word
(see Note 1)
Registe r Physical Address
Fixed Boot
Region 1
Fixed Boot
Region 2 Active Boot
Alias Region
(see Note 2)
Inactive Boot
Alias Region
(see Note 2)
Boot Sequence Number 0x1FC43FF0 0x1FC63FF0 0x1FC03FF0 0x1FC23FF0
Code Protection 0x1FC43FD0 0x1FC63FD0 0x1FC03FD0 0x1FC23FD0
DEVCFG0 0x1FC43FCC 0x1FC63FCC 0x1FC03FCC 0x1FC23FCC
DEVCFG1 0x1FC43FC8 0x1FC63FC80x1FC03FC80x1FC23FC8
DEVCFG2 0x1FC43FC4 0x1FC63FC40x1FC03FC40x1FC23FC4
DEVCFG3 0x1FC43FC0 0x1FC63FC00x1FC03FC00x1FC23FC0
Note 1: If the device has ECC memory, each of the following Configuration Word Groups should be programmed
using the QUAD_WORD_PROGRAM comm and:
• Boot Sequence Number (single quad word programming operation)
• Code Protection (single quad word programming operation)
• DEVCFG3, DEVCFG2, DEVCFG1, and DEVCFG0 (single quad word programming operation)
2: Active/Inactive boot alias selections are assumed for an unprogrammed device where Fixed Region 1 is
active and Fixed Region 2 is inactive. Refer to the Sect ion 48. “Mem ory Organization and Permis-
sions” (DS60001214) for a detailed description of the alias boot regions.
2007-2018 Microchip Technology Inc. DS60001145W-page 59
PIC32
TABLE 19-5: CONFIGURATION WORD LOCATIONS FOR PIC32MKXXXXXXH/G/J/K/L/MXX
FAMILY DEVICES
Configuration Word
(see Note 1)
Registe r Physical Address
Fixed Boot
Region 1
Fixed Boot
Region 2 Active Boot
Alias Region
(see Notes 2, 3)
Inactive Boot
Alias Region
(see Notes 2, 3)
Boot Sequence Number 0x1FC43FF0 0x1FC63FF0 0x1FC03FF0 0x1FC23FF0
Code Protection 0x1FC43FD0 0x1FC63FD0 0x1FC03FD0 0x1FC23FD0
DEVCFG0 0x1FC43FCC 0x1FC63FCC 0x1FC03FCC 0x1FC23FCC
DEVCFG1 0x1FC43FC8 0x1FC63FC8 0x1FC03FC8 0x1FC23FC8
DEVCFG2 0x1FC43FC4 0x1FC63FC4 0x1FC03FC4 0x1FC23FC4
DEVCFG3 0x1FC43FC0 0x1FC63FC0 0x1FC03FC0 0x1FC23FC0
DEVCFG4 0x1FC43FBC
Alternate Boot Sequence Number 0x1FC43F70 0x1FC63F70 0x1FC03F70 0x1FC23F70
Alternate Code Protection 0x1FC43F50 0x1FC63F50 0x1FC03F50 0x1FC23F50
Alternate DEVCFG0 0x1FC43F4C 0x1FC63F4C 0x1FC03F4C 0x1FC23F4C
Alternate DEVCFG1 0x1FC43F48 0x1FC63F48 0x1FC03F48 0x1FC23F48
Alternate DEVCFG2 0x1FC43F44 0x1FC63F44 0x1FC03F44 0x1FC23F44
Alternate DEVCFG3 0x1FC43F40 0x1FC63F40 0x1FC03F40 0x1FC23F40
Alternate DEVCFG4 0x1FC43F3 C 0x1FC63F3C 0x1FC03F3C 0x1FC23F3C
Note 1: If the device has ECC memory, each of the following Configuration Word Groups should be programmed
using the QUAD_WORD_PROGRAM comm and:
• Boot Sequence Number (single quad word programming operation)
• Code Protection (single quad word programming operation)
• DEVCFG3, DEVCFG2, DEVCFG1, and DEVCFG0 (single quad word programming operation)
2: All values in the 0x1FCxFF00-0x1FCxFFFF memory regions should be programmed using the
QUAD_WORD_PROGRAM command to ensure proper ECC configuration. Refer to the Section 17.2.16
“QUAD_WORD_PROG RAM Command” for details.
3: Active o r Inactiv e boot ali as selec tions are assume d for an un programme d device where Fixe d Regio n 1 is
active and Fixed Region 2 is inactive. Refer to the Sect ion 48. “Mem ory Organization and Permis-
sions” (DS60001214) for a detailed description of the alias boot regions.
PIC32
DS60001145W-page 60 2007-2018 Microchip Technology Inc.
19.1.1 CONFIGURATION REGISTER
PROTECTION
To prevent inadvertent Configuration bit changes
during c ode executio n, all program mable Configur ation
bits are write-once. After a bit is initially programmed
during a power cycle, it cannot be written to again.
Chang ing a de vice conf igurat ion req uires c hangi ng the
Configuration data in the Boot Flash memory, and
cycling power to the device.
To ensure integrity of the 128-bit data, a comparison is
made between each Configuration bit and its stored
complement continuously. If a mismatch is detected, a
Configuration Mismatch Reset is generated, which
causes a device Reset.
19.2 Devi ce Cod e Protec tion bi t (C P)
The PIC32 family of devices feature code protec-
tion, which when enabled, prevents reading of the
Flash memory by an external programming device.
Once code protection is enabled, it can only be dis-
abled by erasing the device with the Chip Erase
comma nd (MCHP_ERASE).
When programming a device that has opted to uti-
lize code protection, the programming device must
perform verification prior to enabling code protec-
tion. Enabling code protection should be the last step
of the programming process. Location of the code
protection enable bits vary by device. Refer to the
“Special Features” chapter in the specific device
data sheet for deta ils .
19.3 Program Write Protection bits (PWP)
The PIC32 families of devices include write protection
features, which prevent designated boot and program
Flash regions from being erased or written during
program execution.
In PIC3 2MX devices , write prot ection is i mplemented i n
Configuration memory by the Device Configuration
Words, while in PIC32MZ and PIC32MK family
devices, this feature is implemented through SFRs in
the Flash controller.
When write protection is implemented by Device
Configuration Words, the write protection register
should only be wri tten when all b oot and pro gram Flash
memory has been programmed. Refer to the “Special
Features” chapter in th e s pe ci fic d ev ice data shee t f or
details.
If write protection is implemented using SFRs, certain
steps m ay be requ ired during initiali zation of the devic e
by the external programmer prior to programming
Flash regi ons. Refe r to the “ Flash Progra m Memory”
chapter in the specific device data sheet for details.
Note: Once code protection is enabled, the
Flash memory can no longer be read and
can only be disabled by an external
programmer using the Chip Erase
Command (MCHP_ERASE).
2007-2018 Microchip Technology Inc. DS60001145W-page 61
PIC32
20.0 TAP CONTROLLERS
TABLE 20-1: MCHP TAP INSTRUCTIONS
20.1 Microchip TAP Controllers (MTAP)
20.1.1 MTAP_COMMAND INSTR UCTION
MTAP_COMMAND selects the MCHP Command Shift
register. See Table 20-2 for available commands.
20.1.1.1 MCHP_STATUS INSTRUCTION
MCHP_STATUS returns the 8-bit Status value of the
Microchip TAP controller. Table 20-3 provides the
format of the Status value returned.
20.1.1.2 MCHP_ASSERT_RST INSTRU CTION
MCHP_ASSERT_RST performs a persistent device
Reset. It is similar to asserting and holding the MCLR
pin. Its associated Status bit is DEVRST.
20.1.1.3 MCHP_DE_ASSERT_RST
INSTRUCTION
MCHP_DE_ASSERT_RST removes the persistent
device Reset. It is similar to dea sserting the MCLR pin.
Its associated Status bit is DEVRST.
20.1.1.4 MCHP_ERASE INSTRUCTION
MCHP_ERASE performs a Chip Erase. The CHIP_
ERASE command sets an internal bit that requests
the Flash Controller to perform the erase. Once the
controller becomes busy, as indicated by FCBUSY
(Status bit), the internal bit is cleared.
20.1.1.5 MCHP_FLASH_ENABLE
INSTRUCTION
MCHP_FLASH_ENABLE sets the FAEN bit, which con-
trols processor accesses to the Flash memory. The
FAEN bit’s state is returned in the field of the same
name. This command has no effect if CPS = 0. This
command requires a NOP to complete.
20.1.1.6 MCHP_FLASH_DISABLE
INSTRUCTION
MCHP_FLASH_DISABLE clears the FAEN bit which
controls proce ssor acce sses to the Fl ash me mo ry. The
FAEN bit’s state is returned in the field of the same
name. This command has no effect if CPS = 0. This
comma nd requ ires a NOP to complete.
20.1.2 MTAP_SW_MTAP INSTRUCTION
MTAP_SW_MTAP sw itches the TAP inst ruction s et to the
MCHP TAP instruction set.
Each of these commands should be followed with a
SetMode ( 6'b011111) to force the Chip T AP controller
to the Run Test/Idle state.
20.1.3 MTAP_SW_ETAP INSTRUCTION
MTAP_SW_ETAP effectively switches the TAP
inst ruction set to the EJT A G TAP in struction set. It does
this by holding the EJTAG TAP controller in the Run
Test/Idle state until a MTAP_SW_ETAP instruction is
decoded by the MCHP TAP controller.
Each of these commands should be followed with a
SetMode ( 6'b011111) to force the Chip T AP controller
to the Run Test/Idle state.
20.1.4 MTAP_IDCODE INSTRUCTION
MTAP_IDCODE returns the value stored in the DEVID
register.
Command Value Description
MTAP_COMMAND 5’h0x07 TDI and TDO connected to MCHP Command Shift register (See Table 20-2)
MTAP_SW_MTAP 5’h0x04 Switch TAP controller to MCHP TAP controller
MTAP_SW_ETAP 5’h0x05 Switch TAP controller to EJTAG TAP controller
MTAP_IDCODE 5’h0x01 Select Chip Identification Data register
Note: This command is not required for
PIC32MZ and PIC32MK family devices.
Note: This command is not required for
PIC32MZ and PIC32MK family devices.
PIC32
DS60001145W-page 62 2007-2018 Microchip Technology Inc.
TABLE 20-2: MTAP_COMMAND DR COMMANDS
TABLE 20-3: MCHP STATUS VALUE
TABLE 20-4: EJTAG TAP INSTRUCTIONS
Command Value Description
MCHP_STATUS 8’h0x00 NOP and return Status.
MCHP_ASSERT_RST 8’h0xD1 Requests the Reset controller to assert device Reset.
MCHP_DE_ASSERT_RST 8’h0xD0 Removes the request for device Reset, which causes the reset
controller to deassert device Reset if there is no other source
requesting Reset (i.e., MCLR).
MCHP_ERASE 8’h0xFC Cause the Flash controller to perform a Chip Erase.
MCHP_FLASH_ENABLE
(1)
8’h0xFE Enables fetches and loads to the Flash (from the processor).
MCHP_FLASH_DISABLE
(1)
8’h0xFD Disables fetches and loads to the Flash (from the processor).
Note 1: This command is not required for PIC32MK and PIC32MZ family of devices.
Bit
Range Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
7:0 CPS 0 NVMERR
(1)
0 CFGRDY FCBUSY FAEN
(2)
DEVRST
bit 7 CPS: Code-Protect State bit
1 = Device is not code-protected
0 = Device is code-protected
bit 6 Unimplemented: Read as ‘0’
bit 5 NVMERR: NVMCON Status bit
(1)
1 = An Error occurred during NVM operation
0 = An Error did not occur during NVM operation
bit 4 Unimplemented: Read as ‘0’
bit 3 CFGRDY: Code-Protect State bit
1 = Configuration has been read and CP is valid
0 = Configuration has not been read
bit 2 FCBUSY: Flash Controller Busy bit
1 = Flash controller is busy (Erase is in progress)
0 = Flash control ler is not busy (ei ther erase has no t started or it has finished)
bit 1 FAEN: Fla sh Access Enable bit
(2)
This bit reflects the state of CFGCON.FAEN.
1 = Flash access is enabled
0 = Flash access is disab led (i.e., processor accesses are block ed)
bit 0 DEVRST: Device Reset State bit
1 = Device Reset is active
0 = Device Reset is not active
Note 1: This bit is not implemented in PIC32MX320/340/360/420/440/460 devices.
2: This bit is not implemented in PIC32MK and PIC32MZ family devices.
Command Value Description
ETAP_ADDRESS 5’h0x08 Select Add ress register.
ETAP_DATA 5’h0x09 Select Data register.
ETAP_CONTROL 5’h0x0A Select EJTAG Control register.
ETAP_EJTAGBOOT 5’h0x0C Set EjtagBrk, ProbEn and ProbTrap to ‘1’ as the Reset value.
ETAP_FASTDATA 5’h0x0E Selects the Data and Fastdata registers.
2007-2018 Microchip Technology Inc. DS60001145W-page 63
PIC32
20.2 EJTAG TAP Controller
20.2.1 ETAP_ADDRESS COMMAND
ETAP_ADDRESS selects the Address register. The
read-only Address register provides the address for a
processor access. The value read in the register is
valid if a processor access is pending, otherwise the
value is un defined.
The two or three Least Significant Bytes (LSBs) of the
register are used with the Psz field from the EJTAG
Control register to indica te the si ze and da ta positi on of
the pending processor access transfer. These bits are
not taken directly from the address referenced by the
load/store.
20.2.2 ETAP_DATA COMMAND
ETAP_DATA selects the Data register. The read/write
Data register is used for op code and data transfers
during pro cess or access es. The v alue rea d in the Da ta
register is valid onl y if a proc es so r acc es s fo r a write is
pending , in which case t he Data register holds the store
value. The value written to the Data register is only
used if a processor access for a pending read is
finished afterwards; in which case, the data value
written is the value for the fetch or load. This behavior
impl ies th at th e Dat a regi ster is not a me mory lo cat ion
where a previously written value can be read
afterwards.
20.2.3 ETAP_CONTROL COMMAND
ETAP_CONTROL selects the Control register. The
EJTAG Control register (ECR) handles processor R eset
and soft Reset indication, Debug mode indication,
access start, finish and size, and read/write indication.
The ECR also provides the following features :
• Controls debug vector location and indication of
serviced processor accesses
• Allows a debug interrupt request
• Indicates a processo r low-power mode
• Allows implementation-dependent processor and
peripheral Resets
20.2.3.1 EJTAG Control Register (ECR)
The EJTAG Control register (see Register 20-1) is not
updated/written in the Update-DR state unless the
Rese t occurr ed; that is R
OCC
(bit 31) is either already
‘0’ or is written to ‘0’ at the same time. This condition
ensures pro per handling of p r oc essor accesse s afte r a
Reset.
Reset of the processor can be indicated through the
R
OCC
bit in the TCK domain a number of TCK cycles
after it is removed in the processor clock domain in
order to allow for proper synchronization between the
two clock domains.
Bits that are Read/Write (R/W) in the register return
their written value on a subsequent read, unless other
behavior is defined.
Internal sy nc hro niz ati on ensures that a writte n va lue is
updated for reading immediately afterwards, even
when the TAP controller takes the shortest path from
the Update-DR to Capture-DR state.
PIC32
DS60001145W-page 64 2007-2018 Microchip Technology Inc.
REGISTER 20-1: ECR: EJTAG CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R-0 R-0 U-0 U-0 U-0 U-0 U-0
Rocc Psz<1:0> — — — — —
23:16
R-0 R-0 R-0 R/W-0 R-0 R/W-0 U-0 R/W-0
VPED Doze Halt PerRst PrnW PrACC —PrRst
15:8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0
ProbEn ProbTrap —EjtagBrk— — — —
7:0
U-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0
— — — — DM — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 See Note 1
bit 28-24 Unimplemented: Read as ‘0’
bit 23-19 See Note 1
bit 18 PrACC: Pending Processor Access and Control bit
This bit indic ates a pe nding pro cess or access an d control s finis hing of a pen ding proc esso r acces s. A write
of ‘0’ fini shes proces sor access if pen ding. A write o f ‘1’ is ignore d. A successfu l F ASTDAT A acce ss will cle ar
this bit.
1 = Pending processor access
0 = No pending preprocessor access
bit 17 Unimplemented: Read as ‘0’
bit 16 See Note 1
bit 15 ProbEn: Processor Access Service Control bit
This bit co ntrols w here th e probe h andles acce sses to the DMSEG se gment through s ervic ing of pro cessor
accesses.
1 = Probe services processor accesses
0 = Probe does not service processor access
bit 14 ProbTrap: Debug Exception Vector Control Location bit
This bit controls the location of the debug exception vector.
1 = 0xFF200200
0 = 0xBFC00480
bit 13 Unimplemented: Read as ‘0’
bit 12 EjtagBrk: Debug Interrupt Exception Request bit
This bit req ues ts a deb ug inte rrup t ex cep t io n to the p roc es sor when this bit is w ri tten as ‘1’. A write of ‘ 0’ is
ignored.
1 = A debug interrupt exception request is pending
0 = A debug interrupt exception request is not pending
bit 11-4 Unimplemented: Read as ‘0’
bit 3 See Note 1
bit 2-0 Unimplemented: Read as ‘0’
Note 1: For descriptions of these bits, please refer to the Imagination Technologies Limited web site.
(www.imgtec.com).
2007-2018 Microchip Technology Inc. DS60001145W-page 65
PIC32
20.2.4 ETAP_EJTAGBOOT COMMAND
The ETAP_EJTAGBOOT command causes the
processor to fetch code from the debug exception
vector after a Reset. This allows the programmer to
send instructions to the processor to execute, instead
of the processor fetching them from the normal Reset
vector. The Reset v alue of th e EjtagBrk , ProbTrap, and
ProbE bits follows the setting of the internal
EJTAGBOOT indication.
If the EJTAGBOOT instruction has been given, and the
internal EJTAGBOOT indication is active, then the
Rese t value of th e three bi ts is set (‘ 1’), otherwise the
Reset value is clear (‘0’).
The results of setting these bits are:
• Setting the EjtagBrk causes a Debug interru pt
exception to be requested right after the
process or R ese t from the EJTAGBOOT instruction
• The debug handler is executed from the EJTAG
memory because ProbTrap is set to indicate
debug vector in EJTAG memory at 0xFF200200
• Service of the processor access is indicated
because ProbEn is set
With this configuration in place, an interrupt exception
will occur and the processor will fetch the handler from
the DMSEG at 0xFF200200. Since ProbEn is set, the
processor will wait for the instruction to be provided by
the probe.
20.2.5 ETAP_FASTDATA COMMAND
The ETAP_FASTDATA command provides a
mechanism for quickly transferring data between the
processor and the probe. The width of the Fastdata
register is one bit. During a fast data access, the
Fastdata register is written and read (i.e ., a bit is sh ifted
in and a bit is shifted out). During a fast data access,
the Fastdata regis ter v al ue s hi fted in specifie s w h eth er
the fast data access should be completed or not. The
value s hifted out is a flag that i ndicates whet her the fast
data access was successful or not (if completion was
requeste d). The FASTDAT A access is us ed for ef ficient
block transfers between the DMSEG segment (on the
probe) and target memory (on the processor). An
“upload” is defined as a sequence that the processor
loads from target memory and stores to the DMSEG
segment. A “download” is a sequence of processor
loads from the DMSEG segment and stores to target
memory. The “Fastdata area” specifies the legal range
of DMSEG segment addresses (0xFF200000 to
0xFF20000F) that can be used for uploads and
downloads. The Data and Fastdata registers (selected
with the FASTDATA instruction) allow efficient
completion of pending Fastdata area accesses.
During Fastdata uploads and downloads, the
processor will stall on accesses to the Fastdata area.
The PrAcc (processor access pending bit) will be ‘1’
indica ting the pro be is require d to complete the access .
Both upload and downlo ad ac ce ss es are atte mp ted by
shifting in a zero SPrAcc value (to request access
completion) and shifting out SPrAcc to see if the
attempt will be successful (i.e., there was an access
pending and a legal Fa stdata area add res s w a s u sed ).
Downloads will also shift in the data to be used to
satisfy the load from the DMSEG segment Fastdata
area, while uploads will shift out the data being stored
to the DMSEG segment Fastdata area.
As indicated, the following two conditions must be true
for the Fastdata access to succeed:
•PrAcc must be ‘1’ (i.e., there must be a pending
proce ssor acc es s)
• The Fastdata operation must use a valid Fastdata
area address in the DMSEG segment
(0xFF200000 to 0xFF20000F)
PIC32
DS60001145W-page 66 2007-2018 Microchip Technology Inc.
21.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
TABLE 21-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: 0ºC to +70ºC. Programming at +25ºC is recommended.
Param.
No. Symbol Characteristic Min. Max. Units Conditions
D111 V
DD
IO
Supply Voltage During Programming — — V See Note 1
D112a V
DD
CORE
Core Power Supply Voltage During Prog ramming — — V See Not e 1
D112b V
DDR
1
V
8
DDR SDRAM Supply Voltage During Programming — — V See Not e 1
D113 I
DDP
Supply Current During Programming — — mA See Note 1
D114 I
PEAK
Instantaneous Peak Current During Start-up — — mA See Note 1
D115a I
DD
CORE
Core Power Supply Current During Programming — — mA See Note 1
D115b I
DDR
1
V
8
P
DDR SDRAM Supply Current During Programming — — mA See Note 1
D116 V
DDVBAT
V
BAT
Supply Voltage During Programming — — V See Note 1
D117 I
DDVBAT
V
BAT
Supply Current During Programming — — mA See Note 1
D031 V
IL
Input Low Voltage — — V See Note 1
D041 V
IH
Input High Voltage — — V See Note 1
D080 V
OL
Output Low Voltage — — V See Note 1
D090 V
OH
Output High Voltage — — V See Note 1
D012 C
IO
Capacitive Loadi ng on I/O pin (PGEDx) — — pF See Note 1
D013 C
F
Filter Capacitor Value on V
CAP
——FSee Note 1
P1 T
PGC
Serial Clock (PGECx) Period 100 — n s —
P1A T
PGCL
Serial Clock (PGECx) Low Ti me 40 — ns —
P1B T
PGCH
Serial Clock (PGECx) High Time 40 — ns —
P6 T
SET
2
V
DD
Setup Time to MCLR 100 — ns —
P7 T
HLD
2
Input Data Hold Time from M C L R 500 — ns —
P9a T
DLY
4
PE Command Processing Time 40 — s—
P9b T
DLY
5
Delay between PGEDx by the PE to PGEDx
Released by the PE 15 — s—
P11 T
DLY
7
Chip Erase Time — — ms See Note 1
P12 T
DLY
8
Page Erase Time — — ms See Note 1
P13 T
DLY
9
Row Programming Time ——msSee Note 1
P14 T
R
MCLR Rise Time to Enter ICSP™ mode — 1.0 s—
P15 T
VALID
Data Out Valid from PGECx 10 — ns —
P16 T
DLY
8
Delay between Last PGECx and MCLR 0—s —
P17 T
HLD
3
MCLR to V
DD
—100ns —
P18 T
KEY
1
Delay from First MCLR to First PGECx for Key
Sequence on PGEDx 40 — ns —
P19 T
KEY
2
Delay from Last PGE Cx for Key Sequence on
PGEDx to Second MCLR 40 — ns —
P20 T
MCLRH
MCLR High Time — 500 µs —
Note 1: Refer to the “Electrical Characteristics” chapter in the specific device data sheet for the Minimum and
Maximum values for this paramet er.
2007-2018 Microchip Technology Inc. DS60001145W-page 67
PIC32
APPENDIX A: PIC32 FLASH
MEMORY MAP
FIGURE A-1: FLASH MEMORY MAP
APPENDIX B: HEX FILE FORMAT
Flash p rogra mmers p roces s the sta ndard h exade cima l
(hex) format used by the Microchip developm ent tools.
The format supported is the Intel
®
HEX32 Format
(INHX32). Refer to the Section 1.75 “Hex file
Formats” in the “MPASM™ Assembler, MPLINK™
Objec t Li nk er, MPLIB™ O bj ect Li brari an U se r’s Guide”
(DS3301 4) for more informa tion about hex file formats .
The basic format of the hex file is:
:BBAAAATTHHHH...HHHHCC
Each data record begins with a 9-character prefix and
always ends with a 2-character checksum. All records
begin with ‘:’, regardless of the format. The individual
elements are described below.
•BB – is a two-digit hexadecimal byte count
representing the number of data bytes that appear
on the line. Divide this number by two to get the
number of words per line.
•AAAA – is a four-digit hexadecimal address
representing the starting address of the data
record. Format is high byte first followed by low
byte.
•TT – is a two-digit record type that will be ‘00’ for
data records, ‘01’ for end-of-file records and ‘04’
for extended-address record.
•HHHH – is a four-digit hexadecimal data word.
Format is low byte followed by high byte. There
will be BB/2 data words following TT.
•CC – is a two-digit hexadecimal checksum that is
the 2’s complement of the sum of all the
prece di ng byt es in the lin e reco rd.
Because the Intel hex file format is byte-oriented, and
the 16-bit program counter is not, program memory
sections require special treatment. Each 24-bit
program word is extended to 32 bits by inserting a so-
called “phantom byte”. Each program memory
address is multiplied by 2 to yield a byte address.
As an example, a section that is located at 0x100 in
program memory will be represented in the hex file as
0x200.
The hex file will be produced with the following
contents:
:020000040000fa
:040200003322110096
:00000001FF
The data record (second line) has a load address of
0200, while the source code specified address is
0x100. The data is represented in “little-endian”
format, that is the Least Significant Byte appears first
and the phantom byte appears last, before the
checksum.
Boot Page 0
Boot Page 1
Boot Page 2
Debug Page
Configuration Words
(4 x 32 bits)
0x1F000000
0x1F001FFF
0x1F002FF0
0x1F002FFF
0x1D000000
Program Flash Memory
0x1D007FFF
PFM
BFM
Note: The memory map shown is for reference
only. Refer to the “Memory Organization”
chapter in the specific device data sheet for
the memory map for your device.
PIC32
DS60001145W-page 68 2007-2018 Microchip Technology Inc.
APPENDIX C: DEVICE IDS
TABLE C-1: PIC32MX320/340/360/440/460
FAMILY DEVICE IDS
Part Number Device ID (S ee Note 1)
PIC32MX360F512L 0x0938053
PIC32MX360F256L 0x0934053
PIC32MX340F128L 0x092D053
PIC32MX320F128L 0x092A053
PIC32MX340F512H 0x0916053
PIC32MX340F256H 0x0912053
PIC32MX340F128H 0x090D053
PIC32MX320F128H 0x090A053
PIC32MX320F064H 0x0906053
PIC32MX320F032H 0x0902053
PIC32MX460F512L 0x0978053
PIC32MX460F256L 0x0974053
PIC32MX440F128L 0x096D053
PIC32MX440F256H 0x0952053
PIC32MX440F512H 0x0956053
PIC32MX440F128H 0x094D053
PIC32MX420F032H 0x0942053
TABLE C-2: PIC32MX575/675/695/775/795
FAMILY DEVICE IDS
Part Number Devi ce ID (See Note 1)
PIC32MX575F256H 0x04317053
PIC32MX675F256H 0x0430B053
PIC32MX775F256H 0x04303053
PIC32MX575F512H 0x04309053
PIC32MX675F512H 0x0430C053
PIC32MX695F512H 0x04325053
PIC32MX775F512H 0x0430D053
PIC32MX795F512H 0x0430E053
PIC32MX575F256L 0x04333053
PIC32MX675F256L 0x04305053
PIC32MX775F256L 0x04312053
PIC32MX575F512L 0x0430F053
PIC32MX675F512L 0x04311053
PIC32MX695F512L 0x04341053
PIC32MX775F512L 0x04307053
PIC32MX795F512L 0x04307053
TABLE C-3: PIC32MX534/564/664/764
FAMILY DEVIC E IDS
Part Number Device ID (See Note 1)
PIC32MX534F064H 0x04400053
PIC32MX564F064H 0x04401053
PIC32MX564F128H 0x04403053
PIC32MX664F064H 0x04405053
PIC32MX664F128H 0x04407053
PIC32MX764F128H 0x0440B053
PIC32MX534F064L 0x0440C053
PIC32MX564F064L 0x0440D053
PIC32MX564F128L 0x0440F053
PIC32MX664F064L 0x04411053
PIC32MX664F128L 0x04413053
PIC32MX764F128L 0x04417053
TABLE C-4: PIC32MX1XX/2XX 28/36/44-
PIN FAMILY DEVICE IDS
Part Number Device ID (See Note 1)
PIC32MX110F016B 0x04A07053
PIC32MX110F016C 0x04A09053
PIC32MX110F016D 0x04A0B053
PIC32MX210F016B 0x04A01053
PIC32MX210F016C 0x04A03053
PIC32MX210F016D 0x04A05053
PIC32MX120F032B 0x04A06053
PIC32MX120F032C 0x04A08053
PIC32MX120F032D 0x04A0A053
PIC32MX220F032B 0x04A00053
PIC32MX220F032C 0x04A02053
PIC32MX220F032D 0x04A04053
PIC32MX130F064B 0x04D07053
PIC32MX130F064C 0x04D09053
PIC32MX130F064D 0x04D0B053
PIC32MX230F064B 0x04D01053
PIC32MX230F064C 0x04D03053
PIC32MX230F064D 0x04D05053
PIC32MX150F128B 0x04D06053
PIC32MX150F128C 0x04D08053
PIC32MX150F128D 0x04D0A053
PIC32MX250F128B 0x04D00053
PIC32MX250F128C 0x04D02053
PIC32MX250F128D 0x04D04053
PIC32MX170F256B 0x06610053
PIC32MX170F256D 0x0661A053
PIC32MX270F256B 0x06600053
PIC32MX270F256D 0x0660A053
PIC32MX270F256DB 0x0660C053
PIC32MX130F256B 0x06703053
PIC32MX130F256D 0x06705053
PIC32MX230F256B 0x06700053
PIC32MX230F256D 0x06702053
2007-2018 Microchip Technology Inc. DS60001145W-page 69
PIC32
TABLE C-5: PIC32MX330/350/370/430/450/
470 FAMILY DEVICE IDS
Part Number Device ID (S ee Note 1)
PIC32MX330F064H 0x05600053
PIC32MX330F064L 0x05601053
PIC32MX350F256H 0x05704053
PIC32MX350F256L 0x05705053
PIC32MX430F064H 0x05602053
PIC32MX430F064L 0x05603053
PIC32MX450F256H 0x05706053
PIC32MX450F256L 0x05707053
PIC32MX350F128H 0x0570C053
PIC32MX350F128L 0x0570D053
PIC32MX450F128H 0x0570E053
PIC32MX450F128L 0x0570F053
PIC32MX370F512H 0x05808053
PIC32MX370F512L 0x05809053
PIC32MX470F512H 0x0580A053
PIC32MX470F512L 0x0580B053
PIC32MX450F256HB 0x05710053
PIC32MX470F512LB 0x05811053
TABLE C-6: PIC32MZ EMBEDDED
CONNECTIVITY (EC) FAM ILY
DEVICE IDS
Part Number Device ID (S ee Note 1)
PIC32MZ1024ECG064 0x05103053
PIC32MZ1024ECH064 0x05108053
PIC32MZ1024ECM064 0x05130053
PIC32MZ2048ECG064 0x05104053
PIC32MZ2048ECH064 0x05109053
PIC32MZ2048ECM064 0x05131053
PIC32MZ1024ECG100 0x0510D053
PIC32MZ1024ECH100 0x05112053
PIC32MZ1024ECM100 0x0513A053
PIC32MZ2048ECG100 0x0510E053
PIC32MZ2048ECH100 0x05113053
PIC32MZ2048ECM100 0x0513B053
PIC32MZ1024ECG124 0x05117053
PIC32MZ1024ECH124 0x0511C053
PIC32MZ1024ECM124 0x05144053
PIC32MZ2048ECG124 0x05118053
PIC32MZ2048ECH124 0x0511D053
PIC32MZ2048ECM124 0x05145053
PIC32MZ1024ECG144 0x05121053
PIC32MZ1024ECH144 0x05126053
PIC32MZ1024ECM144 0x0514E053
PIC32MZ2048ECG144 0x05122053
PIC32MZ2048ECH144 0x05127053
PIC32MZ2048ECM144 0x0514F053
TABLE C-7: PIC32MX1XX/2XX/5XX 64/100-
PIN FAMILY DEVICE IDS
Part Number Device ID (See Note 1)
PIC32MX150F256H 0x06A10053
PIC32MX150F256L 0x06A11053
PIC32MX170F512H 0x06A30053
PIC32MX170F512L 0x06A31053
PIC32MX250F256H 0x06A12053
PIC32MX250F256L 0x06A13053
PIC32MX270F512H 0x06A32053
PIC32MX270F512L 0x06A33053
PIC32MX550F256H 0x06A14053
PIC32MX550F256L 0x06A15053
PIC32MX570F512H 0x06A34053
PIC32MX570F512L 0x06A35053
PIC32MX120F064H 0x06A50053
PIC32MX130F128H 0x06A00053
PIC32MX130F128L 0x06A01053
PIC32MX230F128H 0x06A02053
PIC32MX230F128L 0x06A03053
PIC32MX530F128H 0x06A04053
PIC32MX530F128L 0x06A05053
PIC32
DS60001145W-page 70 2007-2018 Microchip Technology Inc.
TABLE C-8: PIC32MZ EMBEDDED
CONNECTIVITY WITH FPU
(EF) FAMILY DEVICE IDS
Part Number Device ID (S ee Note 1)
PIC32MZ0512EFE064 0x07201053
PIC32MZ0512EFF064 0x07206053
PIC32MZ0512EFK064 0x0722E053
PIC32MZ1024EFE064 0x07202053
PIC32MZ1024EFF064 0x07207053
PIC32MZ1024EFK064 0x0722F053
PIC32MZ1024EFG064 0x07203053
PIC32MZ1024EFH064 0x07208053
PIC32MZ1024EFM064 0x07230053
PIC32MZ2048EFG064 0x07204053
PIC32MZ2048EFH064 0x07209053
PIC32MZ2048EFM064 0x07231053
PIC32MZ0512EFE100 0x0720B053
PIC32MZ0512EFF100 0x07210053
PIC32MZ0512EFK100 0x07238053
PIC32MZ1024EFE100 0x0720C053
PIC32MZ1024EFF100 0x07211053
PIC32MZ1024EFK100 0x07239053
PIC32MZ1024EFG100 0x0720D053
PIC32MZ1024EFH100 0x07212053
PIC32MZ1024EFM100 0x0723A053
PIC32MZ2048EFG100 0x0720E053
PIC32MZ2048EFH100 0x07213053
PIC32MZ2048EFM100 0x0723B053
PIC32MZ0512EFE124 0x07215053
PIC32MZ0512EFF124 0x0721A053
PIC32MZ0512EFK124 0x07242053
PIC32MZ1024EFE124 0x07216053
PIC32MZ1024EFF124 0x0721B053
PIC32MZ1024EFK124 0x07243053
PIC32MZ1024EFG124 0x07217053
PIC32MZ1024EFH124 0x0721C053
PIC32MZ1024EFM124 0x07244053
PIC32MZ2048EFG124 0x07218053
PIC32MZ2048EFH124 0x0721D053
PIC32MZ2048EFM124 0x07245053
PIC32MZ0512EFE144 0x0721F053
PIC32MZ0512EFF144 0x07224053
PIC32MZ0512EFK144 0x0724C053
PIC32MZ1024EFE144 0x07220053
PIC32MZ1024EFF144 0x07225053
PIC32MZ1024EFK144 0x0724D053
PIC32MZ1024EFG144 0x07221053
PIC32MZ1024EFH144 0x07226053
PIC32MZ1024EFM144 0x0724E053
PIC32MZ2048EFG144 0x07222053
PIC32MZ2048EFH144 0x07227053
PIC32MZ2048EFM144 0x0724F053
TABLE C-9: PIC32MZ GRAPHICS (DA)
FAMILY DEVIC E IDS
Part Number Device ID (See Note 1)
PIC32MZ1025DAA169 0x05F0C053
PIC32MZ1025DAB169 0x05F0D053
PIC32MZ1064DAA169 0x05F0F053
PIC32MZ1064DAB169 0x05F10053
PIC32MZ2025DAA169 0x05F15053
PIC32MZ2025DAB169 0x05F16053
PIC32MZ2064DAA169 0x05F18053
PIC32MZ2064DAB169 0x05F19053
PIC32MZ1025DAG169 0x05F42053
PIC32MZ1025DAH169 0x05F43053
PIC32MZ1064DAG169 0x05F45053
PIC32MZ1064DAH169 0x05F46053
PIC32MZ2025DAG169 0x05F4B053
PIC32MZ2025DAH169 0x05F4C053
PIC32MZ2064DAG169 0x05F4E053
PIC32MZ2064DAH169 0x05F4F053
PIC32MZ1025DAA176 0x05F78053
PIC32MZ1025DAB176 0x05F79053
PIC32MZ1064DAA176 0x05F7B053
PIC32MZ1064DAB176 0x05F7C053
PIC32MZ2025DAA176 0x05F81053
PIC32MZ2025DAB176 0x05F82053
PIC32MZ2064DAA176 0x05F84053
PIC32MZ2064DAB176 0x05F85053
PIC32MZ1025DAG176 0x05FAE053
PIC32MZ1025DAH176 0x05FAF053
PIC32MZ1064DAG176 0x05FB1053
PIC32MZ1064DAH176 0x05FB2053
PIC32MZ2025DAG176 0x05FB7053
PIC32MZ2025DAH176 0x05FB8053
PIC32MZ2064DAG176 0x05FBA053
PIC32MZ2064DAH176 0x05FBB053
PIC32MZ1025DAA288 0x05F5D053
PIC32MZ1025DAB288 0x05F5E053
PIC32MZ1064DAA288 0x05F60053
PIC32MZ1064DAB288 0x05F61053
PIC32MZ2025DAA288 0x05F66053
PIC32MZ2025DAB288 0x05F67053
PIC32MZ2064DAA288 0x05F69053
PIC32MZ2064DAB288 0x05F6A053
PIC32MZ1025DAK169 0x08A0C053
PIC32MZ1025DAL169 0x08A0D053
PIC32MZ1064DAK169 0x08A0F053
PIC32MZ1064DAL169 0x08A10053
PIC32MZ2025DAK169 0x08A15053
PIC32MZ2025DAL169 0x08A16053
PIC32MZ2064DAK169 0x08A18053
2007-2018 Microchip Technology Inc. DS60001145W-page 71
PIC32
PIC32MZ2064DAL169 0x08A19053
PIC32MZ1025DAR169 0x08A42053
PIC32MZ1025DAS169 0x08A43053
PIC32MZ1064DAR169 0x08A45053
PIC32MZ1064DAS169 0x08A46053
PIC32MZ2025DAR169 0x08A4B053
PIC32MZ2025DAS169 0x08A4C053
PIC32MZ2064DAR169 0x08A4E053
PIC32MZ2064DAS169 0x08A4F053
PIC32MZ1025DAK176 0x08A78053
PIC32MZ1025DAL176 0x08A79053
PIC32MZ1064DAK176 0x08A7B053
PIC32MZ1064DAL176 0x08A7C053
PIC32MZ2025DAK176 0x08A81053
PIC32MZ2025DAL176 0x08A82053
PIC32MZ2064DAK176 0x08A84053
PIC32MZ2064DAL176 0x08A85053
PIC32MZ1025DAR176 0x08AAE053
PIC32MZ1025DAS176 0x08AAF053
PIC32MZ1064DAR176 0x08AB1053
PIC32MZ1064DAS176 0x08AB2053
PIC32MZ2025DAR176 0x08AB7053
PIC32MZ2025DAS176 0x08AB8053
PIC32MZ2064DAR176 0x08ABA053
PIC32MZ2064DAS176 0x08ABB053
TABLE C-9: PIC32MZ GRAPHICS (DA)
FAMILY DEVICE IDS
(CONTINUED) (CONTINUED)
(CONTINUED)
Part Number Device ID (S ee Note 1)
PIC32
DS60001145W-page 72 2007-2018 Microchip Technology Inc.
TABLE C-11: PIC32MK GENERAL
PURPOSE AND MOT OR
CONTROL (GP/MC) FAMILY
DEVICE IDS
TABLE C-12: PIC32MK GENERAL
PURPOSE AND MOTOR
CONTROL (GP/MC) with ECC
FLASH FAMILY DEVICE IDS
Note 1: The first 4 bits of 32-bit device ID indicates
silicon revision.
TABLE C-10: PIC32MX1XX/2XX 28/44-PIN
XLP FAMILY DEVICE IDS
Part Number Devi ce ID (See Note 1)
PIC32MX154F128B 0x07800053
PIC32MX154F128D 0x07804053
PIC32MX155F128B 0x07808053
PIC32MX155F128D 0x0780C053
PIC32MX174F256B 0x07801053
PIC32MX174F256D 0x07805053
PIC32MX175F256B 0x07809053
PIC32MX175F256D 0x0780D053
PIC32MX254F128B 0x07802053
PIC32MX254F128D 0x07806053
PIC32MX255F128B 0x0780A053
PIC32MX255F128D 0x0780E053
PIC32MX274F256B 0x07803053
PIC32MX274F256D 0x07807053
PIC32MX275F256B 0x0780B053
PIC32MX275F256D 0x0780F053
Part Number Device ID (S ee Note 1)
PIC32MK1024MCF100 0x06201053
PIC32MK1024MCF064 0x06202053
PIC32MK0512MCF100 0x06204053
PIC32MK0512MCF064 0x06205053
PIC32MK1024GPE100 0x06207053
PIC32MK1024GPE064 0x06208053
PIC32MK0512GPE100 0x0620A053
PIC32MK0512GPE064 0x0620B053
PIC32MK1024GPD100 0x0620D053
PIC32MK1024GPD064 0x0620E053
PIC32MK0512GPD100 0x06210053
PIC32MK0512GPD064 0x06211053
Part Number Device ID (See Note 1)
PIC32MK1024MCM100 0x08B01053
PIC32MK1024MCM064 0x08B02053
PIC32MK0512MCM100 0x08B04053
PIC32MK0512MCM064 0x08B05053
PIC32MK1024GPL100 0x08B07053
PIC32MK1024GPL064 0x08B08053
PIC32MK0512GPL100 0x08B0A053
PIC32MK0512GPL064 0x08B0B053
PIC32MK1024GPK100 0x08B0D053
PIC32MK1024GPK064 0x08B0E053
PIC32MK0512GPK100 0x08B10053
PIC32MK0512GPK064 0x08B11053
PIC32MK0512MCJ064 0x06300053
PIC32MK0512MCJ048 0x06301053
PIC32MK0512MCJ040 0x06302053
PIC32MK0256MCJ064 0x06304053
PIC32MK0256MCJ048 0x06305053
PIC32MK0256MCJ040 0x06306053
PIC32MK0512GPH064 0x06308053
PIC32MK0512GPH048 0x06309053
PIC32MK0512GPH040 0x0630A053
PIC32MK0256GPH064 0x0630C053
PIC32MK0256GPH048 0x0630D053
PIC32MK0256GPH040 0x0630E053
PIC32MK0512GPG064 0x06318053
PIC32MK0512GPG048 0x06319053
PIC32MK0512GPG040 0x0631A053
PIC32MK0256GPG064 0x0631C053
PIC32MK0256GPG048 0x0631D053
PIC32MK0256GPG040 0x0631E053
2007-2018 Microchip Technology Inc. DS60001145W-page 73
PIC32
APPENDIX D: REVIS ION HISTORY
Revision A (August 2007)
This is the initial released version of the document.
Revision B (February 2008)
Update records for this revision are not available.
Revision C (April 2008)
Update records for this revision are not available.
Revision D (May 2008)
Update records for this revision are not available.
Revision E (July 2009)
This version of the document includes the following
additions and updat es:
• Minor changes to style and formatting have been
incorporated throughout the document
• Added the following devices:
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX675F512H
- PIC32MX795F512H
- PIC32MX575F512L
- PIC32MX675F512L
- PIC32MX795F512L
• Updated MCLR pulse line to show active-high
(P20) in Figure 7-1
• Updated Step 7 of Table 11-1 to clarify repeat of
the last instruction in the step
• The following instructions in Table 13-1 were
updated:
- Seventh, ninth and eleventh instructions in
Step 1
- All instruc tions in Step 2
- First instru ction in Step 3
- Third instru cti on in Step 4
• Added the following devices to Table 17-1:
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX575F512L
- PIC32MX675F512H
- PIC32MX675F512L
- PIC32MX795F512H
- PIC32MX795F512L
• Updated address values in Table 17-2
Revision E (July 2009) (Continued)
• Added the following devices to Table 17-5:
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX675F512H
- PIC32MX795F512H
- PIC32MX575F512L
- PIC32MX675F512L
- PIC32MX795F512L
• Added Notes 1-3 and the following bits to the
DEVCFG - Device Configuration Word Summary
and the DEVCFG3: Device Configuration Word 3
(see Table 18-1 and Register ):
- FVBUSIO
- FUSBIDIO
- FCANIO
-FETHIO
- FMIIEN
- FPBDIV<1:0>
-FJTAGEN
• Updated the DEVID Summary (see Table 18-1)
• Updated ICESEL bit description and added the
FJTAGEN bit in DEVCFG0: Device Co nfi gura tio n
Word 0 (see Register 16-1)
• Updated DEVID: Device and Revision ID register
• Added Device IDs and Revision table (Table 18-4)
• Added MCLR High Time (parameter P20) to
Table 20-1
• Added Appendix B: “Hex File Format” and
Appendix D: “Revision History”
Revision F (April 2010)
This version of the document includes the following
additions and updates:
• The following global bit name changes were
made:
- NVMWR renamed as WR
- NVMWREN renamed as WREN
- NVMERR renamed as WRERR
- FVBUSIO renamed as FVBUSONIO
- FUPLLEN renamed as UPLLEN
- FUPLLIDIV renamed as UPLLIDIV
- POSCMD renamed as POSCMOD
• Updated the PIC32MX family data sheet
reference s in the fou rth para gra ph of Section 2.0
“Programming Overview”
• Updated the note in Section 5.2.2 “2-Phase
ICSP”
• Updated the Initia te Flash Row W r ite Op Codes and
instructions (se e steps 4, 5 and 6 in Table 13-1)
PIC32
DS60001145W-page 74 2007-2018 Microchip Technology Inc.
Revision F (April 2010) (Continued)
• Added the following devices:
- PIC32MX534F064H
- PIC32MX534F064L
- PIC32MX564F064H
- PIC32MX564F064L
- PIC32MX564F128H
- PIC32MX564F128L
- PIC32MX575F256L
- PIC32MX664F064H
- PIC32MX664F064L
- PIC32MX664F128H
- PIC32MX664F128L
- PIC32MX675F256H
- PIC32MX675F256L
- PIC32MX695F512H
- PIC32MX605F512L
- PIC32MX764F128H
- PIC32MX764F128L
- PIC32MX775F256H
- PIC32MX775F256L
- PIC32MX775F512H
- PIC32MX775F512L
Revision G (August 2010)
This revision of the document includes the following
updates:
• Up date d Step 3 in Table 11-1: Download the PE
• Minor corrections to formatting and text have
been incorporated throughout the document
Revision H (April 2011)
This version of the document includes the following
additions and updat es:
• Updates to formatting and minor typographical
changes have been incorporated throughout the
document
• The following devices were added:
- PIC32MX110F016B
- PIC32MX110F016C
- PIC32MX110F016D
- PIC32MX120F032B
- PIC32MX120F032C
- PIC32MX120F032D
- PIC32MX210F016B
- PIC32MX210F016C
- PIC32MX210F016D
- PIC32MX220F032B
- PIC32MX220F032C
- PIC32MX220F032D
• The following rows were added to Table 17-1:
-PIC32MX1X0
-PIC32MX2X0
• Added a new sub section Section 17.4.6
“Checksum Values While Device Is Code-
Protected”
• Removed Register 18-1 through Register 18-5.
• Rem oved Table 17-2
• Removed Section 17.5 “Checksum for PIC32
Devices” and its sub sections
• The Flash Program Memo ry Write- Protect
Ranges table was removed (formerly Table 18-4)
• Added DEVCFG Locations for PIC32MX1X0 and
PIC32M X20X Devi ces Only (see Table 18-3)
•In Section 18.0 “Configuration Memo ry and
Device ID”, removed Table 18-1 and updated
Table 18-2: DEVID Summary as Table 18-1
• Added the NVMERR bit to the MCHP Status
Value table (see Table 19-3)
• The following Silicon Revision and Revision ID
are added to Table 18-4:
- 0x5 - B6 Revision
- 0x1 - A1 Revi si on
• Added a note to the Flash Memory Map (see
Figure A-1)
• Added Appendix C: “Flash Program Memory
Data Sheet Clarificatio n”
Revision J (August 2011)
This revision includes the following updates:
• All occurrences of V
CORE
/V
CAP
have b een changed
to V
CAP
• Updated the fourth paragraph of Section 2.0
“Programming Overview”
• Removed the column, Programmer Pin Name, from
the 2-Wire Interface Pins table and updated the Pin
Type for MCLR (see Table 4-2)
• Added the following new devices to the Code
Memory Size table (see Table 5-1) and the Device
IDs and Revision table (see Table 18-4):
- PIC32MX130F064B
- PIC32MX130F064C
- PIC32MX130F064D
- PIC32MX150F128B
- PIC32MX150F128C
- PIC32MX150F128D
- PIC32MX230F064B
- PIC32MX230F064C
- PIC32MX230F064D
- PIC32MX250F128B
- PIC32MX250F128C
- PIC32MX250F128D
• Added Row Size and Page Size columns to the
Code Memory Size table (see Table 5-1)
Note: The revision history in this document
intentionally skips from Revision H to
Revision J to avoid confusing the
uppercase letter “I” (EY) with the
lowercase letter “l” (EL).
2007-2018 Microchip Technology Inc. DS60001145W-page 75
PIC32
Revision J (August 2011) (Continued)
• Updated the PGCx signal in Entering Enhanced
ICSP Mode (see Figure 7-1)
• Updated the Erase Device block diagram (see
Figure 9-1)
• Ad ded a ne w step 4 to the process to erase a ta rget
device in Section 9.0 “Erasing the Device”
• Updated the MCLR signal in 2-Wire Exit Test
Mode (see Figure 15-2)
• Updated the PE Command Set with the following
commands and modified Note 2 (see Table 16-2):
- PROGRAM_CLUSTER
- GET_DEVICEID
- CHANGE_CFG
• Added a second note to Section 16.2.11
“GET_CRC Command”
• Upd ated th e Address and Length desc ription s in th e
PROGRAM_CLUSTER Format (see Table 16-13)
• Added a note after th e CHANGE_CFG R esponse (se e
Figure 16-27)
• Upd ated the DEVCFG 0 and DEVCFG1 v alues for
All PIC32MX1XX an d All PIC32MX2XX d evices in
Table 17-1
• The following changes were made to the AC/DC
Characteristics and Timing Requirement s
(Table 20-1):
- Updated the Min. value for parameter D111 (V
DD
)
- Added parameter D114 (I
PEAK
)
- Removed parameters P2, P3, P4, P4A, P5, P8
and P10
• Removed Appendix C: “Flash Program Memory
Data Sheet Clarification”
• Minor updates to text and formatting were
incorporated throughout the document
Revision K (July 2012)
This revision includes the following updates:
• All occurrences of PGC and PGD were changed to:
PGEC and PGED, respectively
• Updated Section 1.0 “Devi ce Ov ervi ew” wit h a lis t
of all major topics in this document
• Added Section 2.3 “Data Sizes”
• Updated Section 4.0 “Connecting to the Device”
• Added Note 2 to Connections for the On-chip
Regulator (see Figure 4-2)
• Ad ded Note 2 to the 4-wire an d 2-wire Interface Pin s
tables (se e Table 4-1 and Table 4-2)
• Updated Section 7.0 “Entering 2-Wire Enhanced
ICSP Mode”
• Updated Entering Serial Execution Mode (see
Figure 10-1)
• Updated step 11 in Section 10.2 “2-wire Interface”
• Updated Section 12.2 “With the PE”
• Updated Step 3 in Initiate Flash Row Write Op
Codes (see Table 13-1)
• Updated Step 1 in Verify Device op Codes (see
Table 14-1)
• Updated the interval in Section 15.1 “4-wire
Interface” and Section 15.2 “2-wire Interface”
• Added a note regarding the PE location in
Section 16.0 “The Programming Executive”
• Ad ded references to the Ope rand field th roughout
Section 16.2 “The PE Command Set”
• Updated the PROGRAM Command Algori thm (see
Figure 16-9)
• Updated the mask values for All PIC32MX1XX
and PIC32MX2XX devices, and DEVCFG3 for all
devices (see Table 17-1)
• Updated the DCR value (see Section 17.4.3
“Calculating for “DCR” in the Checksum
Formula” and Table 17-2)
• Upd ate d the Check sum Cal cu lati on Pro ces s (see
Example 17-1)
• Ad ded thes e new dev ices to the Code Memory Size
table (see Table 5-1) and the Device IDs and
Revision table (see Table 18-4):
• Added a Note to Section 18.2 “Device Code
Protection bit (CP)”
• Added the EJTAG Contro l Regist er (see
Register 19-1)
• Updated Section 19.2.4 “ETAP_EJTAGBOOT
Command”
• AC/DC Characteristics and Timing Requirements
updates (see Table 20-1):
- Removed parameter D112
- Replaced Notes 1 and 2 with a new Note 1
- Updated parameters D111, D113, D114, D031,
D041, D080, D090, D012, D013, P11, P12, and
P13
• Minor updates to text and formatting were
incorporated through the document
- PIC32MX420F032H - PIC32MX450F128L
- PIC32MX330F064H - PIC32MX440F256H
- PIC32MX330F064L - PIC32MX450F256H
- PIC32MX430F064H - PIC32MX450F256L
- PIC32MX430F064L - PIC32MX460F256L
- PIC32MX340F128H - PIC32MX340F512H
- PIC32MX340F128L - PIC32MX360F512H
- PIC32MX350F128H - PIC32MX370F512H
- PIC32MX350F128L - PIC32MX370F512L
- PIC32MX350F256H - PIC32MX440F512H
- PIC32MX350F256L - PIC32MX460F512L
- PIC32MX440F128H - PIC32MX470F512H
- PIC32MX440F128L - PIC32MX470F512L
- PIC32MX450F128H
PIC32
DS60001145W-page 76 2007-2018 Microchip Technology Inc.
Revision L (January 2013)
This revision includes the following updates:
• The following sections were added or updated:
-Section 2.1 “Devices with Dual Flash
Panel and Dual Boot Regions” (new)
- Section 4.3 “Power Requirements”
- Section 13.0 “Initi ating a Fl ash Ro w W rite ”
- Section 16.1.1 “2-wire ICSP EJTAG RATE”
• Updated the Device Configuration Register Mask
Values (see Table 17-1)
• The following devices were added to the Code
Memory Size table an d the Devi ce IDs and Re vision
table (see Table 5-1 and Table 18-4):
• Note 3 and Note 4 and the GET_CHECKSUM and
QUAD_WORD_PRGM command s were added to the
PE Command Set (see Table 16-2)
• Added Section 16.2.15 “GET_CHECKSUM
Command”
• Added Section 16.2.16 “QUAD_WORD_PRO-
GRAM Command”
• Updated al l addresses in DEVCFG Locations
(see Table 18-1 and Table 18-2)
• Added Co nfiguration Word Locations for
PIC32MZ EC Family Devices (see Table 18-3)
• Updated Sectio n 18.2 “Device Code Protection
bit (CP)”
• Updated Sectio n 18.3 “Program Write Protectio n
bits (PWP)”
• All references to Test mode were updated to
programming mode throughout the document
• Minor updates to text and formatting were
incorporated through the document
Revision M (September 2013)
This revision includes the following updates:
• All references to MIPS Technologies Inc. and
www.mips.com were updated to Imagination
Technologies Limited and www.imgtec.com,
respectively
• Updated Section 2.0 “Programming Overview”
• Updated the last paragraph in Section 5.1.6
“Flash Memory”
• Updated Code Memory Sizes and added Note 3
(see Table 5-1)
• Updated the Erase Device flow diagram (see
Figure 9-1)
• Updated Steps 1, 2, 3, and 5 in Table 11-1
• Added a new paragraph in Section 13.2
“Without the PE”
• Updated Step 2, 3, and 5 in Table 13-1
• Updated the Op code description in Table 16-17
• Updated Device Configuration Mask Values (see
Table 17-1)
• Removed the first sentence in the fourth
paragraph of Section 17.3 “Algorithm”
• Updated Device IDs and Revision (see Table 18-4)
Revision N (April 2014 )
This revision includes the following updates:
• Not e 2 was upd ate d in TABLE 4-1: “4-wire
Interface Pins”
• Not e 2 was upd ate d in TABLE 4-2: “2-wire
Interface Pins”
• The D elay value in Step 5 o f Section 9.0
“Erasing the Device” was updated
• The Revision ID and Silicon Revision column
was updated and the following devices were
added to the Device IDs and Revision table (see
Table 18-4):
- PIC32MZ0256ECE064 - PIC32MZ1024ECF064
- PIC32MZ0256ECE100 - PIC32MZ1024ECF100
- PIC32MZ0256ECE124 - PIC32MZ1024ECF124
- PIC32MZ0256ECE144 - PIC32MZ1024ECF144
- PIC32MZ0256ECF064 - PIC32MZ1024ECG064
- PIC32MZ0256ECF100 - PIC32MZ1024ECG100
- PIC32MZ0256ECF124 - PIC32MZ1024ECG124
- PIC32MZ0256ECF144 - PIC32MZ1024ECG144
- PIC32MZ0512ECE064 - PIC32MZ1024ECH064
- PIC32MZ0512ECE100 - PIC32MZ1024ECH100
- PIC32MZ0512ECE124 - PIC32MZ1024ECH124
- PIC32MZ0512ECE144 - PIC32MZ1024ECH144
- PIC32MZ0512ECF064 - PIC32MZ2048ECG064
- PIC32MZ0512ECF100 - PIC32MZ2048ECG100
- PIC32MZ0512ECF124 - PIC32MZ2048ECG124
- PIC32MZ0512ECF144 - PIC32MZ2048ECG144
- PIC32MZ1024ECE064 - PIC32MZ2048ECH064
- PIC32MZ1024ECE100 - PIC32MZ2048ECH100
- PIC32MZ1024ECE124 - PIC32MZ2048ECH124
- PIC32MZ1024ECE144 - PIC32MZ2048ECH144
- PIC32MX170F256B - PIC32MX350F256H
- PIC32MX170F256D - PIC32MX350F256L
- PIC32MX270F256B - PIC32MX430F064H
- PIC32MX270F256D - PIC32MX430F064L
- PIC32MX330F064H - PIC32MX450F128H
- PIC32MX330F064L - PIC32MX450F128L
- PIC32MX350F128H - PIC32MX450F256H
- PIC32MX350F128L - PIC32MX450F256L
2007-2018 Microchip Technology Inc. DS60001145W-page 77
PIC32
Revision P (October 2014)
The following updates were implemented:
•TABLE 5-1: “Code Memory Size” was update d
to include PIC32MK device information
•TABLE 18-1: “Device Configuration Register
Mask Values of Currentl y Supported PIC32M X,
PIC32MZ, and PIC32MK Devices” was updated
to include PIC32MK device information
• The original table, Ta ble 18-4: Device IDs and
Revision was removed as this information is
readily available in the current Family Silicon
Errata
•TABLE 19-4: “Configuration Word Locations
for PIC32MK family Devices” was added
Revision Q (July 2015)
This revision includes the following updates:
•Section 14.0 “Initiating a Flash Row Write” was
added
•TABLE 18-1: “Device Configuration Register
Mask Values of Currently Supported PIC32MX,
PIC32MZ, and PIC32MK Devices” was updated to
include DEVCFG4
•EQUATION 18-1: “Checksum Formula” was
updated
•TABLE 19-3: “Configuration Word Locations for
PIC32MZ family Devices” was updated to include
DEVCFG4
• Minor updates to text and formatting were
incorporated throughout the document
Revision R (April 2016)
This revision includes the following updates:
•FIGURE 4-1: “Programming Interfaces” was
updated
•TABLE 4-1: “4-wire Interface Pins” was updated
•TABLE 4-2: “2-wire Interface Pins” was updated
•FIGURE 4-4: “PIC32MZ EC/EF Power
Connections” was updated
•FIGURE 4-5: “PIC32MZ DA Power Connections”
was updated
•TABLE 5-1: “Code Memory Size” was update d
•FIGURE 5-2: “Basic PIC32 Programming
Interface Block Diagram” was upd ated
•FIGURE 16-1: “4-wire Exit Programming Mode”
was updated
•FIGURE 16-2: “2-wire Exit Programming Mode”
was updated
• Parameters D112 (V
DD
1
V
8
) and D115 (I
DD
1
V
8
P
)
were added to TABLE 21-1: “AC/DC
Characteristics and Timin g Require ments”
•Section 4.3 “PIC32MX Power Requirements” was
updated
•Section 4.4 “PIC32MX With V
BAT
Pin Power
Requirements” was added
•Section 4.5 “PIC32MZ EC and PIC32MZ EF
Power Requirements” was added
•Section 4.6 “PIC32MZ DA Power Requirements”
was added
•Section 4.7 “PIC32MK Power Requirements”
was added
•Section 5.3.3 “Synchronization” was added
•Section 6.7 “Synchronize Pseudo Operation”
was added
•Section 8.1 “4-wire Interface” was update d
•Section 8.2 “2-wire Interface” was update d
•TABLE 13-1: “Page Erase Op Codes” was
updated
•TABLE 18-1: “Device Configuration Register
Mask Values of Currently Supported PIC3 2MX,
PIC32MZ, and PIC32MK Devices” was updated
• Not e 1 in the Checks um Formu la w as upd ate d
(see Equatio n 1 8-1)
Revision S (September 2016)
This revision includes the following updates:
• The P rogramming Interfaces diagra m was
updated (see Figure 4-1)
• The 4 -Wire Interface Pi ns tab le was u pda ted (se e
Table 4-1)
• The 2 -Wire Interface Pi ns tab le was u pda ted (se e
Table 4-2)
• The PIC32MZ DA Power Connections diagram
was updated (see Figure 4-5)
• The Basic PIC32 Progr amming Inte rface Block
Diagram was updated (see Figure 5-2)
• The Note in Section 5.3.2 “2-phase ICSP” was
updated
• The AC/DC Characte ristic s and Timing Require-
ments were updated (see Table 21-1)
• Device IDs were added (see Table C-1 through
Table C-11 in Appendix C: “Device IDs”)
Revision T (May 2017)
This revision includes the following updates:
• Updated Table 20-1, Table 4-1, Table 4-2
• Updated Figure 4-1, Figure 4-2, Figure 5-2
• Added Table C-12
• Minor updates to text and formatting were
incorporated throughout the document
Note: The revision history in this document
intentionally skips from Revision N to
Revision P to avoid confusing the
uppercase letter “O” with the number
zero “0”.
PIC32
DS60001145W-page 78 2007-2018 Microchip Technology Inc.
Revision U (July 2017)
This revision includes the following updates:
• Updated the PIC32MK devices (see Section 2.1
“Devices with Dual Flash Pan el and Dua l Boot
Regions”)
• Updated the PIC32MK devices in Code Memory
Size (see Table 5-1)
• Up date d t he PIC 32M K d ev ic es in Dev ic e C on fig u-
ration Register Mask Values of Currently Sup-
ported PIC32MX, PIC32MZ, and PIC32MK
Devices (see Table 18-1)
• Updated the Configuration Word Locations for
PIC32MK Family Devices (see Table 19-4)
• Added TABLE 19-5: “Configuration W ord Loca-
tions for PIC32MKXXXXXXH/G/J/K/L/MXX
Family Devices”
• Updated the PIC32MK General Purpose and
Motor Control (GP/MC) Family Device IDs (see
Table C-11)
• In additions, minor updates to text and formatting
were incorporated throughout the document
Revision V (July 2018)
This revision includes the following updates:
•In Table 18-1: Renamed PIC32M K025 6/
0512XXG/H to PIC32MK0256/0512XXH/G/J.
Also, updated Device Configuration Register
Mask Values for PIC32MK0512/1024XXK/L/M
and PIC32MK0512/1024XXH/G/J
•In Table 19-5: Renamed family name from
PIC32MKXXXXXXG/H/K/L/MXX to
PIC32MKXXXXXXH/G/J/K/L/MXX
•In Table C-11: Removed references to
PIC32MKXXXXMCM/GPL/ GPKXXX and
PIC32MKXXXXMCH/GPGXXX
•In Table C-12: Rearranged PIC32MKXXXX/MCM/
GPL/GPKXXX devices. Added PIC32MKXXXX-
MCJ/GPH/GPGXXX devices
• A note reference to the revision ID has been
added from Table C-1 to Table C-12, which identi-
fies the revision ID field within 32-bit device ID.
Revision W (October 2018)
This revision includes the following updates:
• Added note below Table 13-1 and Table 14-1
• Table C-13 content has been moved to Table C-9
2007-2018 Microchip Technology Inc. DS60001145W-page 79
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates . It is y o u r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microc hip name and logo, the Micr ochip log o, Any Rate, A VR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBl ox, KeeLoq, Kl eer, LANCheck, LI NK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other c ountries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Spe ed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Qui et-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacito r , AnyIn, A nyOut, BodyCom, CodeGuard,
CryptoAuthentication , Cry ptoAutomotive, CryptoComp anion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
Jitt erBloc ke r, KleerNe t, Kl ee r N et logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, Mult iT RAK, NetDetach, Omnis cient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerS mart, PureS ilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microch i p Technology Inco rporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon S torage Technol ogy is a regist ered trademark of Microchip
Technology Inc. in other countries.
GestIC i s a reg i stered trade mark of Microchip Techno logy
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countr ies.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3733 -8
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal met hods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly e volving. We at M icrochip are c omm itted t o c ontinuously impr oving t he c ode pr otection feat ures of our
products. Attempts to break Microchip’s code protection feature may be a violat ion of t he Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that A ct.
Microch ip rece iv ed ISO/T S -16 94 9:20 09 certific at ion for i ts worldw id e
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, K
EE
L
OQ
®
code hopping
devices, Serial EEPROMs, microperiph erals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949
==
DS60001145W-page 80 2017-2018 Microchip Technology Inc.
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