LTC1863L/LTC1867L
1
1863l7lfa
APPLICATIO S
U
BLOCK DIAGRA
W
FEATURES
DESCRIPTIO
U
■
Industrial Process Control
■
High Speed Data Acquisition
■
Battery Operated Systems
■
Multiplexed Data Acquisition Systems
■
Imaging Systems
■
Sample Rate: 175ksps
■
16-Bit No Missing Codes and ±3LSB Max INL
■
8-Channel Multiplexer with:
Single Ended or Differential Inputs and
Unipolar or Bipolar Conversion Modes
■
SPI/MICROWIRE
TM
Serial I/O
■
2.7V Guaranteed Supply Voltage
■
Pin Compatible with LTC1863/LTC1867
■
True Differential Inputs
■
On-Chip or External Reference
■
Low Power: 750µA at 175ksps, 300µA at 50ksps
■
Sleep Mode
■
Automatic Nap Mode Between Conversions
■
16-Pin Narrow SSOP Package
Micropower, 3V,
12-/16-Bit, 8-Channel
175ksps ADCs
The LTC
®
1863L/LTC1867L are pin compatible, 8-channel
12-/16-bit A/D converters with serial I/O and an internal
reference.
The 8-channel input multiplexer can be configured for
either single-ended or differential inputs and unipolar or
bipolar conversions (or combinations thereof). The ADCs
convert 0V to 2.5V unipolar inputs or ±1.25V bipolar
inputs. The ADCs typically draw only 750µA from a single
2.7V supply. The automatic nap and sleep modes benefit
power sensitive applications.
The LTC1867L’s DC performance is outstanding with a
±3LSB INL specification and 16-bit no missing codes over
temperature.
Housed in a compact, narrow 16-pin SSOP package, the
LTC1863L/LTC1867L can be used in space-sensitive as
well as low power applications.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
V
DD
GND
SDI
SDO
SCK
CS/CONV
V
REF
1863L7L BD
SERIAL
PORT
ANALOG
INPUT
MUX
REFCOMP
9
INTERNAL
1.25V REF
LTC1863L/LTC1867L
12-/16-BIT
175ksps
ADC
+
–
Integral Nonlinearity vs Output Code
(LTC1867L)
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
OUTPUT CODE
0
INL (LSB)
0
0.5
1.0
65536
1863L7L G01
–0.5
–1.0
–2.0 16384 32768 49152
–1.5
2.0
1.5
V
DD
= 2.7V
f
SAMPLE
= 175ksps
LTC1863L/LTC1867L
2
1863l7lfa
CO VERTER CHARACTERISTICS
U
Supply Voltage (V
DD
) ................................... –0.3V to 6V
Analog Input Voltage
CH0-CH7/COM (Note 3) .......... –0.3V to (V
DD
+ 0.3V)
V
REF
, REFCOMP (Note 4)......... –0.3V to (V
DD
+ 0.3V)
Digital Input Voltage (SDI, SCK, CS/CONV)
(Note 4) .................................................–0.3V to 10V
Digital Output Voltage (SDO) ....... –0.3V to (V
DD
+ 0.3V)
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1863LC/LTC1867LC/LTC1867LAC .... 0°C to 70°C
LTC1863LI/LTC1867LI/LTC1867LAI .. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
T
JMAX
= 110°C, θ
JA
= 95°C/W
LTC1863LCGN
LTC1863LIGN
LTC1867LCGN
LTC1867LIGN
LTC1867LACGN
LTC1867LAIGN
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Notes 1, 2)
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V, external VREF = 1.25V (Notes 5, 6)
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
VDD
GND
SDI
SDO
SCK
CS/CONV
VREF
REFCOMP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC1863L LTC1867L LTC1867LA
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution ●12 16 16 Bits
No Missing Codes ●12 15 16 Bits
Integral Linearity Error Unipolar (Note 7) ●±1±4±3 LSB
Bipolar ●±1±4±3 LSB
Differential Linearity Error ●±1 –2 –1 LSB
Transition Noise 0.1 1.6 1.6 LSB
RMS
Offset Error Unipolar (Note 8) ●±3±32 ±32 LSB
Bipolar ●±4±64 ±64 LSB
Offset Error Match Unipolar ±1±4±3 LSB
Bipolar ±1±4±3 LSB
Offset Error Drift ±0.5 ±0.5 ±0.5 ppm/°C
Gain Error Unipolar ±6±96 ±64 LSB
Bipolar ±6±96 ±64 LSB
Gain Error Match Unipolar ±1±4±3 LSB
Bipolar ±1±4±3 LSB
Gain Error Tempco Internal Reference ±20 ±20 ±20 ppm/°C
External Reference ±3±3±3 ppm/°C
Power Supply Sensitivity V
DD
= 2.7V – 3.6V ±1±3±3 LSB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade for the 1867L is identified by a label on the
shipping container.
GN PART
MARKING*
1863L
1863LI
1867L
VDD = 3V, external VREF = 1.25V (Note 5)
DY A IC ACCURACY
U
W
LTC1863L LTC1867L/LTC1867LA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 1kHz Input Signal 73.1 83.7 dB
S/(N+D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal 73 83.1 dB
LTC1863L/LTC1867L
3
1863l7lfa
A ALOG I PUT
UU
I TER AL REFERE CE CHARACTERISTICS
UU U
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
LTC1863L LTC1867L/LTC1867LA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
THD Total Harmonic Distortion 1kHz Input Signal, Up to 5th Harmonic –91.8 – 92.3 dB
Peak Harmonic or Spurious Noise 1kHz Input Signal –94.8 – 95.1 dB
Channel-to-Channel Isolation 100kHz Input Signal –100 –112 dB
Full Power Bandwidth –3dB Point 1.25 1.25 MHz
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
(Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Input Range Unipolar Mode (Note 9) ●0 to 2.5 V
Bipolar Mode ●±1.25 V
C
IN
Analog Input Capacitance for CH0 to Between Conversions (Sample Mode) 32 pF
CH7/COM During Conversions (Hold Mode) 4 pF
t
ACQ
Sample-and-Hold Acquisition Time ●2.01 1.68 µs
Input Leakage Current On Channels, CHX = 0V or V
DD
●±1µA
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
REF
Output Voltage I
OUT
= 0 1.235 1.25 1.265 V
V
REF
Output Tempco I
OUT
= 0 ±20 ppm/°C
V
REF
Line Regulation 2.7V ≤ V
DD
≤ 3.6V 0.3 mV/V
V
REF
Output Resistance ⏐I
OUT
⏐ ≤0.1mA 3 kΩ
REFCOMP Output Voltage I
OUT
= 0 2.5 V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 3.6V ●1.9 V
V
IL
Low Level Input Voltage V
DD
= 2.7V ●0.45 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
●±10 µA
C
IN
Digital Input Capacitance 2pF
V
OH
High Level Output Voltage (SDO) V
DD
= 2.7V, I
O
= –10µA 2.68 V
V
DD
= 2.7V, I
O
= –200µA●2.3 2.65 V
V
OL
Low Level Output Voltage (SDO) V
DD
= 2.7V, I
O
= 160µA 0.05 V
V
DD
= 2.7V, I
O
= 1.6mA ●0.15 0.4 V
I
SOURCE
Output Source Current SDO = 0V –9.7 mA
I
SINK
Output Sink Current SDO = V
DD
6mA
Hi-Z Output Leakage CS/CONV = High, SDO = 0V or V
DD
●±10 µA
Hi-Z Output Capacitance CS/CONV = High (Note 10) ●15 pF
Data Format Unipolar Straight Binary
Bipolar Two’s Complement
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
LTC1863L/LTC1867L/LTC1867LA
LTC1863L/LTC1867L/LTC1867LA
LTC1863L/LTC1867L/LTC1867LA
VDD = 3V, external VREF = 1.25V (Note 5)
DY A IC ACCURACY
U
W
LTC1863L/LTC1867L
4
1863l7lfa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Supply Voltage (Note 9) 2.7 3.6 V
I
DD
Supply Current f
SAMPLE
= 175ksps, Internal REF ●0.75 1 mA
NAP Mode 170 µA
SLEEP Mode ●0.2 3 µA
P
DISS
Power Dissipation f
SAMPLE
= 175ksps ●2 2.7 mW
TI I G CHARACTERISTICS
UW
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE
Maximum Sampling Frequency ●175 kHz
t
CONV
Conversion Time ●3.2 3.7 µs
t
ACQ
Acquisition Time ●2.01 1.68 µs
f
SCK
SCK Frequency 20 MHz
t
1
CS/CONV High Time Short CS/CONV Pulse Mode ●40 100 ns
t
2
SDO Valid After SCK↓C
L
= 25pF (Note 11) ●22 47 ns
t
3
SDO Valid Hold Time After SCK↓C
L
= 25pF ●517 ns
t
4
SDO Valid After CS/CONV↓C
L
= 25pF ●20 40 ns
t
5
SDI Setup Time Before SCK↑●15 –6 ns
t
6
SDI Hold Time After SCK↑●15 6 ns
t
7
SLEEP Mode Wake-Up Time C
REFCOMP
= 10µF, C
VREF
= 2.2µF80ms
t
8
Bus Relinquish Time After CS/CONV↑C
L
= 25pF ●30 50 ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND without latchup. These pins are not
clamped to V
DD
.
Note 5: V
DD
= 2.7V, f
SAMPLE
= 175ksps and f
SCK
= 20MHz at 25°C,
t
r
= t
f
= 5ns and V
IN–
= 1.25V for bipolar mode unless otherwise specified.
Note 6: Linearity, offset and gain error specifications apply for both
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001 for LTC1867L and between 0000 0000 0000 and
0000 0000 0001 for LTC1863L. Bipolar offset is the offset voltage
measured from –1/2LSB when output code flickers between 0000 0000
0000 0000 and 1111 1111 1111 1111 for LTC1867L, and between
0000 0000 0000 and 1111 1111 1111 for LTC1863L.
Note 9: Recommended operating conditions. The input range of ±1.25V
for bipolar mode is measured with respect to V
IN–
= 1.25V. For unipolar
mode, common mode input range is 0V to V
DD
for the positive input and
0V to 1.5V for the negative input. For bipolar mode, common mode input
range is 0V to V
DD
for both positive and negative inputs.
Note 10: Guaranteed by design, not subject to test.
Note 11: t
2
of 47ns maximum allows f
SCK
up to 10MHz for rising capture
with 50% duty cycle and f
SCK
up to 20MHz for falling capture (with 3ns
setup time for the receiving logic).
POWER REQUIRE E TS
WU
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863L/LTC1867L/LTC1867LA
LTC1863L/LTC1867L/LTC1867LA
LTC1863L/LTC1867L
5
1863l7lfa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
4096 Points FFT Plot
(VDD = 2.7V, Internal REF)
4096 Points FFT Plot
(VDD = 3V, REFCOMP = Ext 3V) Crosstalk vs Input Frequency
Signal-to-(Noise + Distortion)
Ratio vs Input Frequency
Power Supply Feedthrough
vs Ripple Frequency
(LTC1867L)
Supply Current vs fSAMPLE
(LTC1863L/LTC1867L)
FREQUENCY (kHz)
0
–60
–40
0
65.625
1863L7L G04
–80
–100
21.875 43.75 87.5
–120
–140
–20
AMPLITUDE (dB)
f
SAMPLE
= 175ksps
f
IN
= 1kHz
SNR = 84.7dB
SINAD = 83.5dB
THD = 90dB
fSAMPLE (ksps)
1
500
SUPPLY CURRENT (µA)
600
700
800
10 100 1000
1863L7L G09
400
300
200
100
VDD = 2.7V
ACTIVE CHANNEL INPUT FREQUENCY (kHz)
–120
RESULTING AMPLITUDE ON
SELECTED CHANNEL (dB)
–100
–90
–70
–60
0.1 10 100 1000
1863L7L G05
–140
1
–80
–110
–130
V
DD
= 3V
f
SAMPLE
= 175ksps
ADJACENT PAIR
NONADJACENT
PAIR
INPUT FREQUENCY (kHz)
1
20
AMPLITUDE (dB)
40
60
100
10 100
1863L7L G06
80
30
50
90
70
VDD = 3V
INTERNAL REF
fSAMPLE = 175ksps
SNR
SINAD
Total Harmonic Distortion
vs Input Frequency
INPUT FREQUENCY (kHz)
1
–20
AMPLITUDE (dB)
–40
–60
–100
10 100
1863L7L G06
–80
–30
–50
–90
–70
VDD = 3V
INTERNAL REF
fSAMPLE = 175ksps
THD
SFDR
RIPPLE FREQUENCY (kHz)
1
–60
POWER SUPPLY FEEDTHROUGH (dB)
–40
–20
10 100 1000
1863L7L G08
–80
–70
–50
–30
–90
–100
V
DD
= 3V
f
SAMPLE
= 175ksps
V
RIPPLE
= 10mV
P-P
OUTPUT CODE
0
INL (LSB)
0
0.5
1.0
65536
1863L7L G01
–0.5
–1.0
–2.0 16384 32768 49152
–1.5
2.0
1.5
V
DD
= 2.7V
f
SAMPLE
= 175ksps
OUTPUT CODE
0
DNL (LSB)
0
0.5
1.0
65536
1863L7L G02
–0.5
–1.0
–2.0 16384 32768 49152
–1.5
2.0
1.5
V
DD
= 2.7V
f
SAMPLE
= 175ksps
FREQUENCY (kHz)
0
–60
–40
0
65.625
1863L7L G03
–80
–100
21.875 43.75 87.5
–120
–140
–20
AMPLITUDE (dB)
f
SAMPLE
= 175ksps
f
IN
= 1kHz
SNR = 82.9dB
SINAD = 81.4dB
THD = 86.8dB
LTC1863L/LTC1867L
6
1863l7lfa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Supply Current vs Supply Voltage Supply Current vs Temperature
(LTC1863L/LTC1867L)
Differential Nonlinearity
vs Output Code (LTC1863L)
Integral Nonlinearity
vs Output Code (LTC1863L)
Histogram for 4096 Conversions
(LTC1867L)
REFCOMP vs Load Current
SUPPLY VOLTAGE (V)
2.7
600
SUPPLY CURRENT (µA)
700
800
900
1000
1200
3 3.3
1963L7L G10
3.6
1100
f
SAMPLE
= 175ksps
TEMPERATURE (°C)
–50
500
SUPPLY CURRENT (µA)
750
1000
1250
1500
–25 0 25 50
1863L7L G11
75 100
3.6V
DD
3.3V
DD
2.7V
DD
3V
DD
f
SAMPLE
= 175ksps
INTERNAL REF
CODE
20
7
0
COUNTS
200
400
600
800
1200
22 24 26 28
1863L7L G12
3021 23 25 27 29 31
1000
58
465
1044
895
830
261
23 91
170
333
VDD = 2.7V
INTERNAL REF
LOAD CURRENT (mA)
0
2.495
2.500
2.510
1.5
1863L7L G13
2.490
2.485
0.5 1 2
2.480
2.475
2.505
REFCOMP (V)
V
DD
= 2.7V
Offset Drift (LTC1867L)
vs Temperature
TEMPERATURE (°C)
–50
–10
UNIPOLAR OFFSET (LSB)
–5
0
5
10
–25 0 25 50
1863L7L G14
75 100
BIPOLAR
MODE
UNIPOLAR
MODE
V
DD
= 2.7V
f
SAMPLE
= 175ksps
EXT V
REF
= 1.25V
Gain Error Drift (LTC1867L)
vs Temperature
TEMPERATURE (°C)
–50
–15
UNIPOLAR OFFSET (LSB)
–10
–5
0
5
15
–25 02550
1863L7L G15
75 100
10
VDD = 2.7V
fSAMPLE = 175ksps
EXT VREF = 1.25V
UNIPOLAR/BIPOLAR
CODE
0
INL (LSB)
0
0.50
4096
1863L7L G16
–0.50
–1.00 1024 2048 3072
512 1536 2560 3584
1.00
–0.25
0.25
–0.75
0.75
CODE
0
DNL (LSB)
0
0.50
4096
1863L7L G17
–0.50
–1.00 1024 2048 3072
512 1536 2560 3584
1.00
–0.25
0.25
–0.75
0.75
LTC1863L/LTC1867L
7
1863l7lfa
UU
U
PI FU CTIO S
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog
inputs must be free of noise with respect to GND. CH7/
COM can be either a separate channel or the common
minus input for the other channels. Unused channels
should be tied to ground.
REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass to
GND with 10µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor (2.5V Nominal). To overdrive REFCOMP,
tie V
REF
to GND.
V
REF
(Pin 10): 1.25V Reference Output. This pin can also
be used as an external reference buffer input for improved
accuracy and drift. Bypass to GND with 2.2µF tantalum
capacitor in parallel with 0.1µF ceramic capacitor.
CS/CONV (Pin 11): This input provides the dual function
of initiating conversions on the ADC and also frames the
serial data transfer.
SCK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer.
SDO (Pin 13): Digital Data Output. The A/D conversion
result is shifted out of this output. Straight binary format
for unipolar mode and two’s complement format for
bipolar mode.
SDI (Pin 14): Digital Data Input Pin. The A/D configuration
word is shifted into this input.
GND (Pin 15): Analog and Digital GND.
V
DD
(Pin 16): Analog and Digital Power Supply. Bypass to
GND with 10µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor.
TEST CIRCUITS
UUU
TYPICAL CO ECTIO DIAGRA
U
U
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
V
DD
GND
SDI
SDO
SCK
CS/CONV
V
REF
REFCOMP
LTC1863L/
LTC1867L
–
+
+
DIGITAL
I/O
2.7V TO 3.6V
10µF
2.5V
10µF
2.2µF
1.25V
±1.25V
DIFFERENTIAL
INPUTS
2.5V
SINGLE-ENDED
INPUT
1863L7L TCD
3k
(A) Hi-Z TO VOH AND VOL TO VOH
CL
3k
2.7V
SDOSDO
(B) Hi-Z TO VOL AND VOH TO VOL
CL
1863L7L TC01
3k
(A) VOH TO Hi-Z
CL
3k
2.7V
SDOSDO
(B) VOL TO Hi-Z
CL
1863L7L TC02
Load Circuits for Access Timing Load Circuits for Output Float Delay
LTC1863L/LTC1867L
8
1863l7lfa
TI I G DIAGRA S
WUW
t5 (SDI Setup Time Before SCK↑),
t6 (SDI Hold Time After SCK↑)
50%
50%
t3
0.45V
t7 (SLEEP Mode Wake-Up Time)
t7
SCK
CS/CONV
t8 (BUS Relinquish Time)
t8
CS/CONV
SDO
1.9V
t4 (SDO Valid After CS/CONV↓)
t4
CS/CONV
SDO 1.9V
0.45V
0.45V
t6
1.9V
0.45V
t5
SCK
SDI 1.9V
1.9V
0.45V
1.9V
0.45V
SDO
1863L7L TD
SLEEP BIT (SLP = 0)
READ-IN
10%
90% Hi-Z
Hi-Z
t1
(For Short Pulse Mode) t2 (SDO Valid After SCK↓),
t3 (SDO Valid Hold Time After SCK↓)
t1
CS/CONV
t2
SCK
50%
50%
Overview
The LTC1863L/LTC1867L are complete, low power, multi-
plexed ADCs. They consist of a 12-/16-bit, 175ksps capaci-
tive successive approximation A/D converter, a precision
internal reference, a configurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, the ADCs receive an input
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
the next conversion. In the acquire phase, a minimum time
of 2.01µs will provide enough time for the sample-and-
hold capacitors to acquire the analog signal.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). The input is sucessively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low power, differential
comparator that rejects common mode noise. At the end
of a conversion, the DAC output balances the analog input.
The SAR content (a 12-/16-bit data word) that represents
the analog input is loaded into the 12-/16-bit output
latches.
APPLICATIO S I FOR ATIO
WUUU
LTC1863L/LTC1867L
9
1863l7lfa
APPLICATIO S I FOR ATIO
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Examples of Multiplexer Options
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
GND (–)
8 Single-Ended
+
+
+
+
+
+
+
4 Differential
+ (–)+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM (–)
7 Single-Ended
to CH7/COM
+
+
+
+
+
+
+
+ (–)
+ (–)
+ (–)
– (+)
– (+)
– (+)
– (+)
GND (–)
Combinations of Differential
and Single-Ended
+
+
+
+
+
+
–
–
{
{
{
{
{
{
1863L7L AI01
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
Analog Input Multiplexer
The analog input multiplexer is controlled by a 7-bit input
data word. The input data word is defined as follows:
SD OS S1 S0 COM UNI SLP
SD = SINGLE/DIFFERENTIAL BIT
OS = ODD/SIGN BIT
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
COM = CH7/COM CONFIGURATION BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
APPLICATIO S I FOR ATIO
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Tables 1 and 2 show the configurations when COM = 0,
and COM = 1.
Table 1. Channel Configuration (When COM = 0, CH7/COM Pin
Is Used as CH7)
Channel Configuration
SD OS S1 S0 COM “+” “–”
00000 CH0 CH1
00010 CH2 CH3
00100 CH4 CH5
00110 CH6 CH7
01000 CH1 CH0
01010 CH3 CH2
01100 CH5 CH4
01110 CH7 CH6
10000 CH0 GND
10010 CH2 GND
10100 CH4 GND
10110 CH6 GND
11000 CH1 GND
11010 CH3 GND
11100 CH5 GND
11110 CH7 GND
Table 2. Channel Configuration (When COM = 1, CH7/COM Pin
Is Used as COMMON)
Channel Configuration
SD OS S1 S0 COM "+" "–"
10001 CH0 CH7/COM
10011 CH2 CH7/COM
10101 CH4 CH7/COM
10111 CH6 CH7/COM
11001 CH1 CH7/COM
11011 CH3 CH7/COM
11101 CH5 CH7/COM
Changing the MUX Assignment “On the Fly”
CH7/COM
(UNUSED) CH7/COM (–)
1st Conversion 2nd Conversion
+
–
+
–
+
–
+
+
{
{
{
{
CH2
CH3
CH4
CH5
CH2
CH3
CH4
CH5
1863L7L AI02
LTC1863L/LTC1867L
10
1863l7lfa
Driving the Analog Inputs
The analog inputs of the LTC1863L/LTC1867L are easy to
drive. Each of the analog inputs can be used as a single-
ended input relative to the GND pin (CH0-GND, CH1-GND,
etc) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5,
CH6 and CH7) for differential inputs. In addition, CH7 can
act as a COM pin for both single-ended and differential
modes if the COM bit in the input word is high. Regardless
of the MUX configuration, the “+” and “–” inputs are
sampled at the same instant. Any unwanted signal that is
common mode to both inputs will be reduced by the
common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charg-
ing the sample-and-hold capacitors during the acquire
mode. In conversion mode, the analog inputs draw only a
small leakage current. If the source impedance of the
driving circuit is low then the LTC1863L/LTC1867L inputs
can be driven directly. More acquisition time should be
allowed for a higher impedance source.
The following list is a summary of the op amps that are
suitable for driving the LTC1863L/LTC1867L. More de-
tailed information is available in the Linear Technology
data books or Linear Technology website.
LT
®
1468: 90MHz, 22V/µs 16-bit accurate amplifier
LT1469: Dual LT1468
LT1490A/LT1491A: Dual/quad micropower amplifiers,
50µA/amplifier max, 500µV offset, common mode range
extends 44V above V
–
independent of V
+
, 3V, 5V and ±15V
supplies.
LT1568: Very low noise, active RC filter building block,
cutoff frequency up to 10MHz, 2.7V to ±5V supplies.
LT1638/LT1639: Dual/quad 1.2MHz, 0.4V/µs amplifiers,
230µA per amplifier, 3V, 5V and ±15V supplies.
LT1881/LT1882: Dual and quad, 200pA bias current, rail-
to-rail output op amps, up to ±15V supplies.
LTC1992-2: Gain of 2 fully differential input/output am-
plifier/driver, 2.5mV offset, C
LOAD
stable, 2.7V to ±5V
supplies.
LT1995: 30MHz, 1000V/µs gain selectable amplifier, pin
configurable as a difference amplifier, inverting and
noninverting amplifier, ±2.5V to ±15V supplies.
LTC6912: Dual programmable gain amplifiers with SPI
serial interface, 2mV offset, 2.7V to ±5V supplies.
LTC6915: Zero drift, instrumentation amplifier with SPI
programmable gain, 125dB CMRR, 0.1% gain accuracy,
10µV offset.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1863L/LTC1867L noise and distortion. Noisy in-
put circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For instance, Figure 1 shows a 50Ω
source resistor and a 2000pF capacitor to ground on the
input will limit the input bandwidth to 1.6MHz. The source
impedance has to be kept low to avoid gain error and
degradation in the AC performance. The capacitor also
acts as a charge reservoir for the input sample-and-hold
and isolates the ADC input from sampling glitch sensitive
circuitry. High quality capacitors and resistors should be
APPLICATIO S I FOR ATIO
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1863L7L F01a
CH0
GND
LTC1863L/
LTC1867L
REFCOMP
2000pF
10µF
50Ω
ANALOG
INPUT
1000pF
1863L7L F01b
CH0
CH1
LTC1863L/
LTC1867L
REFCOMP
1000pF
1000pF
10µF
50Ω
50Ω
DIFFERENTIAL
ANALOG
INPUTS
Figure 1a. Optional RC Input Filtering for Single-Ended Input Figure 1b. Optional RC Input Filtering for Differential Inputs
LTC1863L/LTC1867L
11
1863l7lfa
used since these components can add distortion. NPO and
silver mica type dielectric capacitors have excellent linear-
ity. Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resis-
tors are much less susceptible to both problems.
DC Performance
One way of measuring the transition noise associated with
a high resolution ADC is to use a technique where a DC
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conver-
sions. For example, in Figure 2 the distribution of output
codes is shown for a DC input that had been digitized 4096
times. The distribution is Gaussian and the RMS code
transition noise is about 1.6LSB.
APPLICATIO S I FOR ATIO
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Figure 2. LTC1867L Histogram for 4096 Conversions
Figure 3a. LTC1867L Nonaveraged 4096 Point
FFT Plot with 2.7V Supply
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 3a shows a typical SINAD of 81.4dB with
a 175kHz sampling rate and a 1kHz input. Higher SINAD can
be obtained with a 3V supply. For example, when an exter-
nal 3V is applied to REFCOMP (tie V
REF
to GND), a SINAD
of 83.5dB can be achieved as shown in Figure 3b.
Figure 3b. LTC1867L Nonaveraged 4096 Point
FFT Plot with 3V Supply
CODE
20
7
0
COUNTS
200
400
600
800
1200
22 24 26 28
1863L7L G12
3021 23 25 27 29 31
1000
58
465
1044
895
830
261
23 91
170
333
VDD = 2.7V
INTERNAL REF
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
FREQUENCY (kHz)
0
–60
–40
0
65.625
1863L7L G03
–80
–100
21.875 43.75 87.5
–120
–140
–20
AMPLITUDE (dB)
f
SAMPLE
= 175ksps
f
IN
= 1kHz
SNR = 82.9dB
SINAD = 81.4dB
THD = 86.8dB
FREQUENCY (kHz)
0
–60
–40
0
65.625
1863L7L F03b
–80
–100
21.875 43.75 87.5
–120
–140
–20
AMPLITUDE (dB)
f
SAMPLE
= 175ksps
f
IN
= 1kHz
SNR = 84.7dB
SINAD = 83.5dB
THD = 90dB
REFCOMP = EXT 3V
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
LTC1863L/LTC1867L
12
1863l7lfa
compensation pin, REFCOMP, must be bypassed with a
10µF ceramic or tantalum in parallel with a 0.1µF ceramic
for best noise performance.
Digital Interface
The LTC1863L and LTC1867L have a very simple digital
interface that is enabled by the control input, CS/CONV. A
logic rising edge applied to the CS/CONV input will initiate
a conversion. After the conversion, taking CS/CONV low
will enable the serial port and the ADC will present digital
data in two’s complement format in bipolar mode or
straight binary format in unipolar mode, through the SCK/
SDO serial port.
Internal Clock
The internal clock is factory trimmed to achieve a typical
conversion time of 3.2µs and a maximum conversion
time, 3.7µs, over the full operating temperature range. The
typical acquisition time is 1.68µs, and a throughput sam-
pling rate of 175ksps is tested and guaranteed.
Automatic Nap Mode
The LTC1863L and LTC1867L go into automatic nap mode
when CS/CONV is held high after the conversion is com-
plete. With a typical operating current of 750µA and auto-
matic 170µA nap mode between conversions, the power
dissipation drops with reduced sample rate. The ADC only
keeps the V
REF
and REFCOMP voltages active when the part
is in the automatic nap mode. The slower the sample rate
allows the power dissipation to be lower (see Figure 5).
R2
R3
REFERENCE
AMP
10µF
2.2µF
REFCOMP
GND
V
REF
R1
3k
10
9
15
1.25V
2.5V
LTC1863L/LTC1867L
1863L7L F04a
BANDGAP
REFERENCE
10
0.1µF10µF
1863L7L F04b
LT1790A-1.25
V
OUT
V
IN
3V
V
REF
LTC1863L/
LTC1867L
GND
REFCOMP
15
9
+
2.2µF
band between DC and half the sampling frequency. THD is
expressed as:
THD VVV V
V
N
=++ +
20 2232422
1
log ...
where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
N
are the amplitudes of the
second through Nth harmonics.
Internal Reference
T
he LTC1863L and LTC1867L have an on-chip, tempera-
ture compensated, curvature corrected, bandgap refer-
ence that is factory trimmed to 1.25V. It is internally
connected to a reference amplifier and is available at VREF
(Pin 10). A 3k resistor is in series with the output so that
it can be easily overdriven by an external reference if
better drift and/or accuracy are required as shown in
Figure 4. The reference amplifier gains the VREF voltage by
2x to 2.5V at REFCOMP (Pin 9). This reference amplifier
Figure 4b. Using the LT1790A-1.25 as an External Reference
Figure 4a. LTC1867L Reference Circuit
APPLICATIO S I FOR ATIO
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Figure 5. Supply Current vs fSAMPLE
fSAMPLE (ksps)
1
500
SUPPLY CURRENT (µA)
600
700
800
10 100 1000
1863L7L G09
400
300
200
100
VDD = 2.7V
LTC1863L/LTC1867L
13
1863l7lfa
If the CS/CONV returns low during a bit decision, it can
create a small error. For best performance ensure that the
CS/CONV returns low either within 100ns after the conver-
sion starts (i.e. before the first bit decision) or after the
conversion ends. If CS/CONV is low when the conversion
ends, the MSB bit will appear on SDO at the end of the
conversion and the ADC will remain powered up.
Sleep Mode
If the SLP = 1 is selected in the input word, the ADC will
enter SLEEP mode and draw only leakage current (pro-
vided that all the digital inputs stay at GND or V
DD
). After
release from the SLEEP mode, the ADC needs 80ms to
wake up (charge the 2.2µF/10µF bypass capacitors on
V
REF
/REFCOMP pins).
Board Layout and Bypassing
To obtain the best performance, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside an
analog signal.
All analog inputs should be screened by GND. V
REF
,
REFCOMP and V
DD
should be bypassed to this ground
plane as close to the pin as possible; the low impedance of
APPLICATIO S I FOR ATIO
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the common return for these bypass capacitors is essen-
tial to the low noise operation of the ADC. The width for
these tracks should be as wide as possible.
Timing and Control
Conversion start is controlled by the CS/CONV digital
input. The rising edge transition of the CS/CONV will start
a conversion. Once initiated, it cannot be restarted until the
conversion is complete. Figures 6 and 7 show the timing
diagrams for two types of CS/CONV pulses.
Example 1 (Figure 6) shows the LTC1863L/LTC1867L
operating in automatic nap mode with CS/CONV signal
staying HIGH after the conversion. Automatic nap mode
provides power reduction at reduced sample rate.
The ADCs can also operate with the CS/CONV signal
returning LOW before the conversion ends. In this mode
(Example 2, Figure 7), the ADCs remain powered up. The
digital output, SDO, will go HIGH immediately after the
conversion is complete if the analog inputs are above half
scale in unipolar mode or below half scale in bipolar mode.
This is a way to measure the conversion time of the A/D
converter.
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar mode.
S0SD 0S S1 COM UNI SLP
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1/f
SCK
CS/CONV
SCK
SDI
SDO
(LTC1863L)
Hi-Z
D12D15 D14 D13 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
12345678910111213141516
1867 F06
DON'T CAREDON'T CARE
NOT NEEDED FOR LTC1863L
t
CONV
NAP MODE
SDO
(LTC1867L)
MSB
MSB
Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV
Remaining HIGH after the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate
LTC1863L/LTC1867L
14
1863l7lfa
APPLICATIO S I FOR ATIO
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Figure 7. Example 2, CS/CONV Starts a Conversion with Short Active HIGH Pulse.
With CS/CONV Returning LOW Before the Conversion, the ADC Remains Powered Up.
INPUT VOLTAGE (V)
OUTPUT CODE
1863L7L F09
111...111
111...110
100...001
100...000
000...000
000...001
011...110
011...111
FS – 1LSB0V
UNIPOLAR
ZERO
FS = 2.5V
1LSB = FS/2
n
1LSB (LTC1863L) = 610µV
1LSB (LTC1867L) = 38.1µV
Figure 8. LTC1863L/LTC1867L Bipolar Transfer
Characteristics (Two’s Complement)
Figure 9. LTC1863L/LTC1867L Unipolar Transfer
Characteristics (Straight Binary)
S0SD 0S S1 COM UNI SLP
MSB = D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CS/CONV
SCK
SDI
SDO
(LTC1867L)
Hi-Z
12345678910111213141516
tCONV
D12MSB = D15 D14 D13 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
1863L7L F07
tCONV
DON'T CAREDON'T CARE
NOT NEEDED FOR LTC1863L
tACQ
SDO
(LTC1863L)
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
1863L7L F08
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 – 1LSB–FS/2
FS = 2.5V
1LSB = FS/2n
1LSB (LTC1863L) = 610µV
1LSB (LTC1867L) = 38.1µV
LTC1863L/LTC1867L
15
1863l7lfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LTC1863L/LTC1867L
16
1863l7lfa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
LT/LT 0605 REV A • PRINTED IN USA
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