LTC1863L/LTC1867L Micropower, 3V, 12-/16-Bit, 8-Channel 175ksps ADCs U FEATURES DESCRIPTIO The LTC(R)1863L/LTC1867L are pin compatible, 8-channel 12-/16-bit A/D converters with serial I/O and an internal reference. Sample Rate: 175ksps 16-Bit No Missing Codes and 3LSB Max INL 8-Channel Multiplexer with: Single Ended or Differential Inputs and Unipolar or Bipolar Conversion Modes SPI/MICROWIRETM Serial I/O 2.7V Guaranteed Supply Voltage Pin Compatible with LTC1863/LTC1867 True Differential Inputs On-Chip or External Reference Low Power: 750A at 175ksps, 300A at 50ksps Sleep Mode Automatic Nap Mode Between Conversions 16-Pin Narrow SSOP Package The 8-channel input multiplexer can be configured for either single-ended or differential inputs and unipolar or bipolar conversions (or combinations thereof). The ADCs convert 0V to 2.5V unipolar inputs or 1.25V bipolar inputs. The ADCs typically draw only 750A from a single 2.7V supply. The automatic nap and sleep modes benefit power sensitive applications. The LTC1867L's DC performance is outstanding with a 3LSB INL specification and 16-bit no missing codes over temperature. U APPLICATIO S Industrial Process Control High Speed Data Acquisition Battery Operated Systems Multiplexed Data Acquisition Systems Imaging Systems , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. W Housed in a compact, narrow 16-pin SSOP package, the LTC1863L/LTC1867L can be used in space-sensitive as well as low power applications. BLOCK DIAGRA CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM LTC1863L/LTC1867L 1 2 15 3 4 5 6 16 14 ANALOG INPUT MUX + - 12-/16-BIT 175ksps ADC SERIAL PORT 13 12 11 7 10 8 VDD 2.0 GND 1.5 SDI VDD = 2.7V fSAMPLE = 175ksps 1.0 SDO SCK CS/CONV VREF INTERNAL 1.25V REF INL (LSB) CH0 Integral Nonlinearity vs Output Code (LTC1867L) 0.5 0 -0.5 -1.0 -1.5 9 1863L7L BD REFCOMP -2.0 0 16384 32768 49152 65536 OUTPUT CODE 1863L7L G01 1863l7lfa 1 LTC1863L/LTC1867L U W U PACKAGE/ORDER I FOR ATIO W W U W ABSOLUTE AXI U RATI GS (Notes 1, 2) ORDER PART NUMBER GN PART MARKING* LTC1863LCGN LTC1863LIGN LTC1867LCGN LTC1867LIGN LTC1867LACGN LTC1867LAIGN 1863L 1863LI 1867L TOP VIEW Supply Voltage (VDD) ................................... -0.3V to 6V Analog Input Voltage CH0-CH7/COM (Note 3) .......... - 0.3V to (VDD + 0.3V) VREF, REFCOMP (Note 4)......... - 0.3V to (VDD + 0.3V) Digital Input Voltage (SDI, SCK, CS/CONV) (Note 4) .................................................- 0.3V to 10V Digital Output Voltage (SDO) ....... - 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1863LC/LTC1867LC/LTC1867LAC .... 0C to 70C LTC1863LI/LTC1867LI/LTC1867LAI .. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C CH0 1 16 VDD CH1 2 15 GND CH2 3 14 SDI CH3 4 13 SDO CH4 5 12 SCK CH5 6 11 CS/CONV CH6 7 10 VREF CH7/COM 8 9 REFCOMP GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 110C, JA = 95C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade for the 1867L is identified by a label on the shipping container. U CO VERTER CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 2.7V, external VREF = 1.25V (Notes 5, 6) PARAMETER CONDITIONS MIN LTC1863L TYP MAX MIN LTC1867L TYP MAX MIN LTC1867LA TYP MAX UNITS Resolution 12 16 16 Bits No Missing Codes 12 15 16 Bits Integral Linearity Error Unipolar (Note 7) Bipolar Differential Linearity Error 1 1 1 Transition Noise 4 4 -2 0.1 Offset Error Unipolar (Note 8) Bipolar Offset Error Match Unipolar Bipolar -1 1.6 LSB LSB LSB 1.6 LSBRMS 3 4 32 64 32 64 LSB LSB 1 1 4 4 3 3 LSB LSB 0.5 Offset Error Drift 3 3 0.5 0.5 ppm/C Gain Error Unipolar Bipolar 6 6 96 96 64 64 LSB LSB Gain Error Match Unipolar Bipolar 1 1 4 4 3 3 LSB LSB Gain Error Tempco Internal Reference External Reference 20 3 20 3 20 3 ppm/C ppm/C Power Supply Sensitivity VDD = 2.7V - 3.6V 1 3 3 LSB W U DY A IC ACCURACY SYMBOL VDD = 3V, external VREF = 1.25V (Note 5) MIN LTC1863L TYP MAX LTC1867L/LTC1867LA MIN TYP MAX PARAMETER CONDITIONS UNITS SNR Signal-to-Noise Ratio 1kHz Input Signal 73.1 83.7 dB S/(N+D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal 73 83.1 dB 1863l7lfa 2 LTC1863L/LTC1867L W U DY A IC ACCURACY THD PARAMETER CONDITIONS MIN LTC1863L TYP MAX LTC1867L/LTC1867LA MIN TYP MAX UNITS Total Harmonic Distortion 1kHz Input Signal, Up to 5th Harmonic -91.8 - 92.3 dB Peak Harmonic or Spurious Noise 1kHz Input Signal -94.8 - 95.1 dB Channel-to-Channel Isolation 100kHz Input Signal -100 -112 dB Full Power Bandwidth -3dB Point 1.25 1.25 MHz U SYMBOL VDD = 3V, external VREF = 1.25V (Note 5) U A ALOG I PUT The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX PARAMETER CONDITIONS Analog Input Range Unipolar Mode (Note 9) Bipolar Mode CIN Analog Input Capacitance for CH0 to CH7/COM Between Conversions (Sample Mode) During Conversions (Hold Mode) tACQ Sample-and-Hold Acquisition Time Input Leakage Current On Channels, CHX = 0V or VDD U U U I TER AL REFERE CE CHARACTERISTICS PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 2.01 UNITS 0 to 2.5 1.25 V V 32 4 pF pF 1.68 s 1 A (Note 5) LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX 1.235 1.25 UNITS 1.265 V VREF Output Tempco IOUT = 0 20 ppm/C VREF Line Regulation 2.7V VDD 3.6V 0.3 mV/V VREF Output Resistance IOUT 0.1mA REFCOMP Output Voltage IOUT = 0 3 k 2.5 V U U DIGITAL I PUTS A D DIGITAL OUTPUTS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 3.6V VIL Low Level Input Voltage VDD = 2.7V IIN Digital Input Current VIN = 0V to VDD CIN Digital Input Capacitance VOH High Level Output Voltage (SDO) VOL Low Level Output Voltage (SDO) VDD = 2.7V, IO = -10A VDD = 2.7V, IO = -200A VDD = 2.7V, IO = 160A VDD = 2.7V, IO = 1.6mA 1.9 2.3 UNITS V 0.45 V 10 A 2 pF 2.68 2.65 V V 0.05 0.15 0.4 V V ISOURCE Output Source Current SDO = 0V -9.7 mA ISINK Output Sink Current SDO = VDD 6 mA Hi-Z Output Leakage Hi-Z Output Capacitance CS/CONV = High, SDO = 0V or VDD CS/CONV = High (Note 10) Data Format Unipolar Bipolar 10 15 A pF Straight Binary Two's Complement 1863l7lfa 3 LTC1863L/LTC1867L U W POWER REQUIRE E TS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX SYMBOL PARAMETER CONDITIONS VDD Supply Voltage (Note 9) IDD Supply Current fSAMPLE = 175ksps, Internal REF NAP Mode SLEEP Mode PDISS Power Dissipation fSAMPLE = 175ksps 2.7 UNITS 3.6 1 V 0.75 170 0.2 3 mA A A 2 2.7 mW WU TI I G CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX SYMBOL PARAMETER CONDITIONS fSAMPLE Maximum Sampling Frequency tCONV Conversion Time tACQ Acquisition Time fSCK SCK Frequency t1 CS/CONV High Time Short CS/CONV Pulse Mode t2 SDO Valid After SCK CL = 25pF (Note 11) t3 SDO Valid Hold Time After SCK CL = 25pF t4 SDO Valid After CS/CONV CL = 25pF t5 SDI Setup Time Before SCK 15 -6 ns t6 SDI Hold Time After SCK 15 6 ns t7 SLEEP Mode Wake-Up Time CREFCOMP = 10F, CVREF = 2.2F 80 ms t8 Bus Relinquish Time After CS/CONV CL = 25pF Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA without latchup. Note 4: When these pin voltages are taken below GND, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. These pins are not clamped to VDD. Note 5: VDD = 2.7V, fSAMPLE = 175ksps and fSCK = 20MHz at 25C, t r = t f = 5ns and VIN - = 1.25V for bipolar mode unless otherwise specified. Note 6: Linearity, offset and gain error specifications apply for both unipolar and bipolar modes. The INL and DNL are tested in bipolar mode. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 175 kHz 3.2 2.01 UNITS 3.7 s 20 MHz s 1.68 40 100 5 17 22 20 30 ns 47 ns ns 40 50 ns ns Note 8: Unipolar offset is the offset voltage measured from +1/2LSB when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001 for LTC1867L and between 0000 0000 0000 and 0000 0000 0001 for LTC1863L. Bipolar offset is the offset voltage measured from -1/2LSB when output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for LTC1867L, and between 0000 0000 0000 and 1111 1111 1111 for LTC1863L. Note 9: Recommended operating conditions. The input range of 1.25V for bipolar mode is measured with respect to VIN - = 1.25V. For unipolar mode, common mode input range is 0V to VDD for the positive input and 0V to 1.5V for the negative input. For bipolar mode, common mode input range is 0V to VDD for both positive and negative inputs. Note 10: Guaranteed by design, not subject to test. Note 11: t2 of 47ns maximum allows fSCK up to 10MHz for rising capture with 50% duty cycle and fSCK up to 20MHz for falling capture (with 3ns setup time for the receiving logic). 1863l7lfa 4 LTC1863L/LTC1867L U W TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity vs Output Code 2.0 VDD = 2.7V fSAMPLE = 175ksps 0.5 0.5 DNL (LSB) 1.0 0 -0.5 -1.0 -1.0 -1.5 -1.5 0 16384 32768 -2.0 65536 49152 -140 0 32768 16384 -80 -100 -120 100 90 SNR 80 -90 -100 ADJACENT PAIR -110 -120 87.5 Total Harmonic Distortion vs Input Frequency 50 VDD = 3V 30 INTERNAL REF fSAMPLE = 175ksps 20 1 10 INPUT FREQUENCY (kHz) Supply Current vs fSAMPLE (LTC1863L/LTC1867L) 800 -20 -80 SFDR -70 THD -60 -50 -40 VDD = 3V -30 fSAMPLE = 175ksps VRIPPLE = 10mVP-P -40 -50 -60 -70 -80 1863L7L G06 600 500 400 300 200 -90 100 -100 100 VDD = 2.7V 700 SUPPLY CURRENT (A) POWER SUPPLY FEEDTHROUGH (dB) -90 100 1863L7L G06 Power Supply Feedthrough vs Ripple Frequency -100 AMPLITUDE (dB) SINAD 60 1863L7L G05 1863L7L G04 VDD = 3V -30 INTERNAL REF fSAMPLE = 175ksps -20 1 10 INPUT FREQUENCY (kHz) 70 40 NONADJACENT PAIR -140 0.1 10 100 1000 1 ACTIVE CHANNEL INPUT FREQUENCY (kHz) -140 87.5 Signal-to-(Noise + Distortion) Ratio vs Input Frequency -80 -130 65.625 FREQUENCY (kHz) 43.75 65.625 FREQUENCY (kHz) 1863L7L G03 VDD = 3V fSAMPLE = 175ksps -70 RESULTING AMPLITUDE ON SELECTED CHANNEL (dB) AMPLITUDE (dB) -60 43.75 21.875 1863L7L G02 -60 21.875 0 65536 49152 Crosstalk vs Input Frequency fSAMPLE = 175ksps fIN = 1kHz SNR = 84.7dB SINAD = 83.5dB THD = 90dB 0 -80 OUTPUT CODE 4096 Points FFT Plot (VDD = 3V, REFCOMP = Ext 3V) -40 -60 -120 1863L7L G01 -20 -40 -100 OUTPUT CODE 0 fSAMPLE = 175ksps fIN = 1kHz SNR = 82.9dB SINAD = 81.4dB THD = 86.8dB -20 0 -0.5 -2.0 0 VDD = 2.7V fSAMPLE = 175ksps 1.5 1.0 4096 Points FFT Plot (VDD = 2.7V, Internal REF) AMPLITUDE (dB) 1.5 INL (LSB) Differential Nonlinearity vs Output Code AMPLITUDE (dB) 2.0 (LTC1867L) 1 10 100 RIPPLE FREQUENCY (kHz) 1000 1863L7L G08 1 10 100 fSAMPLE (ksps) 1000 1863L7L G09 1863l7lfa 5 LTC1863L/LTC1867L U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 1200 (LTC1863L/LTC1867L) Histogram for 4096 Conversions (LTC1867L) Supply Current vs Temperature 1500 fSAMPLE = 175ksps 1200 fSAMPLE = 175ksps INTERNAL REF 1000 1000 900 800 895 1250 830 3.6VDD 800 COUNTS SUPPLY CURRENT (A) SUPPLY CURRENT (A) 1100 3.3VDD 1000 3VDD 2.7VDD 750 465 333 261 170 200 2.7 3 3.3 SUPPLY VOLTAGE (V) 500 -50 3.6 0 -25 75 0 25 50 TEMPERATURE (C) 58 23 9 2.505 2.495 2.490 2.485 15 VDD = 2.7V fSAMPLE = 175ksps EXT VREF = 1.25V UNIPOLAR MODE VDD = 2.7V fSAMPLE = 175ksps EXT VREF = 1.25V UNIPOLAR/BIPOLAR 10 5 UNIPOLAR OFFSET (LSB) 2.500 Gain Error Drift (LTC1867L) vs Temperature UNIPOLAR OFFSET (LSB) 10 VDD = 2.7V 1 20 21 22 23 24 25 26 27 28 29 30 31 CODE 1863L7L G12 Offset Drift (LTC1867L) vs Temperature REFCOMP vs Load Current 2.510 100 7 1863L7L G11 1963L7L G10 REFCOMP (V) 600 400 700 600 VDD = 2.7V INTERNAL REF 1044 BIPOLAR MODE 0 -5 5 0 -5 -10 2.480 2.475 0 0.5 1 1.5 LOAD CURRENT (mA) 2 -10 -50 -25 75 0 25 50 TEMPERATURE (C) 1863L7L G13 1.00 0.75 0.75 0.50 0.50 0.25 0.25 DNL (LSB) INL (LSB) -25 0 25 50 TEMPERATURE (C) 75 100 1863L7L G15 Differential Nonlinearity vs Output Code (LTC1863L) 1.00 0 0 -0.25 -0.25 -0.50 -0.50 -0.75 -0.75 0 -15 -50 1863L7L G14 Integral Nonlinearity vs Output Code (LTC1863L) -1.00 100 512 1024 1536 2048 2560 3072 3584 4096 CODE 1863L7L G16 -1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1863L7L G17 1863l7lfa 6 LTC1863L/LTC1867L U U U PI FU CTIO S CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog inputs must be free of noise with respect to GND. CH7/ COM can be either a separate channel or the common minus input for the other channels. Unused channels should be tied to ground. REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass to GND with 10F tantalum capacitor in parallel with 0.1F ceramic capacitor (2.5V Nominal). To overdrive REFCOMP, tie VREF to GND. VREF (Pin 10): 1.25V Reference Output. This pin can also be used as an external reference buffer input for improved accuracy and drift. Bypass to GND with 2.2F tantalum capacitor in parallel with 0.1F ceramic capacitor. SCK (Pin 12): Shift Clock. This clock synchronizes the serial data transfer. SDO (Pin 13): Digital Data Output. The A/D conversion result is shifted out of this output. Straight binary format for unipolar mode and two's complement format for bipolar mode. SDI (Pin 14): Digital Data Input Pin. The A/D configuration word is shifted into this input. GND (Pin 15): Analog and Digital GND. VDD (Pin 16): Analog and Digital Power Supply. Bypass to GND with 10F tantalum capacitor in parallel with 0.1F ceramic capacitor. CS/CONV (Pin 11): This input provides the dual function of initiating conversions on the ADC and also frames the serial data transfer. U UU ECTIO UU TYPICAL CO DIAGRA 1.25V DIFFERENTIAL INPUTS 2.5V SINGLE-ENDED INPUT + CH0 VDD - CH1 GND CH2 SDI LTC1863L/ CH3 SDO LTC1867L + CH4 SCK CH5 CS/CONV CH6 VREF CH7/COM REFCOMP 2.7V TO 3.6V 10F DIGITAL I/O 1.25V 2.2F 2.5V 10F 1863L7L TCD TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay 2.7V 2.7V 3k 3k SDO SDO SDO 3k CL (A) Hi-Z TO VOH AND VOL TO VOH SDO 3k CL (B) Hi-Z TO VOL AND VOH TO VOL 1863L7L TC01 (A) VOH TO Hi-Z CL CL (B) VOL TO Hi-Z 1863L7L TC02 1863l7lfa 7 LTC1863L/LTC1867L W UW TI I G DIAGRA S t1 (For Short Pulse Mode) t2 (SDO Valid After SCK), t 3 (SDO Valid Hold Time After SCK) t1 t2 50% 50% CS/CONV SCK 0.45V t3 1.9V 0.45V SDO t 5 (SDI Setup Time Before SCK), t6 (SDI Hold Time After SCK) t4 (SDO Valid After CS/CONV) t4 CS/CONV SDO 1.9V SCK 0.45V Hi-Z 1.9V 0.45V SDI t7 (SLEEP Mode Wake-Up Time) 1.9V 0.45V 1.9V 0.45V t 8 (BUS Relinquish Time) t7 SCK t6 t5 t8 50% CS/CONV 1.9V SLEEP BIT (SLP = 0) READ-IN CS/CONV 50% SDO 90% 10% Hi-Z 1863L7L TD U W U U APPLICATIO S I FOR ATIO Overview The LTC1863L/LTC1867L are complete, low power, multiplexed ADCs. They consist of a 12-/16-bit, 175ksps capacitive successive approximation A/D converter, a precision internal reference, a configurable 8-channel analog input multiplexer (MUX) and a serial port for data transfer. Conversions are started by a rising edge on the CS/CONV input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, the ADCs receive an input word for channel selection and output the conversion result, and the analog input is acquired in preparation for the next conversion. In the acquire phase, a minimum time of 2.01s will provide enough time for the sample-andhold capacitors to acquire the analog signal. During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The input is sucessively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by a low power, differential comparator that rejects common mode noise. At the end of a conversion, the DAC output balances the analog input. The SAR content (a 12-/16-bit data word) that represents the analog input is loaded into the 12-/16-bit output latches. 1863l7lfa 8 LTC1863L/LTC1867L U W U U APPLICATIO S I FOR ATIO Changing the MUX Assignment "On the Fly" Analog Input Multiplexer 1st Conversion The analog input multiplexer is controlled by a 7-bit input data word. The input data word is defined as follows: + -{ + -{ SD OS S1 S0 COM UNI SLP SD = SINGLE/DIFFERENTIAL BIT OS = ODD/SIGN BIT 2nd Conversion CH2 CH3 - + { CH2 CH3 CH4 CH5 + + { CH4 CH5 CH7/COM (UNUSED) CH7/COM (-) S1 = ADDRESS SELECT BIT 1 1863L7L AI02 S0 = ADDRESS SELECT BIT 0 Tables 1 and 2 show the configurations when COM = 0, and COM = 1. COM = CH7/COM CONFIGURATION BIT Table 1. Channel Configuration (When COM = 0, CH7/COM Pin Is Used as CH7) UNI = UNIPOLAR/BIPOLAR BIT SLP = SLEEP MODE BIT Examples of Multiplexer Options 4 Differential + (-) - (+) { + (-) - (+) { + (-) - (+) { + (-) - (+) { CH0 CH1 CH2 CH3 CH4 CH5 + + + + + + + + CH6 CH7/COM 7 Single-Ended to CH7/COM + + + + + + + 8 Single-Ended CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM (-) CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM GND (-) Combinations of Differential and Single-Ended + -{ CH0 CH1 - +{ + + + + CH2 CH3 CH4 CH5 CH6 CH7/COM GND (-) 1863L7L AI01 Channel Configuration "+" "-" SD OS S1 S0 COM 0 0 0 0 0 CH0 CH1 0 0 0 1 0 CH2 CH3 0 0 1 0 0 CH4 CH5 0 0 1 1 0 CH6 CH7 0 1 0 0 0 CH1 CH0 0 1 0 1 0 CH3 CH2 0 1 1 0 0 CH5 CH4 0 1 1 1 0 CH7 CH6 1 0 0 0 0 CH0 GND 1 0 0 1 0 CH2 GND 1 0 1 0 0 CH4 GND 1 0 1 1 0 CH6 GND 1 1 0 0 0 CH1 GND 1 1 0 1 0 CH3 GND 1 1 1 0 0 CH5 GND 1 1 1 1 0 CH7 GND Table 2. Channel Configuration (When COM = 1, CH7/COM Pin Is Used as COMMON) Channel Configuration "+" "-" SD OS S1 S0 COM 1 0 0 0 1 CH0 CH7/COM 1 0 0 1 1 CH2 CH7/COM 1 0 1 0 1 CH4 CH7/COM 1 0 1 1 1 CH6 CH7/COM 1 1 0 0 1 CH1 CH7/COM 1 1 0 1 1 CH3 CH7/COM 1 1 1 0 1 CH5 CH7/COM 1863l7lfa 9 LTC1863L/LTC1867L U W U U APPLICATIO S I FOR ATIO Driving the Analog Inputs The analog inputs of the LTC1863L/LTC1867L are easy to drive. Each of the analog inputs can be used as a singleended input relative to the GND pin (CH0-GND, CH1-GND, etc) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) for differential inputs. In addition, CH7 can act as a COM pin for both single-ended and differential modes if the COM bit in the input word is high. Regardless of the MUX configuration, the "+" and "-" inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors during the acquire mode. In conversion mode, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1863L/LTC1867L inputs can be driven directly. More acquisition time should be allowed for a higher impedance source. The following list is a summary of the op amps that are suitable for driving the LTC1863L/LTC1867L. More detailed information is available in the Linear Technology data books or Linear Technology website. LT(R)1468: 90MHz, 22V/s 16-bit accurate amplifier LT1469: Dual LT1468 LT1490A/LT1491A: Dual/quad micropower amplifiers, 50A/amplifier max, 500V offset, common mode range extends 44V above V- independent of V+, 3V, 5V and 15V supplies. LT1568: Very low noise, active RC filter building block, cutoff frequency up to 10MHz, 2.7V to 5V supplies. ANALOG INPUT LT1638/LT1639: Dual/quad 1.2MHz, 0.4V/s amplifiers, 230A per amplifier, 3V, 5V and 15V supplies. LT1881/LT1882: Dual and quad, 200pA bias current, railto-rail output op amps, up to 15V supplies. LTC1992-2: Gain of 2 fully differential input/output amplifier/driver, 2.5mV offset, CLOAD stable, 2.7V to 5V supplies. LT1995: 30MHz, 1000V/s gain selectable amplifier, pin configurable as a difference amplifier, inverting and noninverting amplifier, 2.5V to 15V supplies. LTC6912: Dual programmable gain amplifiers with SPI serial interface, 2mV offset, 2.7V to 5V supplies. LTC6915: Zero drift, instrumentation amplifier with SPI programmable gain, 125dB CMRR, 0.1% gain accuracy, 10V offset. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1863L/LTC1867L noise and distortion. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For instance, Figure 1 shows a 50 source resistor and a 2000pF capacitor to ground on the input will limit the input bandwidth to 1.6MHz. The source impedance has to be kept low to avoid gain error and degradation in the AC performance. The capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be 1000pF 50 50 CH0 LTC1863L/ LTC1867L 2000pF GND DIFFERENTIAL ANALOG INPUTS CH0 LTC1863L/ LTC1867L 1000pF 50 CH1 1000pF REFCOMP REFCOMP 10F 1863L7L F01a Figure 1a. Optional RC Input Filtering for Single-Ended Input 10F 1863L7L F01b Figure 1b. Optional RC Input Filtering for Differential Inputs 1863l7lfa 10 LTC1863L/LTC1867L U W U U APPLICATIO S I FOR ATIO DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions. For example, in Figure 2 the distribution of output codes is shown for a DC input that had been digitized 4096 times. The distribution is Gaussian and the RMS code transition noise is about 1.6LSB. components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 3a shows a typical SINAD of 81.4dB with a 175kHz sampling rate and a 1kHz input. Higher SINAD can be obtained with a 3V supply. For example, when an external 3V is applied to REFCOMP (tie VREF to GND), a SINAD of 83.5dB can be achieved as shown in Figure 3b. 0 fSAMPLE = 175ksps fIN = 1kHz SNR = 82.9dB SINAD = 81.4dB THD = 86.8dB -20 -40 AMPLITUDE (dB) used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. -60 -80 -100 -120 1200 VDD = 2.7V INTERNAL REF 1044 -140 0 1000 895 21.875 43.75 65.625 FREQUENCY (kHz) 830 1863L7L G03 COUNTS 800 Figure 3a. LTC1867L Nonaveraged 4096 Point FFT Plot with 2.7V Supply 600 465 400 333 0 261 170 0 7 58 fSAMPLE = 175ksps fIN = 1kHz SNR = 84.7dB SINAD = 83.5dB THD = 90dB REFCOMP = EXT 3V -20 23 9 1 20 21 22 23 24 25 26 27 28 29 30 31 CODE 1863L7L G12 Figure 2. LTC1867L Histogram for 4096 Conversions AMPLITUDE (dB) 200 87.5 -40 -60 -80 -100 Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. -120 -140 0 21.875 43.75 65.625 FREQUENCY (kHz) 87.5 1863L7L F03b Figure 3b. LTC1867L Nonaveraged 4096 Point FFT Plot with 3V Supply Signal-to-Noise Ratio Total Harmonic Distortion The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency 1863l7lfa 11 LTC1863L/LTC1867L U W U U APPLICATIO S I FOR ATIO band between DC and half the sampling frequency. THD is expressed as: THD = 20 log V22 + V32 + V42 ... + VN2 V1 Digital Interface where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Internal Reference The LTC1863L and LTC1867L have an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 1.25V. It is internally connected to a reference amplifier and is available at VREF (Pin 10). A 3k resistor is in series with the output so that it can be easily overdriven by an external reference if better drift and/or accuracy are required as shown in Figure 4. The reference amplifier gains the VREF voltage by 2x to 2.5V at REFCOMP (Pin 9). This reference amplifier 1.25V R1 3k 10 VREF BANDGAP REFERENCE 2.2F 2.5V 9 REFCOMP REFERENCE AMP 10F R2 R3 15 GND compensation pin, REFCOMP, must be bypassed with a 10F ceramic or tantalum in parallel with a 0.1F ceramic for best noise performance. LTC1863L/LTC1867L The LTC1863L and LTC1867L have a very simple digital interface that is enabled by the control input, CS/CONV. A logic rising edge applied to the CS/CONV input will initiate a conversion. After the conversion, taking CS/CONV low will enable the serial port and the ADC will present digital data in two's complement format in bipolar mode or straight binary format in unipolar mode, through the SCK/ SDO serial port. Internal Clock The internal clock is factory trimmed to achieve a typical conversion time of 3.2s and a maximum conversion time, 3.7s, over the full operating temperature range. The typical acquisition time is 1.68s, and a throughput sampling rate of 175ksps is tested and guaranteed. Automatic Nap Mode The LTC1863L and LTC1867L go into automatic nap mode when CS/CONV is held high after the conversion is complete. With a typical operating current of 750A and automatic 170A nap mode between conversions, the power dissipation drops with reduced sample rate. The ADC only keeps the VREF and REFCOMP voltages active when the part is in the automatic nap mode. The slower the sample rate allows the power dissipation to be lower (see Figure 5). 1863L7L F04a 800 Figure 4a. LTC1867L Reference Circuit VIN LT1790A-1.25 VOUT 10 2.2F 9 + 10F 0.1F 15 VREF LTC1863L/ LTC1867L SUPPLY CURRENT (A) 3V VDD = 2.7V 700 600 500 400 300 200 REFCOMP 100 1 GND 1863L7L F04b Figure 4b. Using the LT1790A-1.25 as an External Reference 10 100 fSAMPLE (ksps) 1000 1863L7L G09 Figure 5. Supply Current vs fSAMPLE 1863l7lfa 12 LTC1863L/LTC1867L U W U U APPLICATIO S I FOR ATIO If the CS/CONV returns low during a bit decision, it can create a small error. For best performance ensure that the CS/CONV returns low either within 100ns after the conversion starts (i.e. before the first bit decision) or after the conversion ends. If CS/CONV is low when the conversion ends, the MSB bit will appear on SDO at the end of the conversion and the ADC will remain powered up. the common return for these bypass capacitors is essential to the low noise operation of the ADC. The width for these tracks should be as wide as possible. Timing and Control Conversion start is controlled by the CS/CONV digital input. The rising edge transition of the CS/CONV will start a conversion. Once initiated, it cannot be restarted until the conversion is complete. Figures 6 and 7 show the timing diagrams for two types of CS/CONV pulses. Sleep Mode If the SLP = 1 is selected in the input word, the ADC will enter SLEEP mode and draw only leakage current (provided that all the digital inputs stay at GND or VDD). After release from the SLEEP mode, the ADC needs 80ms to wake up (charge the 2.2F/10F bypass capacitors on VREF/REFCOMP pins). Example 1 (Figure 6) shows the LTC1863L/LTC1867L operating in automatic nap mode with CS/CONV signal staying HIGH after the conversion. Automatic nap mode provides power reduction at reduced sample rate. The ADCs can also operate with the CS/CONV signal returning LOW before the conversion ends. In this mode (Example 2, Figure 7), the ADCs remain powered up. The digital output, SDO, will go HIGH immediately after the conversion is complete if the analog inputs are above half scale in unipolar mode or below half scale in bipolar mode. This is a way to measure the conversion time of the A/D converter. Board Layout and Bypassing To obtain the best performance, a printed circuit board with a ground plane is required. Layout for the printed circuit board should ensure digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal. Figures 8 and 9 are the transfer characteristics for the bipolar and unipolar mode. All analog inputs should be screened by GND. VREF, REFCOMP and VDD should be bypassed to this ground plane as close to the pin as possible; the low impedance of 1/fSCK CS/CONV tCONV NAP MODE NOT NEEDED FOR LTC1863L SCK SDI SDO (LTC1863L) DON'T CARE Hi-Z Hi-Z SDO (LTC1867L) 1 2 3 4 SD 0S S1 S0 D9 D8 MSB D11 D10 5 6 7 COM UNI SLP D7 8 9 10 11 12 13 14 15 16 DON'T CARE D6 D5 D4 D3 D2 D1 D0 MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1867 F06 Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV Remaining HIGH after the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate 1863l7lfa 13 LTC1863L/LTC1867L U U W U APPLICATIO S I FOR ATIO tACQ CS/CONV NOT NEEDED FOR LTC1863L SCK SDI DON'T CARE 1 2 3 4 5 6 7 COM UNI SLP 8 9 10 11 12 SD 0S S1 S0 MSB = D11 D10 D9 D8 D6 D5 D4 D3 D2 D1 D0 MSB = D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 13 14 15 16 DON'T CARE t CONV SDO (LTC1863L) Hi-Z SDO (LTC1867L) D7 t CONV D3 D2 D1 D0 Hi-Z 1863L7L F07 111...111 011...111 111...110 BIPOLAR ZERO 011...110 OUTPUT CODE OUTPUT CODE (TWO'S COMPLEMENT) Figure 7. Example 2, CS/CONV Starts a Conversion with Short Active HIGH Pulse. With CS/CONV Returning LOW Before the Conversion, the ADC Remains Powered Up. 000...001 000...000 111...111 111...110 FS = 2.5V 1LSB = FS/2n 1LSB (LTC1863L) = 610V 1LSB (LTC1867L) = 38.1V 100...001 100...000 -FS/2 -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB 100...001 100...000 011...111 UNIPOLAR ZERO 011...110 FS = 2.5V 1LSB = FS/2n 1LSB (LTC1863L) = 610V 1LSB (LTC1867L) = 38.1V 000...001 000...000 0V FS - 1LSB INPUT VOLTAGE (V) 1863L7L F08 Figure 8. LTC1863L/LTC1867L Bipolar Transfer Characteristics (Two's Complement) 1863L7L F09 Figure 9. LTC1863L/LTC1867L Unipolar Transfer Characteristics (Straight Binary) 1863l7lfa 14 LTC1863L/LTC1867L U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 - .196* (4.801 - 4.978) .045 .005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .0165 .0015 .150 - .157** (3.810 - 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) 2 3 4 5 6 7 .0532 - .0688 (1.35 - 1.75) 8 .004 - .0098 (0.102 - 0.249) 0 - 8 TYP .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 - .012 (0.203 - 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1863l7lfa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1863L/LTC1867L RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1417 14-Bit, 400ksps Serial ADC 20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package LT1468/LT1469 Single/Dual 90MHz, 22V/s, 16-Bit Accurate Op Amps Low Input Offset: 75V/125V LTC1609 16-Bit, 200ksps Serial ADC 65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply LT1790 Micropower Low Dropout Reference 60A Supply Current, 10ppm/C, SOT-23 Package LT1790A-1.25 Micropower Precision Series Reference Bandgap, 60A Max Supply Current, 10ppm/C, SOT-23 Package LTC1850/LTC1851 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC Parallel Output, Programmable MUX and Sequencer, 5V Supply LTC1852/LTC1853 10-Bit/12-Bit, 8-Channel, 400ksps ADC Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply LTC1860/LTC1861 12-Bit, 1-/2-Channel 250ksps ADC in MSOP 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages LTC1860L/LTC1861L 3V, 12-Bit, 1-/2-Channel 150ksps ADC 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages LTC1863/LTC1867 12-/16-Bit, 8-Channel 200ksps ADC 5V Supply, Pin Compatible with LTC1863L/LTC1867L LTC1864/LTC1865 16-Bit, 1-/2-Channel 250ksps ADC in MSOP 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 1863l7lfa 16 Linear Technology Corporation LT/LT 0605 REV A * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2005