Features Bipolar Speed Read Access Time - 35 ns Low Power CMOS Operation 25 mA max. Standby 45 mA max. Active at 10 MHz e Direct Bipolar PROM Replacement High Output Drive Capability e Reprogrammable - 100 :s/byte (typical) Tested 100% for Programmability e JEDEC Approved Byte-Wide Pinout 300-mil! DIP, 600-mil DIP and LCC packages CMOS and TTL Compatible Inputs and Outputs High Reliability Latch-Up Resistant CMOS Technology Integrated Product identification Code Full Military, Industrial and Commercial Temperature Ranges Fully Compatible with AT27HC641/2 ee eee Description The AT27HC641R/642R chip family is a high-speed, low-power 65,536 bit reprogrammable read only memory (PROM), which is UV erasable, organized as 8K x 8 bits. All devices require only one 5 V power supply in normal read mode operation. All bytes on the 641R and 642R parts can be accessed in less than 35 ns, making these parts ideal for high-performance systems without penalizing bit density or power consumption. The 640R series of devices come in a choice of JEDEC-approved 24-pin DIP or 28-pad LCC packages, providing a direct power saving CMOS upgrade for systems originally using Bipo- lar PROMs. The AT27HC641R is available in a standard 600-mil cerdip or one-time pro- grammable plastic (OTP) package, and LCC package, while the AT27HC642R is available in a space-saving 300-mil cerdip or plastic (OTP) package. Atmels 1.2-micron, high-speed CMOS technology provides optimum speed, low-power and high noise immunity. Power consumption on the AT27HC641 and AT27HC6472 is typically only 30 mA in Active Mode and less than 10 mA in Standby. The high speed CMOS process is an extension of Atmels high quality and highly manufacturable floating poly PROM tech- nology. The ability to reprogram the PROM, which is fully tested before shipment, provides inherently better programmability and reliability than one-time fusable PROMs. continued on next page Pin Configurations AS A7 VCC AS Pin Name | Function 24 VCC AB NC AB 1 A0-Al2 | Addresses 3 Ano CS/Vpe Chip Select/Vpp 3 h GSvpPp ceiver 00-07 Outputs nq 2 8 o7 3 143 15 17 06 1214 16 18 02 NC O04 01 GND O83 05 Almet AT27HC641R/2R 64K (8K x 8) CMOS PROM Reprogrammable 5-19AIMET Description (Continued) Block Diagram With a storage capacity of 8K bytes, Atmels 640R series parts vec allow firmware to be stored reliably and to be accessed at bipo- GND DATA OUTPUTS lar PROM speeds. All the 640R series parts have exceptional abeeaaas output drive capability - source 4 mA and sink 16 mA per out- CSivep >| CS AND OUTPUT put. CE | PROGRAMLOGIC |__,| BUFFERS Atmels 640R series chips also have additional features to en- _, sure high-quality and efficient production use. The Rapid pro- Ao-At2 | Y DECODER -GATING gramming algorithm reduces the time required to program the ADDRESS | ~ | CELL MATRIX chip and guarantees reliable programming. The Integrated INPUTS _ | *OECODER IDENTIFICATION Product Identification Code electronically identifies the device and manufacturing origin. This feature is used by industry stan- dard programming equipment to select the proper programming . . * algorithms and voltages. Absolute Maximum Ratings Temperature Under Bias ................ -55C to +125C Storage Temperature... -65C to +150C oe Voltage on Any Pin with Erasure Characteristics Respect to Ground.......eecccccccceses -2.0 V to +7.0 Vi") The entire memory array of an Atmel 640R series chip is erased (all outputs read as Vou) after exposure to ultraviolet light at a Respect ta own -2.0V to 414.0 Vi) wavelength of 2537A. Complete erasure is assured afteramin- | "@SP@Ct to Ground .................., , . imum of 20 minutes exposure using 12,000 uW/em? intensity CS/Vpp Supply Voltage with lamps spaced one inch away from the chip. Minimum erase time Respect to Ground......-esescccccces -2.0 V to 414.0 Vi) for lamps at other intensity ratings can be calculated from the 2 minimum integrated erasure dose of 15W-sec/cm*. To prevent Integrated UV Erase Dose.............. 7258 Wesec/cm unintentional erasure, an opaque label is recommended to cover the clear window on any PROM which will be subjected to con- tinuous fluorescent indoor lighting or sunlight. *NOTICE: Stresses beyond those listed under "Absolute Maxi- mum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the de- vice at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Notes: 1. Minimum voltage is -0.6 V de which may undershoot to -2.0 V for pulses of less than 20 ns. Maximum output pin voltage is Voc+0.75 V de which may overshoot to +7.0 V for pulses of less than 20 ns. Operating Modes MODE \ PIN CS/Vpp Ai Voc Outputs Read Vit Ai Vec DouT Standby Vin x) Voc High Z Rapid Program?) Vpp Ai Veo DIN PGM Verify Vit Ai Vec Dout AQ=Vy, ses gs Product Identification'*) Vit AO=VIH or ViL Vec G entitication A1-A12=ViL Notes: 1. X can be Vir or Vin. 4. Two identifier bytes may be selected. All Ai inputs are held 2. Refer to Programming characteristics. low (Viz), except A9 which is set to Vi and AO which is tog- 3. Va = 12.0+0.5 V. gled low (Vir) to select the Manufacturers Identification byte and high (Vi) to select the Device Code byte. 5-20 AT27HC641R/2R seussRees AT 27110641 R/2R D.C. and A.C. Operating Conditions for Read Operation AT27HC641R / AT27HC642R -35 -45 -55 -70 -90 Operating Com. 0C - 70C 0C - 70C 0C - 70C 0C - 70C 0C - 70C Temperature Ind. -40C - 85C | -40C-85C | -40C-85C | -40C - 85C (Case) Mil. -5BC - 125C | -55C - 125C | -55C - 125C | -55C - 125C Voc Power Supply 5V+ 5% 5 V+ 10% 5 V+ 10% 5V+10% 5V+10% D.C. and Operating Characteristics for Read Operation Symbo! Parameter Condition Min Max Units a Input Load Current Vin = -0.1 V to Vec+1 V 10 pA ILo Output Leakage Current VouT = -0.1 V to Vec+0.1 V 10 pA CSVpp (1) _- . IPP Read/Standby Current CSVpp = -0.1 V to Voo+t V 10 HA Isp1 (CMOS) Com. 25 mA CS/Vpp = Vcc-0.3 to Vi 1.0V i IsB Voc Standby Current pps wee oor Ind.,Mil. 30 mA Isp (TTL) Com. 25 mA CS/Vep = 2.0 to Vcc+1.0 V Ind.,Mil. 30 mA Ioc Vcc Active Current {= 10 MHz,lout = 0 mA, Com. 45 mA CS/Vep = Vit ind.,Mil. 50 mA los @ | Output Short Circuit Current Vout =0V -100 mA Vit Input Low Voltage -0.6 0.8 Vv VIH Input High Voltage 2.0 Vec+0.75 Vv VoL Output Low Voltage lo. = 16mA 4 Vv =-1 Vec-0. Vv VoH Output High Voltage loH 00 HA co0.3 loH = -4.0 MA 2.4 Vv Notes: 1. Vcc must be applied simultaneously or before CS/Vpp, and removed simultaneously or after CS/Vpp. 2. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. This parameter is only sampled and is not 100% tested. See Abso- lute Maximum Ratings. A.C. Characteristics for Read Operation AT27HC641R / AT27HC642R -35 -45 -55 -70 -90 Symbol Parameter Min Max | Min Max | Min) Max | Min) Max | Min Max | Units tan @ Address to Com. 35 45 55 70 90 | ns Output Delay Ind.,Mil 45 55 70 90 | ns tcs 2) |ES/vep to Output Delay 25 30 35 45 55 | ns tcp &45) |ES/vep to Output Float 0 2/0 30/0 35|0 40/0 45 | ns Notes: 2, 3, 4,5. - see AC Waveforms for Read Operation. ANMEL 5-2 ee| A.C. Waveforms for Read Operation Notes: ADDRESS 1. Timing measurement reference is 1.5 V. Input AC driving levels are 0.0 V and 3.0 V, unless axe otherwise specified. cs/vPP 2. Asserting CS/Vpp may be delayed up to tA tCS taa - tcs after the address transition without im- HIGH pact on access time. OUTPUT oa pUT z OAL qT 3. This parameter is only sampled and is not 100% tested. 4. CL = 30 pF, add 10 ns for Cy = 100 pF. 5. Output float is defined as the point when data is no longer driven. Input Test Waveforms Output Test Load and Measurement Levels 5 0V ad 250 AC AC OUTPUT DRIVING MEASUREMENT PIN LEVELS LEVEL 0.0V 167 CL Co. Lt Note: Ci=30pF including tr, F< 5 ns (10% to 90%) Jig capacitance. Pin Capacitance (f=1MHz T= 25C) Typ Max Units Conditions CIN 4 6 pF ViNn=O0V CouT 8 12 pF Vout =0V Notes: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Programming Waveforms PROGRAM VERIFY VIH ADDRESS OK __ADDRESS STABLE tas tAH VIH DATA VIL DATA IN DATA OUT] tDs | P-1DH vcc 6.5V _ wes L- tcss J pes) Pe Notes: 13.0V 1. The Input Timing References are 0.0 V for Vi_ CS/VPP and 3.0 V for Vin. 5.0V toPwW / 2. tes and tprp are characteristics of the device but vit Pw _ must be accommodated by the programmer. 5-22 AT27HC641R/2R summerses AT 2/1641 R/2R D.C. Programming Characteristics Tas 25+ 58C, Voc = 6.5t 0.25 V, CSWVpp = 13.04 0.25 V Sym- Test Limits bol Parameter Conditions Min Max Units lu Input Load Current Vin=Vi.Vin 10 pA ViL | Input Low Level (Allnputs) -0.6 0.8 Vv Vit | Input High Level 2.0 Veol V VoL | Output Low Volt. lol = 16 mA 4 Vv VoH | Output High Volt. iox=-4.0mA 2.4 Vv Vec Supply Current Icce (Program and Verify) 50 mA CGS/Wep Supply men. Ipp2 Current CS/Vpp=Vep 30 mA AQ Product Vip | Kdentification 11.5 125 V Voltage A.C. Programming Characteristics Ta = 25 + 5C, Vec= 6.5 t 0.25 V, CS/Vpp=13.0+ 0.25 V Test Sym- Conditions* _Limits bol Parameter (see Note 1) Min Max Units tas _| Address Setup Time 2 ps tess | CS/Vep Setup Time 2 ps tps | Data Setup Time 2 ps taH | Address Hold Time 0 ps toH | Data Hold Time 2 ps CSN pp High to torp | Output Float (Note 2) 0 130 ons Delay tvcs | Vcc Setup Time 2 ps CS Program tPW | Pulse Width (Note 3) 95 105s tes _| Data Valid from CS/Vpp 70 ns *A.C. Conditions of Test: Input Rise and Fall Times (10% to 90%) .......... 5 ns Input Pulse Levels ...............000-- 0.0 V to 3.0 V Input Timing Reference Level ................. 15V Output Timing Reference Level ................ 15V Notes: 1. Vcc must be applied simultaneously or before CS/Vep and removed simultaneously or after CS/Vpp. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven see timing diagram. 3. Program Pulse width tolerance is 100 psec + 5%. Atmels 27HC641R/2R Integrated Product Identification Code Pins Hex Codes AO 07 08 O5 O4 03 O02 01 00 |Data Manufacturer|O0 0 0 0 1 1 #1 #1 =#0'4f 1E DeviceType |1 0 0 0 1 0 0 0 O | 10 Rapid Programming Algorithm A 100 ps CS/Vpp pulse width is used to program. The address is set to the first location. Voc is raised to 6.5 V and CS/Vpp is raised to 13.0 V. Each address is first programmed with one 100 pis CS/Vpp pulse without verification. Then a verification / re- programming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 1s pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is consid- ered failed. After the byte verifies properly, the next address is selected until all have been checked. CS/Vpp is then lowered to 5.0 V and Vcc to 5.0 V. All bytes are read again and compared with the original data to determine if the device passes or fails. ADDA = FIRST LOCATION VCC = 6.5V CSEWVPP = 13.0V PROGAAM ONE 100 uS PULSE AIMEL 5-23Almgt Ordering Information te an Teena Ordering Code Package Operation Range 35 45 25 AT27HC641R-35DC 24DW6 Commercial AT27HC642R-35DC 24DW3 (0C to 70C) AT27HC641R-35LC 28LW 45 45 25 AT27HC641R-45DC 24DW6 Commercial AT27HC642R-45DC 24DW3 (0C to 70C) AT27HC641R-45LC 28LW AT27HC641R-45PC 24P6 AT27HC642R-45PC 24P3 45 50 30 AT27HC641R-45DI 24DW6 Industrial AT27HC642R-45DI 24DW3 (-40C to 85C) AT27HC641R-45LI 28LW AT27HC641R-45Pl 24P6 AT27HC642R-45P! 24P3 AT27HC641R-45DM 24DW6 Military AT27HC642R-45DM 24DW3 (-55C to 125C) AT27HC641R-45LM 28LW AT27HC641R-45DM/883 24DW6 Military/883C AT27HC642R-45DM/883 24DW3 Ciass B, Fully Compliant AT27HC641R-45LM/883 28LW (-55C to 125C) 55 45 25 AT27HC641R-55DC 24DW6 Commercial AT27HC642R-55DC 24DW3 (0C to 70C) AT27HC641R-55LC 28LW AT27HC641R-55PC 24P6 AT27HC642R-55PC 24P3 55 50 30 AT27HC641R-55DI 24DW6 Industrial AT27HC642R-55DI 24DW3 (-40C to 85C) AT27HC641R-55LI 28Lw AT27HC641R-55Pi 24P6 AT27HC642R-55PI 24P3 AT27HC641R-55DM 24DW6 Military AT27HC642R-55DM 24DW3 (-55C to 125C) AT27HC641R-55LM 28LW AT27HC641R-55DM/883 24DW6 Military/883C AT27HC642R-55DM/883 24DW3 Class B, Fully Compliant AT27HC641R-55LM/883 28LW (-55C to 125C) 70 45 25 AT27HC641R-70DC 24DW6 Commercial AT27HC642R-70DC 24DW3 (0C to 70C) AT27HC641R-70LC 28Lw AT27HC641R-70PC 24P6 AT27HC642R-70PC 24P3 70 50 30 AT27HC641R-70DI 24DW6 Industrial AT27HC642R-70DI 24DW3 (-40C to 85C) AT27HC641R-70L! 28LW AT27HC641R-70PI 24P6 AT27HC642R-70PI 24P3 5-24 AT27HC641R/2R suenaees A 1 2711 C641 R/2R Ordering Information tacc Icc (MA, (ns) Active ( = Ordering Code Package Operation Range ry 70 50 30 AT27HC641R-70DM 24DW6 Military AT27HC642R-70DM 24DW3 (-55C to 125C) AT27HC641R-70LM 28Lw AT27HC641R-70DM/883 24DW6 Military/883C AT27HC642R-70DM/883 24DW3 Class B, Fully Compliant AT27HC641R-70LM/883 28Lw (-55C to 125C) 90 45 25 AT27HC641R-90DC 24DW6 Commercial AT27HC642R-90DC 24DW3 (0C to 70C) AT27HC641R-90LC 28LW AT27HC641R-90PC 24P6 AT27HC642R-90PC 24P3 90 50 30 AT27HC641R-90D! 24DW6 Industrial AT27HC642R-90DI 24DW3 (-40C to 85C) AT27HC641R-S0LI 28Lw AT27HC641R-90Pi 24P6 AT27HC642R-90P! 24P3 AT27HC641R-90DM 24DW6 Military AT27HC642R-90DM 24DW3 (-55C to 125C) AT27HC641R-S0LM 28LW AT27HC641R-90DM/883 24DW6 Military/883C AT27HC642R-90DM/883 24DW3 Class B, Fully Compliant AT27HC641R-90LM/883 28Lw (-55C to 125C) 45 50 30 5962-87515 01 JX 24DW6 Military/883C 5962-87515 01 KX 24CW Class B, Fully Compliant 5962-87515 01 LX 24DW3 (-55C to 125C) 5962-87515 01 3X 28Lw 55 50 30 5962-87515 02 JX 24DW6 Military/883C 962-87515 02 KX 24Cw Class B, Fully Compliant 5962-87515 02 LX 24DW3 (-55C to 125C) 5962-87515 02 3X 28Lw 70 50 30 5962-87515 03 JX 24DW6 Military/883C 5962-87515 03 KX 24CW Class B, Fully Compliant 5962-87515 03 LX 24DW3 (-55C to 125C) 5962-87515 03 3X 28Lw 90 50 30 5962-87515 04 JX 24DW6 Military/883C 5962-87515 04 KX 24CW Class B, Fully Compliant 5962-87515 04 LX 24DW3 (-55C to 125C) 5962-87515 04 3X 28LW Package Type 24CW 24 Lead, Windowed, Ceramic Flat Package (Cerpack) 24DW3 24 Lead, 0.300" Wide, Windowed, Ceramic Dual Inline Package (Cerdip) 24DW6 24 Lead, 0.600" Wide, Windowed, Ceramic Dual Inline Package (Cerdip) 28LW 28 Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) 24P3 24 Lead, 0.300 Wide, Plastic Dual Inline Package OTP (PDIP) 24P6 24 Lead, 0.600" Wide, Plastic Dual Inline Package OTP (PDIP) AIMEL 5-25