SCLS401G - APRIL 1998 - REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25C Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) CLR 1Q 1D 2D 2Q 3D 3Q GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 6Q 6D 5D 5Q 4D 4Q CLK SN54LV174A . . . FK PACKAGE (TOP VIEW) 1Q CLR NC VCC 6Q D SN54LV174A . . . J OR W PACKAGE SN74LV174A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) description/ordering information 3 The 'LV174A devices are hex D-type flip-flops designed for 2-V to 5.5-V VCC operation. 1D 2D NC 2Q 3D 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6D 5D NC 5Q 4D 3Q GND NC CLK 4Q These devices are positive-edge-triggered flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of the clock pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. 4 NC - No internal connection ORDERING INFORMATION TOP-SIDE MARKING Tube of 40 SN74LV174AD Reel of 2500 SN74LV174ADR SOP - NS Reel of 2000 SN74LV174ANSR 74LV174A SSOP - DB Reel of 2000 SN74LV174ADBR LV174A Tube of 90 SN74LV174APW Reel of 2000 SN74LV174APWR Reel of 250 SN74LV174APWT TVSOP - DGV Reel of 2000 SN74LV174ADGVR LV174A CDIP - J Tube of 25 SNJ54LV174AJ SNJ54LV174AJ CFP - W Tube of 150 SNJ54LV174AW SNJ54LV174AW SOIC - D -40C to 85C TSSOP - PW -55C -55 C to 125 125C C ORDERABLE PART NUMBER PACKAGE TA LV174A LV174A LCCC - FK Tube of 55 SNJ54LV174AFK SNJ54LV174AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated !"#$% !%&% %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# )$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/, ("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++ )&(&#$$(, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCLS401G - APRIL 1998 - REVISED APRIL 2005 FUNCTION TABLE INPUTS CLR CLK OUTPUT Q D L X X L H H H H L L H L X Q0 logic diagram (positive logic) 1 CLR CLK 1D 9 3 1D C1 2 1Q R To Five Other Channels Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS401G - APRIL 1998 - REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV174A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL t/v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.5 2 5.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 VCC x 0.7 Output voltage UNIT V V 0.5 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 0 0 VCC -50 VCC = 2 V VCC = 2.3 V to 2.7 V VCC x 0.3 VCC x 0.3 0 V VCC -50 A 0 V -2 -6 -6 -12 -12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 12 200 200 100 100 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V V VCC x 0.3 5.5 -2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Input transition rise or fall rate MAX VCC x 0.7 VCC x 0.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level output current MIN 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V High-level output current SN74LV174A mA A mA ns/V VCC = 4.5 V to 5.5 V 20 20 TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV174A PARAMETER VOH VOL TEST CONDITIONS IOH = -50 A IOH = -2 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND MIN 2 V to 5.5 V IOH = -6 mA IOH = -12 mA II ICC VCC IO = 0 TYP SN74LV174A MAX MIN 2.3 V VCC-0.1 2 VCC-0.1 2 3V 2.48 2.48 4.5 V 3.8 TYP MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V V 0.55 0.55 0 to 5.5 V 1 1 A 5.5 V 20 20 A 0 5 5 A 3.3 V 1.7 1.7 pF %'(#&% !%!$(% )("! % $ '(#&1$ ( $0% )&$ ' $1$+)#$%, &(&!$(! && &% $( )$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCLS401G - APRIL 1998 - REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration tsu Setup time before CLK th Hold time, data after CLK TA = 25C TYP MAX SN54LV174A MIN MAX SN74LV174A MIN CLR low 6 6.5 6.5 CLK high or low 7 7 7 8.5 9.5 9.5 4 4 4 -0.5 0 0 Data CLR inactive MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration tsu Setup time before CLK th Hold time, data after CLK TA = 25C TYP MAX SN54LV174A MIN MAX SN74LV174A MIN CLR low 5 5 5 CLK high or low 5 5 5 Data 5 6 6 CLR inactive 3 3 3 0 0 0 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration tsu Setup time before CLK th Hold time, data after CLK TA = 25C TYP MAX FROM (INPUT) TO (OUTPUT) fmax CLK Q CLK MIN 5 5 5 5 5 Data 4.5 4.5 4.5 CLR inactive 2.5 2.5 2.5 0.5 0.5 0.5 free-air TA = 25C TYP MAX SN54LV174A CL = 15 pF 55* 115* 50* 50 CL = 50 pF 45 90 40 40 CL = 15 pF Q CL = 50 pF ns ns ns range, MIN MAX 17.3* 1* 19.5* 1 19.5 8.4* 17.1* 1* 19* 1 19 8.2 21.9 1 23.5 1 23.5 10.8 20.6 1 23 1 23 * On products compliant to MIL-PRF-38535, this parameter is not production tested. %'(#&% !%!$(% )("! % $ '(#&1$ ( $0% )&$ ' $1$+)#$%, &(&!$(! && &% $( )$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$, * DALLAS, TEXAS 75265 UNIT MHz 6.3* 2 POST OFFICE BOX 655303 MAX UNIT SN74LV174A MIN MIN MAX temperature LOAD CAPACITANCE tsk(o) 4 SN74LV174A 5 CLR tpd MAX CLK high or low CLR tpd MIN CLR low switching characteristics over recommended operating VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER SN54LV174A 2 ns ns SCLS401G - APRIL 1998 - REVISED APRIL 2005 switching characteristics over recommended operating VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25C TYP MAX Q CLK 95* 170* 80* 80 CL = 50 pF 55 130 50 50 CL = 15 pF CL = 50 pF MIN MAX range, SN74LV174A CL = 15 pF Q CLK SN54LV174A MIN CLR tpd temperature LOAD CAPACITANCE CLR tpd free-air MIN MAX MHz 4.5* 11.4* 1* 13.5* 1 13.5 5.8* 11* 1* 13* 1 13 6 14.9 1 17 1 17 7.5 14.5 1 16.5 1 16.5 tsk(o) UNIT 1.5 ns ns 1.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax LOAD CAPACITANCE TA = 25C MIN TYP MAX Q CLK MIN MAX MIN 240* 110* 110 90 180 80 80 CL = 15 pF CL = 50 pF range, SN74LV174A 130* Q CLK SN54LV174A CL = 50 pF CLR tpd temperature CL = 15 pF CLR tpd free-air MAX MHz 3* 7.6* 1* 9* 1 9 4.1* 7.2* 1* 8.5* 1 8.5 4.2 9.6 1 11 1 11 5.5 9.2 1 10.5 1 10.5 tsk(o) UNIT 1 ns ns 1 * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 5) SN74LV174A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.34 0.8 V Quiet output, minimum dynamic VOL -0.3 -0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3.02 High-level dynamic input voltage V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 15.1 operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz 14 pF %'(#&% !%!$(% )("! % $ '(#&1$ ( $0% )&$ ' $1$+)#$%, &(&!$(! && &% $( )$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SCLS401G - APRIL 1998 - REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 k From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL VOH 50% VCC VOL 50% VCC 50% VCC 0V tPLZ tPZL Output Waveform 1 S1 at VCC (see Note B) VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC VCC Output Control 50% VCC VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LV174AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174ADE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174ADG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV174ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV174ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV174ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV174ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV174ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV174ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174APW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV174APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 28-Aug-2010 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LV174APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV174APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV174APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LV174ADGVR TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 12.0 Q1 DGV 16 2000 330.0 12.4 6.8 4.0 1.6 W Pin1 (mm) Quadrant SN74LV174ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV174ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV174APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV174APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV174ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV174ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV174ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV174APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV174APWT TSSOP PW 16 250 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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