74HC4094; 74HCT4094
8-stage shift-and-store bus register
Rev. 8 — 14 November 2018 Product data sheet
1. General description
The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks. The device
features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is
shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-
HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data
is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when
clock edges are slow. The data in the shift register is transferred to the storage register when the
STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable
input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state.
Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC4094: CMOS level
For 74HCT4094: TTL level
Low-power dissipation
ESD protection:
••HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
4. Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74HC4094D
74HCT4094D
-40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC4094DB
74HCT4094DB
-40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HC4094PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT403-1
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
5. Functional diagram
15
2
OE
D
CP STR
3 1
QP0
QP1
QP2
QP3
QP4
QP5
QP6
QP7
QS1
QS2
9
10
4
5
6
7
14
13
12
11
001aaf111
Fig. 1. Logic symbol
001aaf112
2 4
C1/
1D
EN3
SRG8
C2
5
6
7
14
13
12
11
9
10
32D
3
15
1
Fig. 2. IEC Logic symbol
001aaf119
8-STAGE SHIFT
REGISTER
8-BIT STORAGE
REGISTER
3-STATE OUTPUTS
D
2QS2 10
QS1
QP0
4 5 6 7 14 13 12 11
QP1 QP2 QP3 QP4 QP5 QP6 QP7
9
CP
3
STR
1
OE
15
Fig. 3. Functional diagram
001aag799
DD
CP
CP
Q
FF 0
D
LE
Q
LATCH 0
D
CP
Q
FF 7
D
LE
Q
LATCH 7
D
CP
Q
STAGES 1 TO 6STAGE 0 STAGE 7
QP2QP0
D QS2
QS1
LE
Q
LATCH
QP1
QP4
QP3
QP6
QP5 QP7
STR
OE
Fig. 4. Logic diagram
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 2 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
6. Pinning information
6.1. Pinning
74HC4094
74HCT4094
STR VCC
D OE
CP QP4
QP0 QP5
QP1 QP6
QP2 QP7
QP3 QS2
GND QS1
001aan577
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Fig. 5. Pin configuration SOT109-1 (SO16)
74HC4094
74HCT4094
STR VCC
D OE
CP QP4
QP0 QP5
QP1 QP6
QP2 QP7
QP3 QS2
GND QS1
001aan578
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Fig. 6. Pin configuration SOT338-1 (SSOP16) and
SOT403-1 (TSSOP16)
6.2. Pin description
Table 2. Pin description
Symbol Pin Description
STR 1 strobe input
D 2 data input
CP 3 clock input
QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output
GND 8 ground supply voltage
QS1, QS2 9, 10 serial output
OE 15 output enable input
VCC 16 supply voltage
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 3 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = HIGH-impedance OFF-state; NC = no change;
↑ = positive-going transition; ↓ = negative-going transition;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Inputs Parallel outputs Serial outputs
CP OE STR D QP0 QPn QS1 QS2
L X X Z Z Q6S NC
L X X Z Z NC Q7S
H L X NC NC Q6S NC
H H L L QPn -1 Q6S NC
H H H H QPn -1 Q6S NC
H H H NC NC NC Q7S
001aaf117
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
Z-state
Z-state
At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the
QSn outputs.
Fig. 7. Timing diagram
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 4 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA
IOoutput current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA
ICC supply current - +50 mA
IGND ground current - -50 mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation SO16, SSOP16 and TSSOP16 packages [1] - 500 mW
[1] For SO16: Ptot derates linearly with 8 mW/K above 70 °C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
74HC4094 74HCT4094Symbol Parameter Conditions
Min Typ Max Min Typ Max
Unit
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0 - VCC V
VOoutput voltage 0 - VCC 0 - VCC V
Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
Δt/ΔV input transition rise and fall rate
VCC = 6.0 V - - 83 - - - ns/V
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 5 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
74HC4094
VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VIH HIGH-level
input voltage
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VIL LOW-level
input voltage
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VI = VIH or VIL
IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
VOH HIGH-level
output voltage
IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
VOL LOW-level
output voltage
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current
VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current
VI = VIH or VIL;
VO = VCC or GND;
VCC = 6.0 V
- - ±0.5 - ±5.0 - ±10.0 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
- - 8.0 - 80 - 160 μA
CIinput
capacitance
- 3.5 - - - - - pF
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 6 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
74HCT4094
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V
VOH HIGH-level
output voltage
IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA - 0 0.1 - 0.1 - 0.1 V
VOL LOW-level
output voltage
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current
VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current
VI = VIH or VIL;
VO = VCC or GND;
VCC = 5.5 V
- - ±0.5 - ±5.0 - ±10 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
- - 8.0 - 80 - 160 μA
VI = VCC - 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
per input pin; STR input - 100 360 - 450 - 490 μA
per input pin; OE input - 150 540 - 675 - 735 μA
per input pin; CP input - 150 540 - 675 - 735 μA
ΔICC additional
supply current
per input pin; D input - 40 144 - 180 - 196 μA
CIinput
capacitance
- 3.5 - - - - - pF
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 7 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 12.
25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
74HC4094
CP to QS1; see Fig. 8 [1]
VCC = 2.0 V - 50 150 - 190 - 225 ns
VCC = 4.5 V - 18 30 - 38 - 45 ns
VCC = 5 V; CL = 15 pF - 15 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
CP to QS2; see Fig. 8 [1]
VCC = 2.0 V - 44 135 - 170 - 205 ns
VCC = 4.5 V - 16 27 - 34 - 41 ns
VCC = 5 V; CL = 15 pF - 13 - - - - - ns
VCC = 6.0 V - 13 23 - 29 - 35 ns
CP to QPn; see Fig. 8 [1]
VCC = 2.0 V - 63 195 - 245 - 295 ns
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC = 5 V; CL = 15 pF - 20 - - - - - ns
VCC = 6.0 V - 18 33 - 42 - 50 ns
STR to QPn; see Fig. 9 [1]
VCC = 2.0 V - 58 180 - 225 - 270 ns
VCC = 4.5 V - 21 36 - 45 - 54 ns
VCC = 5 V; CL = 15 pF - 18 - - - - - ns
tpd propagation
delay
VCC = 6.0 V - 17 31 - 38 - 46 ns
OE to QPn; see Fig. 10 [1]
VCC = 2.0 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
ten enable time
VCC = 6.0 V - 16 30 - 37 - 45 ns
OE to QPn; see Fig. 10 [1]
VCC = 2.0 V - 41 125 - 155 - 190 ns
VCC = 4.5 V - 15 25 - 31 - 38 ns
tdis disable time
VCC = 6.0 V - 12 21 - 26 - 32 ns
QPn and QSn; see Fig. 8 [1]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
tttransition
time
VCC = 6.0 V - 6 13 - 16 - 19 ns
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 8 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
CP HIGH or LOW;
see Fig. 8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
STR HIGH; see Fig. 9
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
tWpulse width
VCC = 6.0 V 14 4 - 17 - 20 - ns
D to CP; see Fig. 11
VCC = 2.0 V 50 14 - 65 - 75 - ns
VCC = 4.5 V 10 5 - 13 - 15 - ns
VCC = 6.0 V 9 4 - 11 - 13 - ns
CP to STR; see Fig. 9
VCC = 2.0 V 100 28 - 125 - 150 - ns
VCC = 4.5 V 20 10 - 25 - 30 - ns
tsu set-up time
VCC = 6.0 V 17 8 - 21 - 26 - ns
D to CP; see Fig. 11
VCC = 2.0 V 3 -6 - 3 - 3 - ns
VCC = 4.5 V 3 -2 - 3 - 3 - ns
VCC = 6.0 V 3 -2 - 3 - 3 - ns
CP to STR; see Fig. 9
VCC = 2.0 V 0 -14 - 0 - 0 - ns
VCC = 4.5 V 0 -5 - 0 - 0 - ns
thhold time
VCC = 6.0 V 0 -4 - 0 - 0 - ns
CP; see Fig. 8
VCC = 2.0 V 6.0 28 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 87 - 24 - 20 - MHz
VCC = 5 V; CL = 15 pF - 95 - - - - - MHz
fmax maximum
frequency
VCC = 6.0 V 35 103 - 28 - 24 - MHz
CPD power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
[2] - 83 - - - - - pF
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 9 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
74HCT4094
CP to QS1; see Fig. 8 [1]
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC = 5 V; CL = 15 pF - 19 - - - - - ns
CP to QS2; see Fig. 8 [1]
VCC = 4.5 V - 21 36 - 45 - 54 ns
VCC = 5 V; CL = 15 pF - 18 - - - - - ns
CP to QPn; see Fig. 8 [1]
VCC = 4.5 V - 25 43 - 54 - 65 ns
VCC = 5 V; CL = 15 pF - 21 - - - - - ns
STR to QPn; see Fig. 9 [1]
VCC = 4.5 V - 22 39 - 49 - 59 ns
tpd propagation
delay
VCC = 5 V; CL = 15 pF - 19 - - - - - ns
OE to QPn; see Fig. 10 [1]ten enable time
VCC = 4.5 V - 20 35 - 44 - 53 ns
OE to QPn; see Fig. 10 [1]tdis disable time
VCC = 4.5 V - 21 35 - 44 - 53 ns
QPn and QSn; see Fig. 8 [1]tttransition
time VCC = 4.5 V - 7 15 - 19 - 22 ns
CP HIGH or LOW;
see Fig. 8
VCC = 4.5 V 16 7 - 20 - 24 - ns
STR HIGH; see Fig. 9
tWpulse width
VCC = 4.5 V 16 5 - 20 - 24 - ns
Dn to CP; see Fig. 11
VCC = 4.5 V 10 4 - 13 - 15 - ns
CP to STR; see Fig. 9
tsu set-up time
VCC = 4.5 V 20 9 - 25 - 30 - ns
Dn to CP; see Fig. 11
VCC = 4.5 V 4 0 - 4 - 4 - ns
CP to STR; see Fig. 9
thhold time
VCC = 4.5 V 0 -4 - 0 - 0 - ns
CP; see Fig. 8
VCC = 4.5 V 30 80 - 24 - 20 - MHz
fmax maximum
frequency
VCC = 5 V; CL = 15 pF - 86 - - - - - MHz
CPD power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC - 1.5 V
[2] - 92 - - - - - pF
[1] tpd is the same as tPLH and tPHL; ten is the same as tPZH and tPZL; tdis is the same as tPLZ and tPHZ; tt is the same as tTHL and tTLH.
[2] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC
2 x fi x N + ∑(CL x VCC
2 x fo) where:
fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF;
VCC = supply voltage in V; N = number of inputs switching; ∑(CL x VCC
2 x fo) = sum of outputs.
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 10 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
11.1. Waveforms and test circuits
1/fmax
tW
tPHL
tPLH
VI
GND
VOH
VOL
QPn, QS1 output
CP input VM
VM
90 %
10 %
aaa-003132
tPHL
tPLH
tTLH tTHL
VOH
VOL
QS2 output VM
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8. Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse
width and the maximum frequency (CP)
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 9. Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock set-up
and hold times for strobe input
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 11 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
001aaf116
tPLZ
tPHZ
outputs
disabled
outputs
enabled
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input VM
VI
VOL
VOH
GND
VY
VX
tPZL
tPZH
VM
VM
VCC
GND
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 10. Enable and disable times
001aaf115
GND
GND
th
tsu
th
tsu
VM
VM
VM
VI
VOH
VOL
VI
QPn, QS1, QS2 output
CP input
D input
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 11. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times
Table 8. Measurement points
Input OutputType
VMVMVXVY
74HC4094 0.5VCC 0.5VCC 0.1VOH 0.9VOH
74HCT4094 1.3 V 1.3 V 0.1VOH 0.9VOH
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 12 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
G
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig. 12. Test circuit for measuring switching times
Table 9. Test data
Input Load S1 positionType
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC4094 VCC 6 ns 15 pF, 50 pF 1 kΩ open GND VCC
74HCT4094 3 V 6 ns 15 pF, 50 pF 1 kΩ open GND VCC
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 13 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
12. Package outline
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A
1 A
2 A
3 b
p c D
(1) E
(1) (1)
e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10
1.45
1.25 0.25 0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8 1.27 6.2
5.8
0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004
0.057
0.049 0.01 0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15 0.05
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Fig. 13. Package outline SOT109-1 (SO16)
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 14 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
UNIT A
1 A
2 A
3 b
p c D
(1) E
(1) e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05
1.80
1.65 0.25 0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2 0.65 1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8
0
o
o
0.13 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
w M
b
p
D
H
E
E
Z
e
c
v M A
X
A
y
1 8
16 9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
Fig. 14. Package outline SOT338-1 (SSOP16)
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 15 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
UNIT A
1 A
2 A
3 b
p c D
(1) E (2) (1)
e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3 0.65 6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.1 0.2 1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
1 8
16 9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
Fig. 15. Package outline SOT403-1 (TSSOP16)
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 16 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
13. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4094 v.8 20181114 Product data sheet - 74HC_HCT4094 v.7
Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Fig. 7 corrected.
74HC_HCT4094 v.7 20160210 Product data sheet - 74HC_HCT4094 v.6
Modifications: Type numbers 74HC4094N and 74HCT4094N (SOT38-4) removed.
74HC_HCT4094 v.6 20121231 Product data sheet - 74HC_HCT4094 v.5
Modifications: General description updated.
74HC_HCT4094 v.5 20120628 Product data sheet - 74HC_HCT4094 v.4
Modifications: VX and VY measurement points added to Table 8.
74HC_HCT4094 v.4 20111219 Product data sheet - 74HC_HCT4094 v.3
Modifications: Legal pages updated.
74HC_HCT4094 v.3 20110214 Product data sheet - 74HC_HCT4094_CNV v.2
74HC_HCT4094_CNV v.2 19970901 Product specification - -
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 17 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
15. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Objective [short]
data sheet
Development This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification This document contains data from
the preliminary specification.
Product [short]
data sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 18 / 19
Nexperia 74HC4094; 74HCT4094
8-stage shift-and-store bus register
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description............................................................. 3
7. Functional description................................................. 4
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................5
10. Static characteristics..................................................6
11. Dynamic characteristics.............................................8
11.1. Waveforms and test circuits.....................................11
12. Package outline........................................................ 14
13. Abbreviations............................................................ 17
14. Revision history........................................................17
15. Legal information......................................................18
© Nexperia B.V. 2018. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 14 November 2018
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 8 — 14 November 2018 19 / 19