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DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product-Change Notification
DQualification Pedigree†
D21:3 Data Channel Compression at up to
1.36 Gigabits per Second Throughput
DSuited for Point-to-Point Subsystem
Communication With Very Low EMI
D21 Data Channels Plus Clock in
Low-Voltage TTL and 3 Data Channels Plus
Clock Out Low-Voltage Differential
DOperates From a Single 3.3-V Supply and
250 mW (Typ)
D5-V Tolerant Data Inputs
D’LVDS95 Has Rising Clock Edge Triggered
Inputs
DBus Pins Tolerate 6-kV HBM ESD
DPackaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
DConsumes <1 mW When Disabled
DWide Phase-Lock Input Frequency Range
20 MHz to 68 MHz
DNo External Components Required for PLL
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DInputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
DIndustrial Temperature Qualified
TA = −40°C to 85°C
DReplacement for the National DS90CR215
description/ordering information
The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out
shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single
integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted
over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.
When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising
edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to
serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT)
are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
Copyright 2003, Texas Instruments Incorporated
!"# $%
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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27
26
25
D4
VCC
D5
D6
GND
D7
D8
VCC
D9
D10
GND
D11
D12
NC
D13
D14
GND
D15
D16
D17
VCC
D18
D19
GND
D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSVCC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKIN
D20
DGG PACKAGE
(TOP VIEW)
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description/ordering information (continued)
The SN65LVDS95 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The
only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock
and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal
registers to a low level.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
−40°C to 85°CTSSOP − DGG Tape and reel SN65LVDS95DGGREP 65LVDS95EP
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional block diagram
Serial/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
D0−6
Serial/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
D7−13
Serial/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
D14−20
CLKINH
7×CLK
7× Clock/PLL
CLKIN
Control Logic
SHTDN
CLK
A,B, ...G
A,B, ...G
A,B, ...G
7
7
7
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
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CLKOUT
D0-1
D6 D5 D4 D3 D2 D1 D0 D6+1
D7-1
D13 D12 D11 D10 D9 D8 D7 D13+1
D14-1
D20 D19 D18 D17 D16 D15 D14 D20+1
Current Cycle NextPrevious Cycle
Y2
Y1
Y0
CLKIN
’LVDS95
Dn
Figure 1. ’LVDS95 Load and Shift Sequences
equivalent input and output schematic diagrams
VCC
7 V
300 kΩ
50 Ω
D or
SHTDN 50 Ω
VCC
YnP or
YnM
7 V
10 kΩ
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any output terminal, VO −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any input terminal, VI −0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (see Note 2): Bus pins (Class 3A) 6 KV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus pins (Class 2B) 400 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All pins (Class 3A) 6 KV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All pins (Class 2B) 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation (see Dissipation Rating Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals.
2. This rating is measured using MIL-STD-883C Method, 3015.7.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR‡
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
DGG 1316 mW 13.1 mW/°C724 mW 526 mW
‡This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
Differential load impedance, ZL90 132 Ω
Operating free-air temperature, TA−40 85 °C
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electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT Input voltage threshold 1.4 V
|VOD|Differential steady-state output voltage magnitude 247 454
∆|VOD|Change in the steady-state differential output
voltage magnitude between opposite binary states RL = 100 Ω, See Figure 3 50 mV
VOC(SS) Steady-state common-mode output voltage
See Figure 3
1.125 1.375 V
VOC(PP) Peak-to-peak common-mode output voltage See Figure 3 80 150 mV
IIH High-level input current VIH = VCC 20 µA
IIL Low-level input current VIL = 0 V ±10 µA
IOS
Short-circuit output current
VOY = 0 V ±24 mA
IOS Short-circuit output current VOD = 0 V ±12 mA
IOZ High-impedance state output current VO = 0 V to VCC ±10 µA
Disabled, all inputs at GND 280 µA
ICC(AVG
)
Quiescent current (average) Enabled, RL = 100 Ω (4 places),
Worst-case pattern (see Figure 4),
tc = 15.38 ns 85 110 mA
CiInput capacitance 3 pF
†All typical values are VCC = 3.3 V, TA = 25°C.
timing requirements
MIN NOM MAX UNIT
tcInput clock period 14.7 tc50 ns
twHigh-level input clock pulse width duration 0.4tc0.6tcns
ttInput signal transition time 5 ns
tsu Data setup time, D0 through D27 before CLKIN↑ (’95) (see Figure 2) 3 ns
thData hold time, D0 through D27 after CLKIN↑ (’95) (see Figure 2) 1.5 ns
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switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
t0Delay time, CLKOUT serial bit position 0 −0.20 0 0.20 ns
t1Delay time, CLKOUT↑ serial bit position 1 1/7tc−0.20 1/7tc+0.20 ns
t2Delay time, CLKOUT↑ serial bit position 2
t = 15.38 ns ( 0.2%),
2/7tc−0.20 2/7tc+0.20 ns
t3Delay time, CLKOUT↑ serial bit position 3 tc = 15.38 ns (±0.2%),
|Input clock jitter| < 50 ps‡,
3/7tc−0.20 3/7tc+0.20 ns
t4Delay time, CLKOUT↑ serial bit position 4
c
|Input clock jitter| < 50 ps‡,
See Figure 5
4/7tc−0.20 4/7tc+0.20 ns
t5Delay time, CLKOUT↑ serial bit position 5
See Figure 5
5/7tc−0.20 5/7tc+0.20 ns
t6Delay time, CLKOUT↑ serial bit position 6 6/7tc−0.20 6/7tc+0.20 ns
tsk(o) Output skew, tn −n/7 tc−0.20 0.20 ns
t7Delay time, CLKIN↑ to CLKOUT↑tc = 15.38 ns (±0.2%),
|Input clock jitter| < 50 ps‡,
See Figure 5 4.2 ns
∆tC(O)
Output clock cycle-to-cycle jitter§
tc = 15.38 ns + 0.75 sin(2π500E3t)
±0.05 ns, See Figure 6 ±80 ps
∆tC(O
)
Output clock cycle-to-cycle jitter§
tc = 15.38 ns + 0.75 sin(2π2E6t)
±0.05 ns, See Figure 6 ±300 ps
twHigh-level output clock pulse duration 4/7 tcns
ttDifferential output voltage transition time (tr or tf)See Figure 3 260 700 1500 ps
ten Enable time, SHTDN↑ to phase lock (Yn valid) See Figure 7 1 ms
tdis Disable time, SHTDN↓ to off-state (CLKOUT low) See Figure 8 250 ns
†All typical values are VCC = 3.3 V, TA = 25°C.
‡|Input clock jitter| is the magnitude of the change in the input clock period.
§The output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.
PARAMETER MEASUREMENT INFORMATION
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
Dn
tsu
CLKIN
th
CLKSEL HIGH
NOTE: All input timing is defined at 1.4 V on an input signal with a 10% to 90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Definition
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PARAMETER MEASUREMENT INFORMATION
0 V
YP
YM VID
49.9 Ω ±1%
(2 Places)
VOC
CL = 10 pF MAX
(2 Places)
VOD(L)
VOD(H)
VOC(PP)
0 V
VOC(SS) VOC(SS)
tftr
100%
80%
20%
0%
NOTE: The lumped instrumentation capacitance for any single ended voltage
measurement is less than or equal to 10 pF. When making measurements
at YP or YM, the complementary output shall be similarly loaded.
Figure 3. Test Load and Voltage Definitions for LVDS Outputs
CLKIN
EVEN Dn
ODD Dn
T
VIH = 2 V and VIL = 0.8 V
Figure 4. Worst-Case‡ Power Test Pattern
‡The worst-case test pattern produces nearly the maximum switching frequency for all of the LV-TTL outputs.
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PARAMETER MEASUREMENT INFORMATION
CLKIN
VOD(H)
0 V
t7
t0
t6
t5
t4
t3
t2
t1
VOD(L)
1.4 V
t7
t0−t6
CLKOUT
Yn
CLKIN CLKOUT
or Xn
Figure 5. Timing Definitions
HP8656B Signal
Generator,
0.1 MHz−990 MHz
RF Output OutputModulation Input CLKOUT
HP8665A Synthesized
Signal Generator,
0.1 MHz−4200 MHz
Device Under
Test
CLKIN Input
DTS2070C
Digital Time
Scope
Device
Under
Test
VCO
Reference
Modulation
v(t) = A sin(2πfmodt)
Σ
+
+
Figure 6. Clock Jitter Test Setup
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PARAMETER MEASUREMENT INFORMATION
CLKIN
Dn
SHTDN
Yn
ten
Invalid Valid
Figure 7. Enable Time Measurement Definition
tdis
CLKIN
SHTDN
CLKOUT
Figure 8. Disable Time Measurement Definition
TYPICAL CHARACTERISTICS
ÁÁ
ÁÁ
ICC
60
40
20
030 40 50 60 70
80
100
f − Frequency − MHz
− Supply Current − mA
WORST-CASE SUPPLY CURRENT
vs
FREQUENCY
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
Figure 9
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APPLICATION INFORMATION
16-bit bus extension
In a 16-bit bus application (Figure 10), TTL data and clock coming from bus transceivers that interface the
backplane bus arrive at the Tx parallel inputs of the LVDS serdestransmitter. The clock associated with the b us
is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. The
data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clock
is also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at the
receiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is then
demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, and
then all are presented to the parallel output port of the receiver.
SN74FB2032 8
D0−D7
8
D8−D15
SN65LVDS95
LVDS
Interface
0 To 10 Meters
(Media Dependent)
TTL
Interface
16-Bit
BTL Bus
Interface
CLK
Backplane
Bus
8D0−D7
8D8−D15
CLK
Backplane
Bus
TTL
Interface
16-Bit
BTL Bus
Interface
XMIT Clock RCV Clock
SN74FB2032
SN65LVDS96
SN74FB2032
SN74FB2032
Figure 10. 16-Bit Bus Extension
16-bit bus extension with parity
In the previous application we did not have a checking bit that would provide assurance that the data crosses
the link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure 11.
The device following the SN74FB2032 is a low cost parity generator. Each transmit-side transceiver/parity
generator takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte,
and then passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter.
Again, the on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at the
input. The synchronized LVDS data/parity and clock arrive at the receiver.
The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the
parity calculations. These devices compare their corresponding input bytes with the value received on the parity
bit. The transceiver/parity generator will assert its parity error output if a mismatch is detected.
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APPLICATION INFORMATION
SN74FB2032 8
D0−D7
8
D8−D15
SN65LVDS95
LVDS
Interface
0 To 10 Meters
(Media Dependent)
TTL
Interface
W/Parity
16-Bit
BTL Bus
Interface
CLK
Backplane
Bus
8D0−D7
8D8−D15
CLK
Backplan
e
Bus
TTL
Interface
16-Bit
BTL Bus
Interface
XMIT Clock RCV Clock
9 Bit Latchable
Transceiver/ With
Parity Generator Parity
Parity
TTL
Interface
Parity
Parity
Parity
Error
TTL
Interface
W/Parity
SN74FB2032 9 Bit Latchable
Transceiver/ With
Parity Generator
SN74FB2032
SN74FB2032
9 Bit Latchable
Transceiver/ With
Parity Generator
9 Bit Latchable
Transceiver/ With
Parity Generator
SN65LVDS96
Figure 11. 16-Bit Bus Extension With Parity
low cost virtual backplane transceiver
Figure 12 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of
a VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem
serialized links.
Depending on the application, the designer will face varying choices when implementing a VBT. In addition to
the devices shown in Figure 12, functions such as parity and delay lines for control signals could be included.
Using additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and
control lines properly.
The designer may choose to implement an independent clock oscillator at each end of the link and then use
a PLL to synchronize LVDS serdes’s parallel I/O to the backplane bus. Resynchronizing FIFOs may also be
required.
Bus
Transceivers LVDS Serdes
Transmitter LVDS Serdes
Receiver Bus
Transceivers
TTL
Inputs
Up To
21 or 28
Bits
LVDS
Serial Links
4 or 5
Pairs
TTL
Outputs
Up To
21 or 28
Bits
Bus
Transceivers LVDS Serdes
Transmitter LVDS Serdes
Receiver Bus
Transceivers
Backplane
Bus Backplane
Bus
Figure 12. Virtual Backplane Transceiver
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVDS95DGGREP ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/04643-01XE ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDS95-EP :
•Catalog: SN65LVDS95
•Automotive: SN65LVDS95-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 23-Sep-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS95DGGREP TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS95DGGREP TSSOP DGG 48 2000 346.0 346.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2009
Pack Materials-Page 2
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