Low Cost CMOS, High Speed,
Rail-to-Rail Amplifiers
ADA4891-1/ADA4891-2
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 All rights reserved.
08054-026
P.O. Box 9106, Norwood, MA 020
©2010 Analog Devices, Inc.
FEATURES
Low cost
High speed and fast settling
−3 dB bandwidth: 240 MHz (G = +1)
Slew rate: 170 V/μs
Settling time to 0.1%: 28 ns
Video specifications (G = +2, RL = 150 Ω)
0.1 dB gain flatness: 25 MHz
Differential gain error: 0.05%
Differential phase error: 0.25°
Single-supply operation
Wide supply range: 2.7 V to 5.5 V
Output swings to within 50 mV of supply rails
Low distortion: 79 dBc SFDR @ 1 MHz
Linear output current: 150 mA @ −50 dBc
Low power of 4.4 mA per amplifier
APPLICATIONS
Imaging
Consumer video
Active filters
Coaxial cable drivers
Clock buffers
Photodiode preamp
Contact image sensor and buffers
CONNECTION DIAGRAMS
A
NC
1
–IN
2
+IN
3
–V
S4
NC
8
+V
S
7
V
OUT
6
NC
5
DA4891-1
NC = NO CONNECT
Figure 1. 8-Lead SOIC (R-8)
0
8054-001
V
OUT 1
+IN
3
–V
S2
+V
S
5
ADA4891-1
–IN
4
Figure 2. 5-Lead SOT-23 (RJ-5)
08054-027
ADA4891-2
OUT1 1
–IN1 2
+IN1 3
–VS4
+VS
8
OUT7
–IN26
+IN25
NC = NO CONNECT
Figure 3. 8-Lead SOIC (R-8) and 8-Lead MSOP (RM-8)
GENERAL DESCRIPTION
The ADA4891-1 (single) and ADA4891-2 (dual) are CMOS, high
speed amplifiers that offer high performance at a low cost. The
amplifiers feature true single-supply capability, with an input
voltage range that extends 300 mV below the negative rail.
In spite of their low cost, the ADA4891 family provides high
performance and versatility. The rail-to-rail output stage enables
the output to swing within 50 mV of each rail, enabling maximum
dynamic range.
The ADA4891 family of amplifiers are ideal for imaging applications,
such as consumer video, CCD buffers, and contact image sensor
buffers. Low distortion and fast settling time also make them
ideal for active filter applications.
The ADA4891-1/ADA4891-2 are available in a wide variety of
packages. The ADA4891-1 is available in 8-lead SOIC and
5-lead SOT-23 packages. The ADA4891-2 is available in 8-lead
SOIC and 8-lead MSOP packages. The amplifiers are specified to
operate over the extended temperature range of −40°C to +125°C.
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
0.1 1k
NORMALIZED CLOSE D -LO OP GAI N (dB)
1 10 100
FREQ U ENC Y ( MHz )
G = +1
R
F
= 0
G = +2
R
F
= 604
G = +5
R
F
= 604
V
S
= +5V
R
L
= 150
V
OUT
= 2V p-p
08054-069
Figure 4. Large Signal Frequency Response vs. Gain, VS = 5 V
ADA4891-1/ADA4891-2
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Applications Information .............................................................. 12
Using the ADA4891 ................................................................... 12
Wideband, Noninverting Operation........................................ 12
Wideband, Inverting Gain Operation ..................................... 12
Recommended Values ............................................................... 12
Effect of RF on 0.1 dB Gain Flatness ........................................ 13
Driving Capacitive Loads .......................................................... 14
Terminating Unused Amplifiers .............................................. 15
Video Reconstruction Filter ...................................................... 15
Layout, Grounding, and Bypassing .............................................. 16
Power Supply Bypassing ............................................................ 16
Grounding ................................................................................... 16
Input and Output Capacitance ................................................. 16
Input-to-Output Coupling ........................................................ 16
Leakage Currents ........................................................................ 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 18
REVISION HISTORY
6/10—Rev. 0 to Rev. A
Changes to Figure 26 ........................................................................ 9
Changes to Figure 33 and Figure 34 ............................................. 10
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
2/10—Revision 0: Initial Version
ADA4891-1/ADA4891-2
Rev. A | Page 3 of 20
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 1 kΩ to 2.5 V, unless otherwise noted.
Table 1.
Parameter Test Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, VO = 0.2 V p-p 240 MHz
G = +2, VO = 0.2 V p-p, RL = 150 Ω to 2.5 V, RF = 604 Ω 90 MHz
Bandwidth for 0.1 dB Flatness G = +2, VO = 2 V p-p, RL = 150 Ω to 2.5 V, RF = 604 Ω 25 MHz
Slew Rate (tR/tF) G = +2, VO = 2 V step 170/210 V/μs
Large Signal Frequency Response G = +2, VO = 2 V p-p, RL = 150 Ω 40 MHz
Settling Time to 0.1% G = +2, VO = 2 V step 28 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD3 fC = 1 MHz, VO = 2 V p-p, G = +1 −79/−93 dBc
Harmonic Distortion, HD2/HD3 fC = 1 MHz, VO = 2 V p-p, G = −1 −75/−91 dBc
Input Voltage Noise f = 1 MHz 10 nV/√Hz
Differential Gain Error (NTSC) G = +2, RL = 150 Ω to 2.5 V 0.05 %
Differential Phase Error (NTSC) G = +2, RL = 150 Ω to 2.5 V 0.25 Degrees
Crosstalk f = 5 MHz, G = +2, VO = 2 V p-p −80 dB
DC PERFORMANCE
Input Offset Voltage ±2.5 ±10 mV
T
MIN to TMAX ±3.2 mV
Offset Drift 6 μV/°C
Input Bias Current −50 +2 +50 pA
Open-Loop Gain 77 83 dB
R
L = 150 Ω to 2.5 V 71 dB
INPUT CHARACTERISTICS
Input Resistance 5
Input Capacitance 3.2 pF
Input Common-Mode Voltage Range −VS − 0.3 to
+VS − 0.8
V
Common-Mode Rejection Ratio (CMRR) VCM = 0 V to 3.0 V 71 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 1 to 2.5 V 0.005 to 4.985 V
R
L = 150 Ω to 2.5 V 0.065 to 4.9 V
Output Current 1% THD with 1 MHz, 2 V p-p output 150 mA
Short-Circuit Current Sourcing 250 mA
Sinking 225 mA
Capacitive Load Drive G = +1, <30% overshoot 15 pF
POWER SUPPLY
Operating Range 2.7 5.5 V
Quiescent Current per Amplifier 4.4 mA
Positive Power Supply Rejection Ratio (PSRR) +VS = 5 V to 5.25 V, −VS = 0 V 65 dB
Negative Power Supply Rejection Ratio (PSRR) +VS = 5 V, −VS = −0.25 V to 0 V 63 dB
OPERATING TEMPERATURE RANGE −40 +125 °C
ADA4891-1/ADA4891-2
Rev. A | Page 4 of 20
TA = 25°C, VS = 3.0 V, RL = 1 kΩ to 1.5 V, unless otherwise noted.
Table 2.
Parameter Test Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, VO = 0.2 V p-p 190 MHz
G = +2, VO = 0.2 V p-p, RL = 150 Ω to 2.5 V, RF = 604 Ω 75 MHz
Bandwidth for 0.1 dB Flatness G = +2, VO = 2 V p-p, RL = 150 Ω to 2.5 V, RF = 604 Ω 18 MHz
Slew Rate (tR/tF) G = +2, VO = 2 V step 140/230 V/μs
Large Signal Frequency Response G = +2, VO = 2 V p-p, RL = 150 Ω 40 MHz
Settling Time to 0.1% G = +2, VO = 2 V step 30 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 1 MHz, VO = 2 V p-p, G = −1 −70/−89 dBc
Input Voltage Noise f = 1 MHz 10 nV/√Hz
Differential Gain Error (NTSC) G = +2, RL = 150 Ω to 0.5 V, +VS = 2 V, −VS = −1 V 0.23 %
Differential Phase Error (NTSC) G = +2, RL = 150 Ω to 0.5 V, + VS = 2 V, −VS = −1 V 0.77 Degrees
Crosstalk f = 5 MHz, G = +2 −80 dB
DC PERFORMANCE
Input Offset Voltage ±2.5 ±10 mV
T
MIN to TMAX ±3.2 mV
Offset Drift 6 μV/°C
Input Bias Current −50 +2 +50 pA
Open-Loop Gain 72 76 dB
R
L = 150 Ω to 1.5 V 65 dB
INPUT CHARACTERISTICS
Input Resistance 5
Input Capacitance 3.2 pF
Input Common-Mode Voltage Range −VS − 0.3 to
+VS − 0.8
V
Common-Mode Rejection Ratio (CMRR) VCM = 0 V to 1.5 V 68 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 1 kΩ to 1.5 V 0.005 to 2.985 V
R
L = 150 Ω to 1.5 V 0.095 to 2.965 V
Output Current 1% THD with 1 MHz, 2 V p-p output 50 mA
Short-Circuit Current Sourcing 150 mA
Sinking 95 mA
Capacitive Load Drive G = +1 15 pF
POWER SUPPLY
Operating Range 2.7 5.5 V
Quiescent Current per Amplifier 3.5 mA
Positive Power Supply Rejection Ratio (PSRR) +VS = 3 V to 3.15 V, −VS = 0 V 76 dB
Negative Power Supply Rejection Ratio (PSRR) +VS = 3 V, −VS = −0.15 V to 0 V 72 dB
OPERATING TEMPERATURE RANGE −40 +125 °C
ADA4891-1/ADA4891-2
Rev. A | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 6 V
Input Voltage (Common Mode) −VS − 0.5 V to +VS
Differential Input Voltage ±VS
Storage Temperature Range (R) −65°C to +125°C
Operating Temperature Range (A Grade) −40°C to +125°C
Lead Temperature (Soldering, 10 sec) 300°C
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. It can be calculated by
PD = (VS × IS) + (VSVOUT) × VOUT/RL (2)
where:
VS is the positive supply rail.
IS is the quiescent current.
VOUT is the output of the amplifier.
RL is the output load of the amplifier.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
To ensure proper operating, it is necessary to observe the
maximum power derating curve in Figure 5, where it is derived
by setting TJ = 150°C in Equation 1. Figure 5 shows the maximum
safe power dissipation in the package vs. the ambient temperature
for the 5-lead SOT-23 (146°C/W), the 8-lead SOIC (115°C/W),
and the 8-Lead MSOP (133°C/W) on a JEDEC standard
4-layer board.
MAXIMUM POWER DISSIPATION
0
0.5
1.0
2.0
1.5
–55 –35 –15 5 25 45 65 85 105 125
AMBIENT TEMPE RAURE ( °C)
MAXIMUM POW ER DISSIP
The maximum power that can be safely dissipated by the
ADA4891-1/ADA4891-2 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit can cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure.
TJ = 150 °C
08054-002
The still-air thermal properties of the package (θJA), the ambient
temperature (TA), and the total power dissipated in the package
(PD) can be used to determine the junction temperature of the die.
The junction temperature can be calculated as
TJ = TA + (PD × θJA) (1)
A
TION (W)
8-LE AD M S OP
8-LEAD SOIC
5-LEAD SOT-23
Figure 5. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
ADA4891-1/ADA4891-2
Rev. A | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
NORMALIZED CLOS E D-LO OP GAIN (d B)
0.1 1 10 100 1000
FRE QUENC Y ( MHz)
V
S
= 5V
V
OUT
= 200mV p-p
R
F
= 604
R
L
= 1k
G = +10 G = +5
G = –1
OR +2 G = +1
08054-028
Figure 6. Small Signal Frequency Response vs. Gain, VS = 5 V
–15
–12
–9
–6
–3
0
3
6
CLOSED-LOOP GAIN (dB)
0.1 1 10 100 1000
FREQUENC Y ( M Hz )
G = +1
V
OUT
= 200mV p-p
R
L
= 1k
V
S
= 2. 7V
V
S
= 5V
08054-029
V
S
= 3V
Figure 7. Small Signal Frequency Response vs. Supply Voltage
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
CLOSED-LOOP GAIN (dB)
0.1 1 10 100 1000
FREQUENC Y (MHz)
V
S
= 5V
G = +1
V
OUT
= 200mV p-p
R
L
= 1k
+125°C
+85°C +25°C
0°C
–40°C
08054-030
CLOSED-LOOP GAIN (dB)
FREQ UE NC Y (MHz )
Figure 8. Small Signal Frequency Response vs. Temperature, VS = 5 V
–12
–9
–6
–3
0
3
6
0.1 1 10 100 1000
+125°C
+85°C +25°C
0°C
–40°C
V
S
= 3V
G = +1
V
OUT
= 200mV p-p
R
L
= 1k
08054-031
Figure 9. Small Signal Frequency Response vs. Temperature, VS = 3 V
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
10.1 10 100
FRE QUENC Y ( MHz)
NO RMAL IZED CLOSED-LOOP GAIN (d B )
V
S
= 3V
V
OUT
= 2V p-p
V
S
= 5V
V
OUT
= 1. 4V p - p
G = +2
R
F
= 604
R
L
= 150
V
S
= 3V
V
OUT
= 1. 4V p-p
08054-019
V
S
= 5V
V
OUT
= 2V p-p
Figure 10. 0.1 dB Gain Flatness vs. Frequency, G = +2
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
10.1 10 100
FREQUENC Y (MHz)
NO RMAL IZED CLOSED-LOOP GAIN (d B )
R
F
= 649
R
F
= 604R
F
= 698
R
F
= 549
V
S
= +5V
G = +2
V
OUT
= 2V p-p
R
L
= 150
08054-020
Figure 11. 0.1 dB Gain Flatness vs. RF, VS = 5 V
ADA4891-1/ADA4891-2
Rev. A | Page 7 of 20
–0.5
NO RMAL IZED CLOSED-LOOP GAIN (d B )
–0.4
–0.3
–0.2
–0.1
0
0.1
10.1 10 100
FREQUENC Y ( M Hz )
08054-021
V
S
= 3V
G = +2
V
OUT
= 2V p-p
R
L
= 150
R
F
= 604
R
F
= 549
R
F
= 649
R
F
= 698
Figure 12. 0.1 dB Gain Flatness vs. RF, VS = 3 V
–10
–9
NORMALIZED CLOSE D -LO OP GAI N (dB)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
0.1 1 10 100 1k
FREQ U ENC Y ( MHz )
V
S
= +5V
R
L
= 150
V
OUT
= 2V p-p
G = +1
R
F
= 0
G = –1
R
F
= 604
G = +2
R
F
= 604
G = +5
R
F
= 604
08054-036
Figure 13. Large Signal Frequency Response vs. Gain, VS = 5 V
–10
–9
0.1 1 10 100 1000
N
FRE QUENC Y ( M Hz )
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
ORMALIZED CLOSED-LOOP GAIN (dB)
G = –1
V
OUT
= 2V p-p
G = +2
V
OUT
= 2V p-p
G = +1
V
OUT
= 1V p-p
G = +5
V
OUT
= 2V p-p
V
S
= 3V
R
F
= 604
R
L
= 150
08054-037
Figure 14. Large Signal Frequency Response vs. Gain, VS = 3 V
–120
–110
–100
–90
–80
–70
–60
–50
40
0.1 1 10
DISTORTION (dBc)
FREQ U ENC Y ( MHz )
V
S
= 5V
R
L
= 1k
V
OUT
= 2V p-p G = +2
SECO ND HARMONIC
G = +1
SECO ND HARMONI C
G = +2
THIRD HARMONIC
G = +1
THIRD HARMONI C
08054-038
Figure 15. Harmonic Distortion (HD2, HD3) vs. Frequency, VS = 5 V
–90
–80
–70
–60
–50
–40
30
0.1 1 10
DISTORTION (dBc)
FREQUENC Y ( M Hz )
V
S
= 3V
R
L
= 1k
V
OUT
= 2V p-p G = +1
THI RD HARM O NIC
G = +1
SECOND HARMONI C
G = +2
SECOND HARMONI C
OUT
IN
+V
S
= 2V
–V
S
= –1V
G = +1 CONFIGURATION
1k
50
G = +2
THI RD HARM O NIC
08054-039
Figure 16. Harmonic Distortion (HD2, HD3) vs. Frequency, VS = 3 V
–120
–110
–100
–90
–80
–70
–60
–50
40
DISTORTION (dBc)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V p-p)
G = +1
THI RD HARM O NIC
V
S
= 5V
R
F
= 604
R
L
= 1k
f
C
= 1MHz
G = –1
THIRD HARMONI C
G = +1
SECO ND HARMONIC
G = –1
SECO ND HARMONIC
0
8054-040
Figure 17. Harmonic Distortion vs. Output Voltage, VS = 5 V
ADA4891-1/ADA4891-2
Rev. A | Page 8 of 20
–120
–110
–100
–90
–80
–70
–60
–50
40
0
0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT VOLTAGE (V p-p)
–4
–3
–2
–1
0
1
2
3
4
5
6
0.1 1 10 100 1k
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
DISTORTION (dBc)
V
S
= 3V
FOR G = 1, R
F
= 604,
f
C
= 1MHz
G = 1
SECOND HARMONIC
G = 1
THIRD HARMONIC
G = +1
THIRD HARMONIC
G = +1
SECOND HARMONIC
OUT
IN
+V
S
= +1.8V
V
S
= 1.2V
1k
50
G = +1
CONFIGURATION
C
L
= 47pF
C
L
= 22pF
08054-041
Figure 18. Harmonic Distortion vs. Output Voltage, VS = 3 V
–100
–90
–80
–70
–60
–50
40
00.51.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V p-p)
DISTO RTION (dBc)
V
S
= 5V
SECO ND HARMONIC
V
S
= 5V
TH I R D HAR M ONI C
V
S
= 3V
SECO ND HARMONIC V
S
= 3V
THIRD HARMONIC
G = +2
R
F
= 604
R
L
= 150
f
C
= 1MHz
08054-042
Figure 19. Harmonic Distortion vs. Output Voltage, G = +2
–180
–162
–10
0
0.001 0.01 0.1 1 10 100 1k
FREQ U ENC Y ( MHz )
–144
–126
–108
–90
–72
–54
–36
–18
0
10
20
30
40
50
60
70
80
90
OPEN-LOOP GAIN (dB)
PHASE ( Deg rees)
V
S
= 5V
R
L
= 1k
08054-043
Figure 20. Open-Loop Gain and Phase vs. Frequency
V
S
= 5V
G = +2
R
L
= 150
V
OUT
= 200mV p-p
C
L
= 0pF
C
L
= 10pF
08054-044
Figure 21. Small Signal Frequency Response vs. CLOAD (CL)
0.06
–0.06
0.04
0.02
0
–0.04
–0.02
0.2
0.1
0
–0.1
–0.2
–0.3
0.3
MO DUL ATING RAMP LEVE L (IRE)
DIFFERENTIAL
GAIN ERROR (%)
DIFFERENTIAL
PHASE ERROR (Deg rees)
V
S
= 5V, G = +2
R
F
= 604, R
L
=150
V
S
= 5V, G = +2
R
F
= 604, R
L
=150
1
ST
2
ND
3
RD
4
TH
5
TH
6
TH
7
TH
8
TH
9
TH
10
TH
1
ST
2
ND
3
RD
4
TH
5
TH
6
TH
7
TH
8
TH
9
TH
10
TH
08054-060
Figure 22. Differential Gain and Phase Errors
1
10
100
1k
VOLTAGE NOISE (nV/Hz)
10 100
FRE QUENC Y (Hz)
1k 10k 100k 1M 10M
V
S
= 5V
G = 1
508054-04
Figure 23. Input Voltage Noise vs. Frequency
ADA4891-1/ADA4891-2
Rev. A | Page 9 of 20
0.01
0.1
1
10
100
0.01 0.1 1 10 100
FREQUENC Y (MHz)
VS = 5V
G = +1
VOUT = 2V p-p
V
S
= 5V
G = +1
RL = 1k
OUTPUT I M P EDANCE ()
6
–100
08054-04
OUTP UT VOLTAGE ( m V)
100
0
Figure 24. Closed-Loop Output Impedance vs. Frequency
G = 1
V
OUT
= 200mV p-p
R
L
= 1k
V
S
= 3V
08054-048
V
S
= 5V
50mV/DIV 5ns/DIV
Figure 25. Small Signal Step Response, G = +1
1
0
1
OUT P UT VO LTAGE (V )
V
S
= 3V
R
L
= 1k
V
S
= 5V
R
L
= 150
V
S
= 3V
R
L
= 150
V
S
= 5V
R
L
= 1k
0
8054-047
0.5V/DIV 10ns/DIV
G = +2
V
OUT
= 2V p-p
R
F
= 604
OUT PUT VOLTAGE (mV)
1
0
–1
RL = 150
08054-049
0.5V/DIV 5ns/DIV
0.5
0
–0.5
OUTPUT VOLTAGE (V)
Figure 26. Large Signal Step Response, G = +2
Figure 27. Large Signal Step Response, VS = 5 V
R
L
= 150
R
L
= 1kV
S
= 3V
G = +1
V
OUT
= 1V p-p
08054-050
5ns/DIV
0.5V/DIV
Figure 28. Large Signal Step Response, VS = 3 V
–0.30 0 25303540 45
–0.20
–0.10
0
0.10
0.20
0.30
SETT LI NG (%)
V
S
=+5V
G=+2
R
F
=604
R
L
=150
V
OUT
=2Vp-p
054-06108
5ns/DIV0.10%/DIV
Figure 29. Short-Term Settling Time to 0.1%
ADA4891-1/ADA4891-2
Rev. A | Page 10 of 20
140
SLEW R
150
160
170
180
190
200
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
A
TE (V/µs)
OUT P UT ST EP AMPLITUDE (V )
RISING E DGE
FALLING EDGE
V
S
= 5V
G = +2
R
L
= 150
08054-051
08054-071
Figure 30. Slew Rate vs. Output Step
–1
0
1
2
3
AMPL ITUDE ( V )
5ns/DIV1V/DIV
INPUT VS = ±2.5V
G = +1
RL = 1k
OUTPUT
Figure 31. Input Overdrive Recovery From Positive Rail
08054-063
–3
OUTPUT
–2
–1
0
1
AMPL I T UDE ( V)
INPUT
V
S
= ±2.5V
G = +1
R
L
= 1k
1V/DIV 5ns/DIV
08054-070
Figure 32. Input Overdrive Recovery from Negative Rail
–3
–2
–1
0
1
2
3
AMPL ITUDE (V)
INPUT
OUTPUT V
S
= ±2.5V
G = –2
R
L
= 1k
1V/DIV 5ns/DIV
08054-052
Figure 33. Output Overdrive Recovery from Positive Rail
–3
–2
–1
0
1
2
3
AMPLIT UDE ( V )
V
S
= ±2.5V
G = –2
R
L
= 1k
OUTPUT
INPUT
1V/DIV 5ns/DIV
Figure 34. Output Overdrive Recovery from Negative Rail
–80
–70
–60
–50
–40
–30
20
CMRR (d B )
0.1 1 10 100
FREQUENCY (MHz)
VS = 5V
308054-05
Figure 35. CMRR vs. Frequency
ADA4891-1/ADA4891-2
Rev. A | Page 11 of 20
–80
–70
–60
–50
–40
–30
–20
10
PSRR (dB)
3.0
3.5
4.0
4.5
5.0
5.5
6.0
–40 –20 0 20 40 60 80 100 120
QUI E S CE NT SUPPLY CURRENT (mA)
0.01 0.1 1 10 100
FREQUENCY (MHz)
+PSRR
–PSRR
Vs = 5V
G = +1
0
8054-054
Figure 36. PSRR vs. Frequency
08054-0
V
S
= 5V
TEMPERATURE (ºC)
08054-057
Figure 39. Supply Current per Amplifier vs. Temperature
72
–100
–90
CROSSTALK ( dB)
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100 1000
FREQUENC Y ( M Hz )
Vs = 5V
G = +2
RL = 1 k
VOUT = 2V p-p
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
2.73.03.33.63.94.24.54.85.1
QUI E S CE NT SUPPLY CURRENT ( mA)
SUPPLY VOLTAGE (V)
08054-058
Figure 37. ADA4891-2 (SOIC) Crosstalk (Output-to-Output) vs. Frequency
Figure 40. Supply Current per Amplifier vs. Supply Voltage
0
0.1
0 102030405060708090100
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
OUTPUT S
A
TUR
A
TION VOLTAGE (V)
V
OH
, +125°C
V
OH
, +25°C
V
OH
, –40 ° C
V
OL
, +125°C
V
OL
, +25°C
V
OL
, –40 ° C
I
LOAD
(mA)
V
S
= 5V
G = –2
R
F
= 604
08054-056
Figure 38. Output Saturation Voltage vs. Load Current vs. Temperature
ADA4891-1/ADA4891-2
Rev. A | Page 12 of 20
08
APPLICATIONS INFORMATION
USING THE ADA4891
Understanding the subtleties of the ADA4891 family gives users
insight into how to exact its peak performance. In this section, how
the gain, component values, and parasitics affect the performance
of the ADA4891 are discussed. The wideband, noninverting
configuration of the ADA4891 is shown in Figure 41, while the
wideband, inverting configuration of the ADA4891 is shown
in Figure 42.
WIDEBAND, NONINVERTING OPERATION
054-023
ADA4891-1
RF
RG
RT
50
S
OURCE
RL
+
V
S
10µF
0.1µF
VIVO
–VS
10µF
0.1µF
Figure 41. Noninverting Configuration
In Figure 41, RF and RG denote the feedback and the gain resistor,
respectively. Together, RF and RG determine the noise gain of the
amplifier, and the value of RF defines the 0.1 dB bandwidth. The
effect of RF on the 0.1 dB gain flatness is discussed in the Effect
of RF on 0.1 dB Gain Flatness section. Typical RF values range
from 549  to 698 .
In a controlled impedance signal path, RT is used as the input
termination resistor designed to match that of the input source
impedance. Note that it is not required for normal operation.
RT is generally set to match the input source impedance.
WIDEBAND, INVERTING GAIN OPERATION
08054-024
ADA4891-1
R
F
R
T
R
G
50
SOURCE
R
L
+
V
S
–V
S
V
I
V
O
10µF
0.1µF
10µF
0.1µF
Figure 42. Inverting Configuration
Figure 42 shows the inverting gain configuration. To match the
input source impedance for the inverting gain configuration, set
the parallel combination of RT//RG to match that of the input
source impedance.
Note that a bias current cancellation resistor is not required in
the noninverting input of the amplifier because the input bias
current of the ADA4891 is very low (less than 10 pA). Therefore,
the dc errors caused by the bias current are negligible.
For both configurations, it is often useful to increase the RF value
to decrease the loading on the output. Increasing the RF value
improves the harmonic distortion at the expense of reducing
the 0.1 dB bandwidth of the amplifier. This effect is discussed
further in the Effect of RF on 0.1 dB Gain Flatness section.
RECOMMENDED VALUES
Table 4 provides a handy reference for various configurations
and shows the effect of gain on the −3 dB small signal bandwidth,
slew rate, and peaking of the ADA4891-1/ADA4891-2. Note
that as the gain increases, the small signal bandwidth decreases
as is expected from the gain bandwidth product relationship. In
addition, the phase margin improves with higher gains, and the
amplifier becomes more stable. As a result, the peaking in the
frequency response is reduced (see Figure 6).
Table 4. Recommended Values for the ADA4891-1/ADA4891-2 Performance
Feedback Network Values −3 dB Small Signal Bandwidth (MHz) Slew Rate (V/μs)
Peaking (dB)
Gain RF R
G V
OUT = 200 mV p-p tR t
F
−1 604 604 118 188 192 1.3
+1 0 0 236 154 263 2.6
+2 604 604 120 178 204 1.4
+5 604 151 32.5 149 154 0
+10 604 67.1 12.7 71 72 0
ADA4891-1/ADA4891-2
Rev. A | Page 13 of 20
EFFECT OF RF ON 0.1 dB GAIN FLATNESS
Gain flatness is an important specification in video applications.
It represents the maximum allowable deviation in the signal
amplitude within the pass band. Tests have revealed that the
human eye is unable to distinguish brightness variations of
less than 1%, which translates into a 0.1 dB signal drop within
the pass band, or put simply, 0.1 dB gain flatness.
The PCB layout configuration and bond pads of the chip often
contribute to stray capacitance. The stray capacitance at the
inverting input forms a pole with the feedback and gain resistor.
This additional pole adds phase shift and reduces phase margin
in the closed-loop phase response, causing instability in the
amplifier and peaking in the frequency response.
Figure 43 shows the effect of using various values of Feedback
Resistor RF on the 0.1 dB gain flatness. Note that a larger RF value
causes more peaking because the additional pole formed by RF,
and the input stray capacitance, shifts down in frequency and
interacts significantly with the internal poles of the amplifier.
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
10.1 10 100
NORMALIZED G AIN (d B)
FREQUENC Y (MHz)
V
S
= +5V
G = +2
V
OUT
= 2V p-p
R
L
= 150
R
G
= R
F
= 604
R
G
= R
F
= 549
R
G
= R
F
= 649
R
G
= R
F
= 698
4-0220805
Figure 43. Noninverting Configuration
To get the desired 0.1 dB bandwidth, adjust the feedback
resistor, RF, as shown in Figure 43. If RF cannot be adjusted, a
small capacitor can be placed in parallel with RF to reduce
peaking.
The feedback capacitor, CF, forms a zero with the feedback resistor,
which cancels out the pole formed by the input stray capacitance
and the gain and feedback resistor. For a first pass in determining
the CF value, use the equation RG × CS = RF × CF, where RG is the
gain resistor, CS is the input stray capacitance, RF is the feedback
resistor, and CF is the feedback capacitor. This is the condition
where the original closed-loop frequency response of the amplifier
is restored as if there is no stray input capacitance. Most often,
however, the value of CF is determined empirically.
Figure 44 shows the effect of using various values for the feedback
capacitors to reduce peaking. In this case, RF = RG = 604 . The
input stray capacitance, together with the board parasitics, is
approximately 2 pF.
0.3
0.2
0.1
0
0.1
0.2
0.1 1 10 100
NORMALI Z ED CLOSED- LOOP GAIN (dB)
FRE QUENC Y (MHz)
C
F
= 3.3pF
C
F
= 0pF
C
F
= 1pF
V
S
= 5V
G = 2
R
F
= 604
R
L
= 150
V
OUT
= 2V p-p
08054-025
Figure 44. 0.1 dB Gain Flatness vs. CF, VS = 5 V
ADA4891-1/ADA4891-2
Rev. A | Page 14 of 20
DRIVING CAPACITIVE LOADS
A highly capacitive load reacts with the output impedance of
the amplifiers, causing a loss of phase margin and subsequent
peaking or even oscillation, as is shown in Figure 45 and
Figure 46. Four methods that minimize the output capacitive
loading effect include:
Reducing the output resistive load. This pushes the pole
further away and, hence, improves the phase margin.
Increase the phase margin with higher noise gains. As
the closed-loop gain is increased, the larger phase margin
allows for large capacitor loads with less peaking.
Adding a parallel capacitor, CF with RF, from −IN to the
output. This adds a zero in the closed-loop frequency
response, which tends to cancel out the pole formed by
the capacitive load and output impedance of the amplifier.
Refer to the Effect of RF on 0.1 dB Gain Flatness section for
more details.
Putting a small value resistor, RS, in series with the output
to isolate the load capacitor from the output stage of
the amplifier.
–10
–8
–6
–4
–2
0
2
4
6
8
MAG NI T UDE (d B)
0.1 1 10 100
FRE QUENC Y ( MHz)
V
S
= 5V
V
OUT
= 200mV p-p
G = +1
R
L
= 1k
C
L
= 6.8pF
08054-032
Figure 45. Closed-Loop Frequency Response, CL = 6.8 pF
OUT PUT VOLTAGE (mV)
50ns/DIV50mV/DIV
V
S
= 5V
G = +1
R
L
= 1k
C
L
= 6. 8pF
C1
0
100
–100
08054-034
Figure 46. 200 mV Step Response, CL = 6.8 pF
Figure 47 shows the effect of using a snub resistor (RS) on reducing
the peaking in the worst-case frequency response (gain of +1).
Using RS = 100 Ω reduces the peaking by 3 dB, with the tradeoff
that the closed-loop gain is reduced by 0.9 dB due to attenuation at
the output. RS can be adjusted from 0 Ω to 100 Ω to maintain an
acceptable level of peaking and closed-loop gain, as shown in
Figure 48.
Figure 48 shows that the transient response is also much improved
by the snub resistor RS = 100 Ω, compared to that of Figure 46.
–10
–8
–6
–4
–2
0
2
4
6
8
0.1 1 10 100
FREQ UE NC Y (MHz )
V
S
= 5V
V
OUT
= 200mV p-p
G = +1
R
L
= 1k
C
L
= 6. 8pF
MAGNITUDE ( dB)
R
S
= 0
R
S
= 100
50
R
L
R
S
C
L
V
OUT
V
IN
200mV
STEP
08054-033
Figure 47. Capacitive Load Drive vs. Closed-Loop Gain
V
S
= 5V
G = +1
R
L
= 1k
C
L
= 6.8pF
R
S
= 100
C1
08054-035
50ns/DIV50mV/DIV
OUTPUT VOLTAGE (mV)
0
100
–100
Figure 48. 200 mV Step Response, CL = 50 pF
ADA4891-1/ADA4891-2
Rev. A | Page 15 of 20
08054-064
TERMINATING UNUSED AMPLIFIERS An example of a 15 MHz, 3-pole Sallen-Key, low-pass, video
reconstruction filter is shown in Figure 51. This circuit features
a gain of 2, has a 0.1 dB bandwidth of 7.3 MHz, and over 17 dB
attenuation at 29.7 MHz (see Figure 52). The filter has three poles;
two are active with a third passive pole (R6 and C4) placed at
the output. C3 improves the filter roll-off. R6, R7, and R8 comprise
the video load of 150 Ω. Components R6, C4, R7, R8, and the
input termination of the network analyzer form a 6 dB attenuator;
therefore, the reference level is roughly 0 dB, as shown in Figure 52.
Terminating unused amplifiers in a multiamplifier package is an
important step to ensuring proper operation of the functional
amplifier. Unterminated amplifiers can oscillate and draw excessive
power if left unattended. The recommended procedure for
terminating unused amplifiers is to connect any unused amplifiers
in a unity-gain configuration and connect the noninverting input
to midsupply voltage. With symmetrical bipolar power supplies,
this means connecting the noninverting input to ground, as shown
in Figure 49. In single power supply applications, a synthetic
midsupply source must be created. This can be accomplished
with a simple resistive voltage divider. Figure 50 shows the
proper connection for terminating an unused amplifier in a
single-supply configuration.
C2
51pF
–V
S
+
V
S
ADA4891-2
Figure 49. Terminating Unused Amplifier with
Symmetrical Bipolar Power Supplies
08054-065
2
.5k
2
.5k
+
V
S
ADA4891-2
Figure 50. Terminating Unused Amplifier with Single Power Supply
VIDEO RECONSTRUCTION FILTER
A common application for active filters is at the output of video
digital-to-analog converters (DACs)/encoders. The filter, or more
appropriately, the video reconstruction filter, is used at the output
of a video DAC/encoder to eliminate the multiple images that
are created during the sampling process within the DAC. For
portable video applications, the ADA4891 is an ideal choice
due to its lower power requirements and high performance.
For active filters, a good rule of thumb is that the amplifiers
−3 dB bandwidth be at least 10 times higher than the corner
frequency of the filter. This ensures that no initial roll-off is
introduced by the amplifier and that the pass band is flat until
the cutoff frequency.
R2
47
IN
R3
125R6
6.8
+5V R7
68.1
R1 C1
51pF
C3
15pF
C4
1nF
R4
1k
R5
1k
R8
75
V
OUT
0
8054-062
Figure 51. 13 MHz Video Reconstruction Filter Schematic
–39
–36
–33
–30
–27
–24
–21
–18
–15
–12
–9
–6
–3
0
0.03 0.1 1 10 100
MAGNITUDE (dB)
FREQ UE NCY (M Hz)
8054-059
0
Figure 52. Video Reconstruction Filter Frequency Performance
ADA4891-1/ADA4891-2
Rev. A | Page 16 of 20
LAYOUT, GROUNDING, AND BYPASSING
POWER SUPPLY BYPASSING
Power supply pins are additional op amp inputs, and care must be
taken so that a noise-free stable dc voltage is applied. The purpose
of bypass capacitors is to create a low impedance path from the
supply to ground over a range of frequencies, thereby shunting
or filtering the majority of the noise to ground. Bypassing is
also critical for stability, frequency response, distortion, and PSRR
performance.
Chip capacitors of 0.1 µF (X7R or NPO) are critical and should
be as close as possible to the amplifier package. The 0508 case
size for such a capacitor is recommended because it offers low
series inductance and excellent high frequency performance.
Larger chip capacitors, such as 0.1 µF capacitors, can be shared
among a few closely spaced active components in the same
signal path. A 10 µF tantalum capacitor is less critical for high
frequency bypassing, but does provide additional bypassing for
lower frequencies.
GROUNDING
When possible, ground and power planes should be used. Ground
and power planes reduce the resistance and inductance of the
power supply feeds and ground returns. If multiple planes are
used, they should be stitched together with multiple vias. The
returns for the input, output terminations, bypass capacitors,
and RG should all be kept as close to the ADA4891 as possible.
Ground vias should be placed at the very end of the component
mounting pads to provide a solid ground return. The output load
ground and the bypass capacitor grounds should be returned
to a common point on the ground plane to minimize parasitic
inductance that can help improve distortion performance.
INPUT AND OUTPUT CAPACITANCE
Parasitic capacitance can cause peaking and instability and,
therefore, should be minimized to ensure stable operation.
High speed amplifiers are sensitive to parasitic capacitance between
the inputs and ground. A few picofarads of capacitance reduces
the input impedance at high frequencies, in turn increasing the
gain of the amplifier and causing peaking of the frequency
response or even oscillations, if severe enough. It is recommended
that the external passive components, which are connected to
the input pins, be placed as close as possible to the inputs to
avoid parasitic capacitance.
In addition, all ground and power planes under the pins of
the ADA4891 should be cleared of copper to prevent parasitic
capacitance between the input and output pins to ground. This is
because a single mounting pad on a SOIC footprint can add as
much as 0.2 pF of capacitance to ground if the ground or power
plane is not cleared under the ADA4891 pins. In fact, the ground
and power planes should be kept at a distance of at least 0.05 mm
from the input pins on all layers of the board.
INPUT-TO-OUTPUT COUPLING
To minimize capacitive coupling between the inputs and output
and to avoid any positive feedback, the input and output signal
traces should not be parallel. In addition, the input traces should
not be close to each other. A minimum of 7 mils between the
two inputs is recommended.
LEAKAGE CURRENTS
In extremely low input bias current amplifier applications, stray
leakage current paths must be kept to a minimum. Any voltage
differential between the amplifier inputs and nearby traces sets
up a leakage path through the PCB. Consider a 1 V signal and
100 GΩ to ground present at the input of the amplifier. The
resultant leakage current is 10 pA; this is 5× the typical input
bias current of the amplifier. Poor PCB layout, contamination,
and the board material can create large leakage currents. Common
contaminants on boards are skin oils, moisture, solder flux, and
cleaning agents. Therefore, it is imperative that the board be
thoroughly cleaned and the board surface be free of contaminants
to take full advantage of the low input bias currents of the ADA4891.
To significantly reduce leakage paths, a guard-ring/shield should be
used around the inputs. The guard-ring circles the input pins
and is driven to the same potential as the input signal, thereby
reducing the potential difference between pins. For the guard
ring to be completely effective, it must be driven by a relatively
low impedance source and should completely surround the
input leads on all sides, above, and below, using a multilayer
board (see Figure 53). The SOT-23-5 package presents a challenge
in keeping the leakage paths to a minimum. The pin spacing is
very tight, so extra care must be used when constructing the guard
ring (see Figure 54 for recommended guard-ring construction).
NONINVERTING
GUARD RING
INVERTING
GUARD RING
0
8054-067
Figure 53. Guard-Ring Configurations
+V
08054-068
–IN
+IN
–V
V
OUT
+V
–IN
+IN
–V
V
OUT
ADA4891
ADA4891
NONINVERTING
INVERTING
Figure 54. Guard-Ring Layout SOT-23-5
ADA4891-1/ADA4891-2
Rev. A | Page 17 of 20
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMP LI ANT TO JEDEC S TANDARDS MO-178-AA
121608-A
10°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.20
BSC
5
123
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
Figure 56. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ADA4891-1/ADA4891-2
Rev. A | Page 18 of 20
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
0.40
0.80
0.55
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
0.23
COPLANARITY
0.10
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 57. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
ADA4891-1ARZ −40°C to +125°C 8-Lead SOIC_N R-8
ADA4891-1ARZ-RL −40°C to +125°C 8-Lead SOIC_N, 13” Tape and Reel R-8
ADA4891-1ARZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7” Tape and Reel R-8
ADA4891-1ARJZ-R7 −40°C to +125°C 5-Lead SOT-23, 7” Tape and Reel RJ-5 H1W
ADA4891-1ARJZ-RL −40°C to +125°C 5-Lead SOT-23, 13” Tape and Reel RJ-5 H1W
ADA4891-2ARZ −40°C to +125°C 8-Lead SOIC_N R-8
ADA4891-2ARZ-RL −40°C to +125°C 8-Lead SOIC_N, 13” Tape and Reel R-8
ADA4891-2ARZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7” Tape and Reel R-8
ADA4891-2ARMZ −40°C to +125°C 8-Lead MSOP RM-8 H1U
ADA4891-2ARMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 H1U
ADA4891-2ARMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 H1U
1 Z = RoHS Compliant Part.
ADA4891-1/ADA4891-2
Rev. A | Page 19 of 20
NOTES
ADA4891-1/ADA4891-2
Rev. A | Page 20 of 20
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08054-0-6/10(A)