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April 2016
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
FAN23SV20MAMPX
20 A Synchronous Buck Regulator
Features
VIN Range: 7 V to 18 V Using Internal Linear
Regulator for Bias
VIN Range: 4.5 V to 5.5 V with VIN/PVIN/PVCC
Connected to Bypass Internal Regulator
High Efficiency: Over 96% Peak
Continuous Output Current: 20 A
Internal Linear Bias Regulator
Accurate Enable facilitates VIN UVLO Functionality
PFM Mode for Light-Load Efficiency
Excellent Line and Load Transient Response
Precision Reference: ±1% Over-Temperature
Output Voltage Range: 0.6 to 5.5 V
Programmable Frequency: 200 kHz to 1 MHz
Programmable Soft-Start
Low Shutdown Current
Adjustable Sourcing Current Limit
Internal Boot Diode
Thermal Shutdown
Halogen and Lead Free, RoHS Compliant
Applications
Servers and Desktop Computers
NVDC Notebooks, Netbooks
Game Consoles
Telecommunications
Storage
Description
The FAN23SV20MA is a highly efficient synchronous
buck regulator. The regulator is capable of operating
with an input range from 7 V to 18 V and supporting up
to 20 A load currents. The device can operate from a
5 V rail (±10%) if VIN, PVIN, and PVCC are connected
together to bypass the internal linear regulator.
The FAN23SV20MA utilizes Fairchild’s constant on-time
control architecture to provide excellent transient
response and to maintain a relatively constant switching
frequency. The device utilizes Pulse Frequency
Modulation (PFM) mode to maximize light-load
efficiency by reducing switching frequency when the
inductor is operating in discontinuous conduction mode
at light loads.
Switching frequency and over-current protection can
be programmed to provide a flexible solution for
various applications. Output over-voltage, under-
voltage, over-current, and thermal shutdown protections
help prevent damage to the device during fault
conditions. After thermal shutdown is activated, a
hysteresis feature restarts the device when normal
operating temperature is reached.
Ordering Information
Part Number
Configuration
Operating
Temperature Range
Output
Current (A)
Package
FAN23SV20MAMPX
PFM, No Ultrasonic
Mode
-40 to 125°C
20
34-Lead, PQFN,
5.5 mm x 5.0 mm
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 2
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Typical Application Diagram
Figure 1. Typical Application with VIN = 12 V
R2
1.5kΩ
C4
0.1µF
C5
100pF
L1
0.47µH
R5 1.9kΩ
C10
2.2µF
C9
0.1µF
R11
10Ω
R9
54.9kΩ
C3
0.1µF
CIN
6x10µF
R3
10kΩ
COUT
6x100µF
VIN = 5V
VOUT = 1.2V
IOUT=0-20A
C7
15nF
R4
10kΩ
PVIN
PGND
SW
PVCC
VCC
EN
ILIM
AGND
FREQ
BOOT
SOFT START
FB
VIN
CIN
0.1µF
FAN23SV20MA
Ext
EN
PGOOD
R6
4.99kΩ
Figure 2. Typical Application with VIN=5 V
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 3
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Functional Block Diagram
Control
Logic
PVCC
PVCC
VCC
Modulator
VCC
Thermal
Shutdown
2nd Level OVP
Comparator
1st Level OVP
Comparator
Under-Voltage
Comparator
FB
Comparator
Current Limit
Comparator
PFM
Comparator
HS Gate
Driver
LS Gate
Driver
VREF
x1.2
x1.1
x0.9
VCC
Linear
Regulator
VCC UVLO
PVCC
SW
PGNDILIM
PGOOD
FREQ
FB
SS
VCC
PVCC
VIN BOOT PVIN
AGND
VCC
EN ENABLE
10µA
10µA
1.26V/1.14V
Figure 3. Block Diagram
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 4
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Pin Configuration
9
34
17
26 18
27
10
8
72 3 6
5
4
16
15
14
13
12
11
192021
22232425
33
28
29
30
31
32
PGND
PGND
PGND
PGND
PVIN
PVIN
SW
SW
SW
SW
SW
SW
AGND
SW
VCC
PVCC
ILIM
FB
NC
NC
NC
SS
EN
FREQ
PGOOD
PVIN
PVIN
PVIN
PVIN
PVIN
AGND
BOOT
SW
VIN
AGND
(P1)
PVIN
(P2)
SW
(P3)
1
PVIN
AGND
PVIN
PVIN
PVIN
PVIN
PVIN
SW
SW
SW
SW
SW
SW
PGND
PGND
PGND
PGND
SW
VCC
PVCC
ILIM
FB
NC
NC
NC
SS
EN
FREQ
PGOOD
AGND
BOOT
SW
VIN
PVIN
1
9
10
27
26
18
17
34
2
38 7 4
5
6
28
29
30
31
32
33
19 20 21 22 23 24 25
11
16
15
14
13
12
Figure 4. Pin Assignments, Bottom View
Figure 5. Pin Assignments, Top View
Pin Definitions
Name
Pad / Pin
Description
PVIN
P2, 5-11
Power input for the power stage
VIN
1
Power input to the linear regulator; used in the modulator for input voltage feed-forward
PVCC
25
Power output of the linear regulator; directly supplies power for the low-side gate driver
and boot diode. Can be connected to VIN and PVIN for operation from 5 V rail.
VCC
26
Power supply input for the controller
PGND
18-21
Power ground for the low-side power MOSFET and for the low-side gate driver
AGND
P1, 4, 23
Analog ground for the analog portions of the IC and for substrate
SW
P3, 2, 12-17, 22
Switching node; junction between high-and low-side MOSFETs
BOOT
3
Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the
charge to turn on the N-channel high-side MOSFET. During the freewheeling interval
(low-side MOSFET on), the high-side capacitor is recharged by an internal diode
connected to PVCC.
ILIM
24
Current limit. A resistor between ILIM and SW sets the current limit threshold.
FB
27
Output voltage feedback to the modulator
EN
29
Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable.
SS
31
Soft-start input to the modulator
FREQ
32
On-time and frequency programming pin. Connect a resistor between FREQ and
AGND to program on-time and switching frequency.
PGOOD
30
Power good; open-drain output indicating VOUT is within set limits.
NC
28, 33-34
Leave pin open or connect to AGND.
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 5
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Conditions
Min.
Max.
Unit
VPVIN
Power Input
Referenced to PGND
-0.3
25.0
V
VIN
Modulator Input
Referenced to AGND
-0.3
25.0
V
VBOOT
Boot Voltage
Referenced to PVCC
-0.3
26.0
V
Referenced to PVCC, <20 ns
-0.3
30.0
V
VSW
SW Voltage to GND
Referenced to PGND, AGND
-1
25
V
Referenced to PGND, AGND < 20 ns
-5
25
V
VBOOT
Boot to SW Voltage
Referenced to SW
-0.3
6.0
V
Boot to PGND
Referenced to PGND
-0.3
30
V
VPVCC
Gate Drive Supply Input
Referenced to PGND, AGND
-0.3
6.0
V
VVCC
Controller Supply Input
Referenced to PGND, AGND
-0.3
6.0
V
VILIM
Current Limit Input
Referenced to AGND
-0.3
6.0
V
VFB
Output Voltage Feedback
Referenced to AGND
-0.3
6.0
V
VEN
Enable Input
Referenced to AGND
-0.3
6.0
V
VSS
Soft Start Input
Referenced to AGND
-0.3
6.0
V
VFREQ
Frequency Input
Referenced to AGND
-0.3
6.0
V
VPGOOD
Power Good Output
Referenced to AGND
-0.3
6.0
V
ESD
Electrostatic Discharge
Human Body Model, JESD22-A114
1000
V
Charged Device Model, JESD22-C101
2500
V
TJ
Junction Temperature
+150
°C
TSTG
Storage Temperature
-55
+150
°C
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Conditions
Typ.
Max.
Unit
VPVIN
Power Input
Referenced to PGND
7
18
V
VIN
Modulator Input
Referenced to AGND
7
18
V
TJ
Junction Temperature
-40
+125
°C
ILOAD
Load Current
TA=25°C, No Airflow
20
A
VPVIN, VIN,
VPVCC
PVIN, VIN, and Gate Drive
Supply Input
VPVIN, VIN, VPVCC Connected for 5 V rail
operation and Referenced to PGND, AGND
4.5
5.5
V
Thermal Characteristics
The thermal characteristics were evaluated on a 6-layer pcb structure (2 oz/2 oz/2 oz/2 oz) measuring 7 cm x 7 cm).
Symbol
Parameter
Typ.
Unit
JA
Thermal Resistance, Junction-to-Ambient
22.7
°C/W
ψJC
Thermal Characterization Parameter, Junction-to-Top of Case
12.6
°C/W
ψJPCB
Thermal Characterization Parameter, Junction-to-PCB
1.7
°C/W
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 6
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Electrical Characteristics
Unless otherwise noted; VIN=12 V, VOUT=1.2 V, and TA = TJ = -40 to +125°C.(1)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Supply Current
IVIN,SD
Shutdown Current
EN=0 V
16
µA
IVIN,Q
Quiescent Current
EN=5 V, Not Switching
1.8
mA
IVIN,GateCharge
Gate Charge Current
EN=5 V, fSW=500 kHz
22
mA
Linear Regulator
VREG
Regulator Output Voltage
4.75
5.05
5.25
V
IREG
Regulator Current Limit
60
mA
Reference, Feedback Comparator
VFB
FB Voltage Trip Point
590
596
602
mV
IFB
FB Pin Bias Current
-100
0
100
nA
Modulator
tON
On-Time Accuracy
-20
20
%
tOFF,MIN
Minimum SW Off-Time
320
374
ns
DMIN
Minimum Duty Cycle
FB=1 V
0
%
Soft-Start
ISS
Soft-Start Current
SS=0.5 V
7
10
13
µA
tON,SSMOD
SS On-Time Modulation
SS<0.6 V
25
100
%
VSSCLAMP,NOM
Nominal Soft-Start Voltage Clamp
VFB=0.6 V
400
mV
VSSCLAMP,OVL
Soft-Start Voltage Clamp in Overload
Condition
VFB=0.3 V, OC Condition
40
mV
PFM Zero-Crossing Detection Comparator
VOFF
ZCD Offset Voltage
TA=TJ=25°C
-6
0
mV
Current Limit
ILIM
Valley Current Limit Accuracy
TA=TJ=25°C, IVALLEY=24 A
-10
10
%
KILIM
ILIM Set-Point Scale Factor
80
ILIMTC
Temperature Coefficient
4000
ppm/°C

© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 7
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Electrical Characteristics (Continued)
Unless otherwise noted; VIN=12 V, VOUT=1.2 V, and TA=TJ=25°C.(1)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Enable
VTH+
Rising Threshold
1.11
1.26
1.43
V
VHYST
Hysteresis
122
mV
VTH-
Falling Threshold
1.00
1.14
1.28
V
VENCLAMP
Enable Voltage Clamp
IEN=20 µA
4.3
4.5
V
IENCLAMP
Clamp Current
24
µA
IENLK
Enable Pin Leakage
EN=1.2 V
100
nA
IENLK
Enable Pin Leakage
EN=5 V
76
µA
UVLO
VON
VCC Good Threshold Rising
4.4
V
VHYS
Hysteresis Voltage
160
mV
Fault Protection
VUVP
PGOOD UV Trip Point
On FB Falling
86
89
92
%
VVOP1
PGOOD OV Trip Point
On FB Rising
108
111
115
%
VOVP2
Second OV Trip Point
On FB Rising; LS=On
118
122
125
%
RPGOOD
PGOOD Pull-Down Resistance
IPGOOD=2 mA
125
Ω
tPG,SSDELAY
PGOOD Soft-Start Delay
0.82
1.42
2.03
ms
IPG,LEAK
PGOOD Leakage Current
1
µA
Thermal Shutdown
TOFF
Thermal Shutdown Trip Point(2)
155
°C
THYS
Hysteresis(2)
15
°C
Internal Bootstrap Diode
VFBOOT
Forward Voltage
IF=10 mA
0.6
V
IR
Reverse Leakage
VR=5 V
1000
µA
Notes:
1. Device is 100% production tested at TA=25°C. Limits over that temperature are guaranteed by design.
2. Guaranteed by design; not production tested.
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 8
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, TA=25°C, and no airflow; unless otherwise
specified.
Figure 6. Efficiency vs. Load Current with VIN=12 V
and fSW=500 kHz
Figure 7. Efficiency vs. Load Current with VIN=12 V
and fSW=300 kHz
Figure 8. Case Top Temperature vs. Load Current
with VIN=12 V and fSW=500 kHz
Figure 9. Case Top Temperature vs. Load Current
with VIN=12 V and fSW=300 kHz
Figure 10. Load Regulation with VIN=12 V, VOUT=1.2 V
and fSW=500 kHz
Figure 11. Line Regulation with VIN=12 V, VOUT=1.2 V
and fSW=500 kHz
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 9
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, TA=25°C, and no airflow; unless otherwise
specified.
Figure 12. Startup Waveforms with 0 A Load Current
Figure 13. Startup Waveforms with 20 A Load Current
Figure 14. Shutdown Waveforms with 20 A Load
Current
Figure 15. Startup Waveforms with Prebias Voltage on
Output
Figure 16. Static Load Ripple at No Load
Figure 17. Static Load Ripple at Full Load
EN (5V/div)
Soft Start (0.5V/div)
Vout (1V/div)
PGOOD (5V/div)
Vin=12V
Iout=0A
Time (500µs/div)
EN (5V/div)
Soft Start (0.5V/div)
Vout (1V/div)
PGOOD (5V/div)
Vin=12V
Iout=0A
Vout Prebias
Time (500µs/div)
Vout
(
20
mV
/
div
)
VSW
(
5
V
/
div
)
Vin
=
12
V
Time
(
10
m
s
/
div
)
EN(5V/div)
Soft Start (0.5V/div)
Vout (0.5V/div)
PGOOD (5V/div)
Vin
=
12
V
Iout
=
20
A
Time
(
500
µs
/
div
)
Vout
(
20
mV
/
div
)
VSW
(
10
V
/
div
)
Vin
=
12
V
Iout
=
20
A
Time
(
1
µs
/
div
)
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 10
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, TA=25°C, and no airflow; unless otherwise
specified.
Figure 18. Operation as Load Changes from 0 A to 2 A
Figure 19. Operation as Load Changes from
2 A to 0 A
Figure 20. Load Transient from 0% to 50% Load
Current
Figure 21. Load Transient from 50% to 100% Load
Current
Figure 22. Over-Current Protection with Heavy Load
Applied
Figure 23. Over-Voltage Protection Level 1 and Level 2
Vout (20mV/div)
Iout (2A/div)
Vin=12V
Vout=1.2V
Time (100µs/div)
Time (100µs/div)
PGOOD (5V/div)
Vout (1V/div)
Soft Start (1V/div)
IL (10A/div) Iout=0A then short output
PGOOD indicates UVP
With Vout falling in OCP
Vout
(
20
mV
/
div
)
Iout
(
2
A
/
div
)
Vin
=
12
V
Vout
=
1
.
2
V
Time
(
100
µs
/
div
)
Vin = 12V, Vout = 1.2V
Iout from 0A to 10A, 3.3A/µs
Time (100µs/div)
IL (5A/div)
Vout (200mV/div)
Vout (200mV/div)
Vin = 12V, Vout = 1.2V
Iout from 10A to 20A, 3.3A/µs
IL (5A/div)
Time (100µs/div)
Vout (1V/div)
Vfb (0.5V/div)
PGOOD (5V/div)
Vsw (10V/div)
Level 1
Level 2
Pull Vout to 3.8V
through 3Ω resistor
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 11
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Circuit Operation
The FAN23SV20MA uses a constant on-time
modulation architecture with a VIN feed-forward input to
accommodate a wide VIN range. This method provides
fixed switching frequency (fSW) operation when the
inductor operates in Continuous Conduction Mode
(CCM) and variable frequency when operating in Pulse
Frequency Mode (PFM) at light loads. Additional
benefits include excellent line and load transient
response, cycle-by-cycle current limiting, and no loop
compensation is required.
At the beginning of each cycle, FAN23SV20MA turns on
the high-side MOSFET (HS) for a fixed duration (tON). At
the end of tON, HS turns off for a duration (tOFF)
determined by the operating conditions. Once the FB
voltage (VFB) falls below the reference voltage (VREF), a
new switching cycle begins.
The modulator provides a minimum off-time (tOFF-MIN) of
320 ns to provide a guaranteed interval for low-side
MOSFET (LS) current sensing and PFM operation. tOFF-
MIN is also used to provide stability against multiple
pulsing and limits maximum switching frequency during
transient events.
Enable
The enable pin can be driven with an external logic
signal, connected to a resistive divider from PVIN/Vin to
ground to create an Under-Voltage Lockout (UVLO)
based on the PVIN/VIN supply, or connected to
PVIN/VIN through a single resistor to auto-enable while
operating within the EN pin internal clamp current sink
capability.
The EN pin can be directly driven by logic voltages of
5 V, 3.3 V, 2.5 V, etc. If the EN pin is driven by 5 V logic,
a small current flows into the pin when the EN pin
voltage exceeds the internal clamp voltage of 4.3 V. To
eliminate clamp current flowing into the EN pin use a
voltage divider to limit the EN pin voltage to < 4 V.
To implement the UVLO function based on PVIN/VIN
voltage level, select values for R7 and R8 in Figure 1
such that the tap point reaches 1.26 V when VIN reaches
the desired startup level using the following equation:
󰇧
 󰇨
(1)
where VIN,on is the input voltage for startup and VEN,on
is the EN pin rising threshold of 1.26 V. With R8
selected as 10 kΩ, and VIN,on=9 V the value of R7 is
61.9 kΩ.
The EN pin can be pulled high with a single resistor
connected from VIN to the EN pin. With VIN > 5.5 V a
series resistor is required to limit the current flow into
the EN pin clamp to less than 24 µA to keep the internal
clamp within normal operating range. The resistor value
can be calculated from the following equation:
  

(2)
Constant On-Time Modulation
The FAN23SV20MA uses a constant on-time
modulation technique, in which the HS MOSFET is
turned on for a fixed time, set by the modulator, in
response to the input voltage and the frequency setting
resistor. This on-time is proportional to the desired
output voltage, divided by the input voltage. With this
proportionality, the frequency is essentially constant
over the load range where inductor current is
continuous.
For buck converter in Continuous-Conduction Mode
(CCM), the switching frequency fSW is expressed as:
 
 
(3)
The on-time generator sets the on-time (tON) for the
high-side MOSFET, which results in the switching
frequency of the regulator during steady-state operation.
To maintain a relatively constant switching frequency
over a wide range of input conditions, the input voltage
information is fed into the on-time generator.
tON is determined by:
 
 
(4)
where ItON is:



(5)
where RFREQ is the frequency-setting resistor
described in the Setting Switching Frequency section;
CtON is the internal 2.2 pF capacitor; and ItON is the VIN
feed-forward current that generates the on-time.
The FAN23SV20MA implements open-circuit detection
on the FREQ pin to protect the output from an infinitely
long on-time. In the event the FREQ pin is left floating,
switching of the regulator is disabled. The
FAN23SV20MA is designed for VIN input range 7 to 18 V,
fSW 200 kHz to 1 MHz, resulting in an ItON ratio of 1 to 11.
As the ratio of VOUT to VIN increases, tOFF,min introduces a
limit on the maximum switching frequency as calculated
in the following equation, where the factor 1.2 is
included in the denominator to provide some headroom
for transient operation:
  


(6)
Soft-Start (SS)
A conventional soft-start ramp is implemented to provide
a controlled startup sequence of the output voltage. A
current is generated on the SS pin to charge an external
capacitor. The lesser of the voltage on the SS pin and
the reference voltage is used for output regulation.
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 12
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
To reduce VOUT ripple and achieve a smoother ramp of
the output voltage, tON is modulated during soft-start. tON
starts at 50% of the steady-state on-time (PWM Mode)
and ramps up to 100% gradually.
During normal operation, the SS voltage is clamped to
400 mV above the FB voltage. The clamp voltage drops
to 40 mV during an overload condition to allow the
converter to recover using the soft-start ramp once the
overload condition is removed. On-time modulation
during SS is disabled when an overload condition exists.
To maintain a monotonic soft-start ramp, the regulator is
forced into PFM Mode during soft-start.
The nominal startup time is programmable through an
internal current source charging the external soft-start
capacitor CSS:
  
 
(7)
where:
CSS
=
External soft-start programming capacitor;
ISS
=
Internal soft-start charging current source,
10 µA;
tSS
=
Soft-start time; and
VREF
=
600 mV
For example; for 1 ms startup time, CSS=15 nF.
The soft-start option can be used for ratiometric tracking.
When EN is LOW, the soft-start capacitor is discharged.
Startup on Pre-Bias
FAN23SV20MA allows the regulator to start on a pre-
bias output, VOUT, and ensures VOUT is not discharged
during the soft-start operation.
To guarantee no glitches on VOUT at the beginning of the
soft-start ramp, the LS is disabled until the first positive-
going edge of the PWM signal. The regulator is also
forced into PFM Mode during soft-start to ensure the
inductor current remains positive, reducing the
possibility of discharging the output voltage.
Internal Linear Regulator
The FAN23SV20MA includes a linear regulator to
facilitate single-supply operation for self-biased
applications. PVCC is the linear regulator output and
supplies power to the internal gate drivers. The PVCC
pin should be bypassed with a 2.2 µF ceramic capacitor.
The device can operate from a 5 V rail if the VIN, PVIN,
and PVCC pins are connected together to bypass the
internal linear regulator.
VCC Bias Supply and UVLO
The VCC rail supplies power to the controller. It is
generally connected to the PVCC rail through a low-
pass filter of a 10 resistor and 0.1 µF capacitor to
minimize any noise sources from the driver supply.
An Under-Voltage Lockout (UVLO) circuit monitors the
VCC voltage to ensure proper operation. Once the VCC
voltage is above the UVLO threshold, the part begins
operation after an initialization routine of 50 µs. There is
no UVLO circuitry on either the PVCC or VIN rails.
Pulse Frequency Modulation (PFM)
One of the key benefits of using a constant on-time
modulation scheme is the seamless transitions in and
out of Pulse Frequency Modulation (PFM) Mode. The
PWM signal is not slave to a fixed oscillator and,
therefore, can operate at any frequency below the target
steady-state frequency. By reducing the frequency
during light-load conditions, the efficiency can be
significantly improved.
The FAN23SV20MA provides a Zero-Crossing Detector
(ZCD) circuit to identify when the current in the inductor
reverses direction. To improve efficiency at light load,
the LS MOSFET is turned off around the zero crossing
to eliminate negative current in the inductor. For
predictable operation entering PFM mode the controller
waits for nine consecutive zero crossings before
allowing the LS MOSFET to turn off.
In PFM Mode, fSW varies or modulates proportionally to
the load; as load decreases, fSW also decreases. The
switching frequency, while the regulator is operating in
PFM, can be expressed as:
 

󰇛 󰇜
 
(8)
where L is inductance and IOUT is output load current.
Protection Features
The converter output is monitored and protected against
over-current, over-voltage, under-voltage, and high-
temperature conditions.
Over-Current Protection (OCP)
The FAN23SV20MA uses current information through
the LS to implement valley-current limiting. While an OC
event is detected, the HS is prevented from turning on
and the LS is kept on until the current falls below the
user-defined set point. Once the current is below the set
point, the HS is allowed to turn on.
During an OC event, the output voltage may droop if the
load current is greater than the current the converter is
providing. If the output voltage drops below the UV
threshold, an overload condition is triggered. During an
overload condition, the SS clamp voltage is reduced to
40 mV and the on-time is fixed at the steady-state
duration. By nature of the control method; as VOUT drops,
the switching frequency is lower due to the reduced rate
of inductor current decay during the off-time.
The ILIM pin has an open-detection circuit to provide
protection against operation without a current limit.
Under-Voltage Protection (UVP)
If VFB is below the under-voltage threshold of -11% VREF
(534 mV), the part enters UVP and PGOOD pulls LOW.
Over-Voltage Protection (OVP)
There are two levels of OV protection: +11% and +22%.
During an OV event, PGOOD pulls LOW.
When VFB is > +11% of VREF (666 mV), both HS and LS
turn off. By turning off the LS during an OV event, VOUT
overshoot can be reduced when there is positive
inductor current by increasing the rate of discharge.
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 13
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Once the VFB voltage falls below VREF, the latched OV
signal is cleared and operation returns to normal.
A second over-voltage detection is implemented to
protect the load from more serious failure. When VFB
rises +22% above the VREF (732 mV), the HS turns off
and the LS is forced on until -11% of VREF and device
enters into latch-off mode until a power cycle on VCC.
Over-Temperature Protection (OTP)
FAN23SV20MA incorporates an over-temperature
protection circuit that disables the converter when the
controller die temperature reaches 155°C. The IC
restarts when the die temperature falls below 140°C.
Power Good (PGOOD)
The PGOOD pin serves as an indication to the system
that the output voltage of the regulator is stable and
within regulation. Whenever VOUT is outside the
regulation window or the regulator is at over-
temperature (UV, OV, and OT), the PGOOD pin is
pulled LOW.
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation or when OT is detected.
Application Information
Stability
Constant on-time stability consists of two parameters:
stability criterion and sufficient signal at VFB.
Stability criterion is given by:
  

(9)
Sufficient signal requirement is given by:
  
(10)
where IIND is the inductor current ripple and VFB is
the ripple voltage on VFB, which should be ≥12 mV.
In certain applications, especially designs utilizing only
ceramic output capacitors, there may not be sufficient
ripple magnitude available on the feedback pin for
stable operation. In this case, an external circuit
consisting of 2 resistors (R2 and R6) and 2 capacitors
(C4 and C5) can be added to inject ripple voltage into
the FB pin (see Figure 1).
There are some specific considerations when selecting
the RCC ripple injector circuit. For typical applications,
use 4.99 kΩ for R6; the value of C4 can be selected as
0.1 µF and approximate values for R2 and C5 can be
determined using the following equations.
R2 must be small enough to develop 12 mV of ripple:
 󰇛 󰇜
 
(11)
R2 must be selected such that the R2C4 time constant
enables stable operation:
  

(12)
The minimum value of C5 can be selected to minimize
the capacitive component of ripple appearing on the
feedback pin:
   󰇛󰇜

(13)
Using the minimum value of C5 generally offers the best
transient response, and 100 pF is a good initial value in
many applications. Under some operating conditions,
excessive pulse jitter may be observed. To reduce jitter
and improve stability, the value of C5 can be increased:

(14)
5 V PVCC
The PVCC is the output of the internal regulator that
supplies power to the drivers and VCC. It is crucial to keep
this pin decoupled to PGND with a ≥1 µF X5R or X7R
ceramic capacitor. Because VCC powers internal analog
circuit, it is filtered from PVCC with a 10 Ω resistor and
0.1 µF X7R decoupling ceramic capacitor to AGND.
Setting the Output Voltage (VOUT)
The output voltage VOUT is regulated by initiating a high-
side MOSFET on-time interval when the valley of the
divided output voltage appearing at the FB pin reaches
VREF. Since this method regulates at the valley of the
output ripple voltage, the actual DC output voltage on
VOUT is offset from the programmed output voltage by
the average value of the output ripple voltage. The initial
VOUT setting of the regulator can be programmed from
0.6 V to 5.5 V by an external resistor divider (R3 and
R4):
 
󰇡
󰇢
(15)
where VREF is 600 mV.
For example; for 1.2 V VOUT and 10 k R3, then R4 is
10 k. For 600 mV VOUT, R4 is left open. VFB is
trimmed to a value of 596 mV when VREF=600 mV, so
the final output voltage, including the effect of the output
ripple voltage, can be approximated by the equation:
 

(16)
Setting the Switching Frequency (fSW)
fSW is programmed through external RFREQ as follows:
 
 
(17)
where CtON=2.2 pF internal capacitor that generates
tON. For example; for fSW=500 kHz and VOUT=1.2 V,
select a standard value for RFREQ=54.9 k.
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 14
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Inductor Selection
The inductor is typically selected based on the ripple
current (IL), which is usually selected as 25% to 45% of
the maximum DC load. The inductor current rating
should be selected such that the saturation and heating
current ratings exceed the intended currents
encountered in the application over the expected
temperature range of operation. Regulators that require
fast transient response use smaller inductance and
higher current ripple; while regulators that require higher
efficiency keep ripple current on the low side.
The inductor value is given by:
󰇛 󰇜
 

(18)
Input Capacitor Selection
Input capacitor CIN is selected based on voltage rating,
RMS current ICIN(RMS) rating, and capacitance. For
capacitors having DC voltage bias derating, such as
ceramic capacitors, higher rating is strongly
recommended. RMS current rating is given by:
󰇛󰇜  󰇛󰇜
(19)
where ILOAD-MAX is the maximum load current and D
is the duty cycle VOUT/VIN. The maximum ICIN(RMS)
occurs at 50% duty cycle.
The capacitance is given by:
  󰇛󰇜
  
(20)
where VIN is the input voltage ripple, normally 1% of
VIN.
Select four 10 µF 25 V-rated ceramic capacitors with
X7R or similar dielectric, recognizing that the capacitor
DC bias characteristic indicates that the capacitance
value falls approximately 40% at VIN=12 V, with a
resultant small increase in VIN ripple voltage above
120 mV used in the calculation. Also, each 10 µF can
carry over 3 ARMS in the frequency range from 100 kHz
to 1 MHz, exceeding the input capacitor current rating
requirements. An additional 1 µF capacitor may be
needed to suppress noise generated by high frequency
switching transitions.
Output Capacitor Selection
Output capacitor COUT is selected based on voltage
rating, RMS current ICOUT(RMS) rating, and capacitance.
For capacitors having DC voltage bias derating, such as
ceramic capacitors, higher rating is highly recommended.
When calculating COUT, usually the dominant
requirement is the current load step transient. If the
unloading transient requirement (IOUT transitioning from
HIGH to LOW), is satisfied, then the load transient (IOUT
transitioning LOW to HIGH), is also usually satisfied.
The unloading COUT calculation, assuming COUT has
negligible parasitic resistance and inductance in the
circuit path, is given by:
 

󰇛 󰇜

(21)
where IMAX and IMIN are maximum and minimum
load steps, respectively and VOUT is the voltage
overshoot, usually specified at 3 to 5%.
Setting the Current Limit
Current limit is implemented by sensing the inductor
valley current across the LS MOSFET VDS during the LS
on-time. The current limit comparator prevents a new
on-time from being started until the valley current is less
than the current limit.
The set point is configured by connecting a resistor from
the ILIM pin to the SW pin. A trimmed current is output
onto the ILIM pin, which creates a voltage across the
resistor. When the voltage on ILIM goes negative, an
over-current condition is detected.
RILIM is calculated by:
  
(22)
where KILIM is the current source scale, and IVALLEY is
the inductor valley current when the current limit
threshold is reached. The factor 1.08 accounts for
the temperature offset of the LS MOSFET compared
to control circuit
With the constant on-time architecture, HS is always
turned on for a fixed on-time; this determines the peak-
to-peak inductor current.
Current ripple I is given by:
󰇛 󰇜

(23)
From the equation above, the worst-case ripple occurs
during an output short circuit (where VOUT is 0 V). This
should be taken into account when selecting the current
limit set point.
The FAN23SV20MA uses valley-current sensing; the
current limit (IILIM) set point is the valley (IVALLEY).
The valley current level for calculating RILIM is given by:
 󰇛󰇜

(24)
where ILOAD (CL) is the DC load current when the
current limit threshold is reached.
Boot Resistor
In some applications, especially with higher input voltage,
the VSW ring voltage may exceed derating guidelines of
80% to 90% of absolute rating for VSW. In this situation a
resistor can be connected in series with boot capacitor
(C3 in Figure 1) to reduce the turn-on speed of the high
side MOSFET to reduce the amplitude of the VSW ring
voltage.
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 15
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
PCB (Printed Circuit Board) Layout Guidelines
The following points should be considered before
beginning a PCB layout using the FAN23SV20MA. A
sample PCB layout from the evaluation board is shown in
Figure 24-Figure 27 following the layout guidelines.
Power components consisting of the input capacitors,
output capacitors, inductor, and FAN23SV20MA
device should be placed on a common side of the PCB
in close proximity to each other and connected using
surface copper.
Sensitive analog components including SS, FB, ILIM,
FREQ, and EN should be placed away from the high-
voltage switching circuits such as SW and BOOT, and
connected to their respective pins with short traces.
The inner PCB layer closest to the FAN23SV20MA
device should have Power Ground (PGND) under the
power processing portion of the device (PVIN, SW, and
PGND). This inner PCB layer should have a separate
Analog Ground (AGND) under the P1 pad and the
associated analog components. AGND and PGND
should be connected together near the IC between
PGND pins 18-21 and AGND pin 23 which connects to
P1 thermal pad.
The AGND thermal pad (P1) should be connected to
AGND plane on inner layer using four 0.25 mm vias
spread under the pad. No vias are included under PVIN
(P2) and SW (P3) to maintain the PGND plane under
the power circuitry intact.
Power circuit loops that carry high currents should be
arranged to minimize the loop area. Primary focus
should be directed to minimize the loop for current flow
from the input capacitor to PVIN, through the internal
MOSFETs, and returning to the input capacitor. The
input capacitor should be placed as close to the PVIN
terminals as possible.
The current return path from PGND at the low-side
MOSFET source to the negative terminal of the input
capacitor can be routed under the inductor and also
through vias that connect the input capacitor and low-
side MOSFET source to the PGND region under the
power portion of the IC.
The SW node trace which connects the source of the
high-side MOSFET and the drain of the low-side
MOSFET to the inductor should be short and wide.
To control the voltage across the output capacitor, the
output voltage divider should be located close to the FB
pin, with the upper FB voltage divider resistor connected
to the positive side of the output capacitor, and the
bottom resistor should be connected to the AGND
portion of the FAN23SV20MA device.
When using ceramic capacitor solutions with external
ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and
C4 should be connected near the inductor, and coupling
capacitor C5 should be placed near FB pin to minimize
FB pin trace length.
Decoupling capacitors for PVCC and VCC should be
located close to their respective device pins.
SW node connections to BOOT, ILIM, and ripple injection
resistor R2 should be made through separate traces.
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 16
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Figure 24. Evaluation Board Top Layer
Figure 25. Evaluation Board Inner Layer 1 Copper
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN23SV20MAMPX • Rev. 1.1 17
FAN23SV20MAMPX — 20 A Synchronous Buck Regulator
Figure 26. Evaluation Board Inner Layers 2,3, and 4 Copper
Figure 27. Evaluation Board Bottom Layer Copper
NOTES: UNLESS OTHERWISE SPECIFIED
A) NO INDUSTRY REGISTRATION APPLIES.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) DRAWING FILE NAME: MKT-PQFN34AREV2
F) FAIRCHILD SEMICONDUCTOR
SEE
DETAIL 'A' SCALE: 2:1
SEATING
PLANE
0.25±0.05
0.025±0.025
1.05±0.10
5.50±0.10
5.00±0.10
(30X)
1
PIN#1
INDICATOR
1
9
10
17
18
26
27
34
9
10
17
1826
27
34
0.25±0.05
(0.43)
2.18±0.011.58±0.01
(0.35) 0.50±0.01
0.40±0.01
(0.35)
(1.75)
3.50±0.01
(0.35)
(0.75)
(0.35)
(0.24) (0.28)
1.75±0.01
(0.25)
0.43±0.01
(0.33)
2.58±0.01
(0.35)
0.68±0.01
(0.25)
(30X)
(3X)
LAND PATTERN
RECOMMENDATION
1 9
10
17
1826
27
34
1.80
(0.35)
2.10
2.18
1.58
5.70
0.55 (30X)
(1.75)
(1.85)
3.504.10
(0.08)
0.43
(0.35)(0.30)
0.30 (30X)
0.20
2.58
0.75
0.68
3.60 5.20
0.55
0.50±0.05
4.10
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