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FAN23SV20MAMPX 20 A Synchronous Buck Regulator Features Description VIN Range: 7 V to 18 V Using Internal Linear Regulator for Bias VIN Range: 4.5 V to 5.5 V with VIN/PVIN/PVCC Connected to Bypass Internal Regulator High Efficiency: Over 96% Peak The FAN23SV20MA is a highly efficient synchronous buck regulator. The regulator is capable of operating with an input range from 7 V to 18 V and supporting up to 20 A load currents. The device can operate from a 5 V rail (10%) if VIN, PVIN, and PVCC are connected together to bypass the internal linear regulator. Continuous Output Current: 20 A Internal Linear Bias Regulator Accurate Enable facilitates VIN UVLO Functionality PFM Mode for Light-Load Efficiency Excellent Line and Load Transient Response Precision Reference: 1% Over-Temperature Output Voltage Range: 0.6 to 5.5 V Programmable Frequency: 200 kHz to 1 MHz Programmable Soft-Start Low Shutdown Current Adjustable Sourcing Current Limit The FAN23SV20MA utilizes Fairchild's constant on-time control architecture to provide excellent transient response and to maintain a relatively constant switching frequency. The device utilizes Pulse Frequency Modulation (PFM) mode to maximize light-load efficiency by reducing switching frequency when the inductor is operating in discontinuous conduction mode at light loads. Switching frequency and over-current protection can be programmed to provide a flexible solution for various applications. Output over-voltage, undervoltage, over-current, and thermal shutdown protections help prevent damage to the device during fault conditions. After thermal shutdown is activated, a hysteresis feature restarts the device when normal operating temperature is reached. Internal Boot Diode Thermal Shutdown Halogen and Lead Free, RoHS Compliant Applications Servers and Desktop Computers NVDC Notebooks, Netbooks Game Consoles Telecommunications Storage Ordering Information Part Number Configuration Operating Temperature Range Output Current (A) Package FAN23SV20MAMPX PFM, No Ultrasonic Mode -40 to 125C 20 34-Lead, PQFN, 5.5 mm x 5.0 mm (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator April 2016 VIN = 12V VIN = 12V R11 10 C9 0.1F C10 2.2F CIN 0.1F R7 64.9k PVCC VCC Ext EN VIN PVIN C3 0.1F EN R7, R8 used for Accurate EN R7, R8 open for Ext EN CIN 6x10F R8 10k L1 0.47H SW PGOOD ILIM SOFT START R2 1.5k R5 1.87k C7 15nF VOUT = 1.2V IOUT=0-20A BOOT FAN23SV20MA C4 0.1F C5 100pF FREQ R3 10k COUT 6x100F FB R9 54.9k AGND R6 4.99k PGND R4 10k Figure 1. Typical Application with VIN = 12 V VIN = 5V R11 10 C9 0.1F PVCC VCC Ext EN C10 2.2F CIN 0.1F VIN CIN 6x10F PVIN C3 0.1F EN FAN23SV20MA L1 0.47H ILIM SOFT START R5 1.9k R2 1.5k C4 0.1F C5 100pF FREQ R9 54.9k VOUT = 1.2V IOUT=0-20A BOOT SW PGOOD C7 15nF FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Typical Application Diagram R3 10k COUT 6x100F FB AGND R6 4.99k PGND R4 10k Figure 2. Typical Application with VIN=5 V (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 2 VIN BOOT PVIN PVCC Linear Regulator PVCC VCC VCC VCC UVLO 1.26V/1.14V PVCC EN ENABLE VCC VCC 10A Modulator HS Gate Driver SS FB FB Comparator VREF SW FREQ PFM Comparator Control Logic x1.2 2nd Level OVP Comparator PVCC st x1.1 1 Level OVP Comparator x0.9 Under-Voltage Comparator LS Gate Driver VCC PGOOD Thermal Shutdown 10A Current Limit Comparator AGND ILIM PGND Figure 3. Block Diagram (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 3 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Functional Block Diagram VIN PVIN 9 SW PVIN 8 BOOT PVIN 7 AGND PVIN 6 PVIN PVIN 5 PVIN AGND 4 PVIN BOOT 3 PVIN SW 2 PVIN VIN 1 9 8 7 6 5 4 3 2 1 10 PVIN PVIN 10 34 NC 11 PVIN PVIN 11 33 NC 12 SW SW 12 32 FREQ 13 SW SW 13 31 SS 14 SW SW 30 PGOOD 29 15 SW SW 15 29 EN NC 28 16 SW SW 16 28 NC FB 27 17 SW SW 17 27 FB 25 24 23 22 21 20 PVCC ILIM AGND SW PGND PGND 19 18 Figure 4. Pin Assignments, Bottom View 18 19 20 21 22 23 24 25 26 VCC 26 VCC EN 14 PVCC SW (P3) PGOOD 30 ILIM AGND (P1) AGND 31 SW SS PGND 32 PGND FREQ PGND 33 PGND NC PVIN (P2) PGND 34 PGND NC Figure 5. Pin Assignments, Top View Pin Definitions Name Pad / Pin PVIN P2, 5-11 VIN 1 Power input to the linear regulator; used in the modulator for input voltage feed-forward PVCC 25 Power output of the linear regulator; directly supplies power for the low-side gate driver and boot diode. Can be connected to VIN and PVIN for operation from 5 V rail. Power supply input for the controller VCC 26 PGND 18-21 AGND P1, 4, 23 SW Description Power input for the power stage Power ground for the low-side power MOSFET and for the low-side gate driver Analog ground for the analog portions of the IC and for substrate P3, 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs BOOT 3 Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the charge to turn on the N-channel high-side MOSFET. During the freewheeling interval (low-side MOSFET on), the high-side capacitor is recharged by an internal diode connected to PVCC. ILIM 24 Current limit. A resistor between ILIM and SW sets the current limit threshold. FB 27 Output voltage feedback to the modulator EN 29 Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable. SS 31 Soft-start input to the modulator FREQ 32 On-time and frequency programming pin. Connect a resistor between FREQ and AGND to program on-time and switching frequency. PGOOD 30 Power good; open-drain output indicating VOUT is within set limits. NC 28, 33-34 Leave pin open or connect to AGND. (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 4 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VPVIN VIN VBOOT VSW Parameter Conditions Min. Max. Unit Power Input Referenced to PGND -0.3 25.0 V Modulator Input Referenced to AGND -0.3 25.0 V Referenced to PVCC -0.3 26.0 V Referenced to PVCC, <20 ns -0.3 30.0 V Referenced to PGND, AGND -1 25 V Boot Voltage SW Voltage to GND -5 25 V Boot to SW Voltage Referenced to SW -0.3 6.0 V Boot to PGND Referenced to PGND -0.3 30 V VPVCC Gate Drive Supply Input Referenced to PGND, AGND -0.3 6.0 V VVCC Controller Supply Input Referenced to PGND, AGND -0.3 6.0 V VILIM Current Limit Input Referenced to AGND -0.3 6.0 V VFB Output Voltage Feedback Referenced to AGND -0.3 6.0 V VEN Enable Input Referenced to AGND -0.3 6.0 V VSS Soft Start Input Referenced to AGND -0.3 6.0 V VFREQ Frequency Input Referenced to AGND -0.3 6.0 V Power Good Output Referenced to AGND -0.3 VBOOT VPGOOD ESD Electrostatic Discharge TJ Junction Temperature TSTG Storage Temperature Referenced to PGND, AGND < 20 ns 6.0 V Human Body Model, JESD22-A114 1000 V Charged Device Model, JESD22-C101 2500 V +150 C +150 C -55 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VPVIN Parameter Conditions Typ. Max. Unit Power Input Referenced to PGND 7 18 V VIN Modulator Input Referenced to AGND 7 18 V TJ Junction Temperature -40 +125 C 20 A 5.5 V ILOAD VPVIN, VIN, VPVCC Load Current TA=25C, No Airflow PVIN, VIN, and Gate Drive Supply Input VPVIN, VIN, VPVCC Connected for 5 V rail operation and Referenced to PGND, AGND 4.5 Thermal Characteristics The thermal characteristics were evaluated on a 6-layer pcb structure (2 oz/2 oz/2 oz/2 oz) measuring 7 cm x 7 cm). Symbol Parameter Typ. Unit JA Thermal Resistance, Junction-to-Ambient 22.7 C/W JC Thermal Characterization Parameter, Junction-to-Top of Case 12.6 C/W Thermal Characterization Parameter, Junction-to-PCB 1.7 C/W JPCB (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 5 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Absolute Maximum Ratings Unless otherwise noted; VIN=12 V, VOUT=1.2 V, and TA = TJ = -40 to +125C. Symbol Parameter (1) Condition Min. Typ. Max. Unit 16 A 1.8 mA Supply Current IVIN,SD Shutdown Current EN=0 V IVIN,Q Quiescent Current EN=5 V, Not Switching IVIN,GateCharge Gate Charge Current EN=5 V, fSW=500 kHz 22 mA Linear Regulator VREG Regulator Output Voltage IREG Regulator Current Limit 4.75 5.05 5.25 60 V mA Reference, Feedback Comparator VFB FB Voltage Trip Point 590 596 602 mV IFB FB Pin Bias Current -100 0 100 nA On-Time Accuracy -20 20 % 374 ns Modulator tON tOFF,MIN DMIN Minimum SW Off-Time 320 Minimum Duty Cycle FB=1 V 0 Soft-Start Current SS=0.5 V 7 SS On-Time Modulation SS<0.6 V 25 % Soft-Start ISS tON,SSMOD VSSCLAMP,NOM Nominal Soft-Start Voltage Clamp VSSCLAMP,OVL Soft-Start Voltage Clamp in Overload Condition 10 13 100 A % VFB=0.6 V 400 mV VFB=0.3 V, OC Condition 40 mV PFM Zero-Crossing Detection Comparator VOFF ZCD Offset Voltage TA=TJ=25C -6 0 mV ILIM Valley Current Limit Accuracy TA=TJ=25C, IVALLEY=24 A -10 10 % KILIM ILIM Set-Point Scale Factor ILIMTC Temperature Coefficient Current Limit 80 4000 ppm/C Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 6 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Electrical Characteristics Unless otherwise noted; VIN=12 V, VOUT=1.2 V, and TA=TJ=25C. Symbol Parameter (1) Condition Min. Typ. Max. Unit 1.11 1.26 1.43 V 1.00 1.14 4.3 4.5 Enable VTH+ Rising Threshold VHYST Hysteresis VTH- 122 Falling Threshold VENCLAMP Enable Voltage Clamp IENCLAMP Clamp Current IEN=20 A mV 1.28 V V 24 A IENLK Enable Pin Leakage EN=1.2 V 100 nA IENLK Enable Pin Leakage EN=5 V 76 A UVLO VON VCC Good Threshold Rising VHYS Hysteresis Voltage 4.4 160 V mV Fault Protection VUVP PGOOD UV Trip Point On FB Falling 86 89 92 % VVOP1 PGOOD OV Trip Point On FB Rising 108 111 115 % VOVP2 Second OV Trip Point On FB Rising; LS=On 118 122 125 % PGOOD Pull-Down Resistance IPGOOD=2 mA 125 2.03 ms 1 A RPGOOD tPG,SSDELAY PGOOD Soft-Start Delay IPG,LEAK PGOOD Leakage Current 0.82 1.42 Thermal Shutdown TOFF THYS Thermal Shutdown Trip Point Hysteresis (2) (2) 155 C 15 C Internal Bootstrap Diode VFBOOT Forward Voltage IF=10 mA IR Reverse Leakage VR=5 V 0.6 V 1000 A Notes: 1. Device is 100% production tested at TA=25C. Limits over that temperature are guaranteed by design. 2. Guaranteed by design; not production tested. (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 7 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Electrical Characteristics (Continued) Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, TA=25C, and no airflow; unless otherwise specified. Figure 6. Efficiency vs. Load Current with VIN=12 V and fSW=500 kHz Figure 7. Efficiency vs. Load Current with VIN=12 V and fSW=300 kHz Figure 8. Case Top Temperature vs. Load Current with VIN=12 V and fSW=500 kHz Figure 9. Case Top Temperature vs. Load Current with VIN=12 V and fSW=300 kHz Figure 10. Load Regulation with VIN=12 V, VOUT=1.2 V and fSW=500 kHz Figure 11. Line Regulation with VIN=12 V, VOUT=1.2 V and fSW=500 kHz (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 8 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Typical Performance Characteristics Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, TA=25C, and no airflow; unless otherwise specified. EN (5V/div) EN(5V/div) Soft Start (0.5V/div) Vin=12V Iout=0A Vin=12V Iout=20A Soft Start (0.5V/div) Vout (1V/div) Vout (0.5V/div) PGOOD (5V/div) PGOOD (5V/div) Time (500s/div) Time (500s/div) Figure 12. Startup Waveforms with 0 A Load Current Figure 13. Startup Waveforms with 20 A Load Current EN (5V/div) Vin=12V Iout=0A Soft Start (0.5V/div) Vout (1V/div) Vout Prebias PGOOD (5V/div) Time (500s/div) Figure 14. Shutdown Waveforms with 20 A Load Current Figure 15. Startup Waveforms with Prebias Voltage on Output Vout (20mV/div) Vout (20mV/div) Vin=12V Iout=20A Vin=12V VSW (10V/div) VSW (5V/div) Time (10ms/div) Time (1s/div) Figure 16. Static Load Ripple at No Load (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 Figure 17. Static Load Ripple at Full Load www.fairchildsemi.com 9 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Typical Performance Characteristics Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, TA=25C, and no airflow; unless otherwise specified. Vout (20mV/div) Vout (20mV/div) Vin=12V Vout=1.2V Vin=12V Vout=1.2V Iout (2A/div) Iout (2A/div) Time (100s/div) Time (100s/div) Figure 18. Operation as Load Changes from 0 A to 2 A Figure 19. Operation as Load Changes from 2 A to 0 A Vout (200mV/div) Vout (200mV/div) Vin = 12V, Vout = 1.2V Iout from 0A to 10A, 3.3A/s IL (5A/div) IL (5A/div) Vin = 12V, Vout = 1.2V Iout from 10A to 20A, 3.3A/s Time (100s/div) Time (100s/div) Figure 20. Load Transient from 0% to 50% Load Current Figure 21. Load Transient from 50% to 100% Load Current PGOOD indicates UVP With Vout falling in OCP PGOOD (5V/div) Pull Vout to 3.8V through 3 resistor Vout (1V/div) Level 2 Vfb (0.5V/div) Level 1 Vout (1V/div) Soft Start (1V/div) PGOOD (5V/div) Iout=0A then short output IL (10A/div) Vsw (10V/div) Time (100s/div) Figure 22. Over-Current Protection with Heavy Load Figure 23. Over-Voltage Protection Level 1 and Level 2 Applied (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 10 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Typical Performance Characteristics The FAN23SV20MA uses a constant on-time modulation architecture with a VIN feed-forward input to accommodate a wide VIN range. This method provides fixed switching frequency (fSW ) operation when the inductor operates in Continuous Conduction Mode (CCM) and variable frequency when operating in Pulse Frequency Mode (PFM) at light loads. Additional benefits include excellent line and load transient response, cycle-by-cycle current limiting, and no loop compensation is required. Constant On-Time Modulation The FAN23SV20MA uses a constant on-time modulation technique, in which the HS MOSFET is turned on for a fixed time, set by the modulator, in response to the input voltage and the frequency setting resistor. This on-time is proportional to the desired output voltage, divided by the input voltage. With this proportionality, the frequency is essentially constant over the load range where inductor current is continuous. At the beginning of each cycle, FAN23SV20MA turns on the high-side MOSFET (HS) for a fixed duration (tON). At the end of tON, HS turns off for a duration (tOFF) determined by the operating conditions. Once the FB voltage (VFB) falls below the reference voltage (VREF), a new switching cycle begins. For buck converter in Continuous-Conduction Mode (CCM), the switching frequency fSW is expressed as: (3) The on-time generator sets the on-time (tON) for the high-side MOSFET, which results in the switching frequency of the regulator during steady-state operation. To maintain a relatively constant switching frequency over a wide range of input conditions, the input voltage information is fed into the on-time generator. The modulator provides a minimum off-time (tOFF-MIN) of 320 ns to provide a guaranteed interval for low-side MOSFET (LS) current sensing and PFM operation. tOFFMIN is also used to provide stability against multiple pulsing and limits maximum switching frequency during transient events. tON is determined by: Enable (4) The enable pin can be driven with an external logic signal, connected to a resistive divider from PVIN/Vin to ground to create an Under-Voltage Lockout (UVLO) based on the PVIN/VIN supply, or connected to PVIN/VIN through a single resistor to auto-enable while operating within the EN pin internal clamp current sink capability. where ItON is: (5) where RFREQ is the frequency-setting resistor described in the Setting Switching Frequency section; CtON is the internal 2.2 pF capacitor; and ItON is the VIN feed-forward current that generates the on-time. The EN pin can be directly driven by logic voltages of 5 V, 3.3 V, 2.5 V, etc. If the EN pin is driven by 5 V logic, a small current flows into the pin when the EN pin voltage exceeds the internal clamp voltage of 4.3 V. To eliminate clamp current flowing into the EN pin use a voltage divider to limit the EN pin voltage to < 4 V. The FAN23SV20MA implements open-circuit detection on the FREQ pin to protect the output from an infinitely long on-time. In the event the FREQ pin is left floating, switching of the regulator is disabled. The FAN23SV20MA is designed for VIN input range 7 to 18 V, fSW 200 kHz to 1 MHz, resulting in an ItON ratio of 1 to 11. To implement the UVLO function based on PVIN/VIN voltage level, select values for R7 and R8 in Figure 1 such that the tap point reaches 1.26 V when VIN reaches the desired startup level using the following equation: As the ratio of VOUT to VIN increases, tOFF,min introduces a limit on the maximum switching frequency as calculated in the following equation, where the factor 1.2 is included in the denominator to provide some headroom for transient operation: (1) where VIN,on is the input voltage for startup and VEN,on is the EN pin rising threshold of 1.26 V. With R8 selected as 10 k, and VIN,on=9 V the value of R7 is 61.9 k. (6) The EN pin can be pulled high with a single resistor connected from VIN to the EN pin. With VIN > 5.5 V a series resistor is required to limit the current flow into the EN pin clamp to less than 24 A to keep the internal clamp within normal operating range. The resistor value can be calculated from the following equation: Soft-Start (SS) A conventional soft-start ramp is implemented to provide a controlled startup sequence of the output voltage. A current is generated on the SS pin to charge an external capacitor. The lesser of the voltage on the SS pin and the reference voltage is used for output regulation. (2) (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 11 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Circuit Operation Pulse Frequency Modulation (PFM) One of the key benefits of using a constant on-time modulation scheme is the seamless transitions in and out of Pulse Frequency Modulation (PFM) Mode. The PWM signal is not slave to a fixed oscillator and, therefore, can operate at any frequency below the target steady-state frequency. By reducing the frequency during light-load conditions, the efficiency can be significantly improved. During normal operation, the SS voltage is clamped to 400 mV above the FB voltage. The clamp voltage drops to 40 mV during an overload condition to allow the converter to recover using the soft-start ramp once the overload condition is removed. On-time modulation during SS is disabled when an overload condition exists. The FAN23SV20MA provides a Zero-Crossing Detector (ZCD) circuit to identify when the current in the inductor reverses direction. To improve efficiency at light load, the LS MOSFET is turned off around the zero crossing to eliminate negative current in the inductor. For predictable operation entering PFM mode the controller waits for nine consecutive zero crossings before allowing the LS MOSFET to turn off. To maintain a monotonic soft-start ramp, the regulator is forced into PFM Mode during soft-start. The nominal startup time is programmable through an internal current source charging the external soft-start capacitor CSS: (7) CSS = External soft-start programming capacitor; In PFM Mode, fSW varies or modulates proportionally to the load; as load decreases, fSW also decreases. The switching frequency, while the regulator is operating in PFM, can be expressed as: Internal soft-start charging current source, 10 A; (8) where: ISS = tSS = Soft-start time; and where L is inductance and IOUT is output load current. VREF = 600 mV Protection Features For example; for 1 ms startup time, CSS=15 nF. The soft-start option can be used for ratiometric tracking. When EN is LOW, the soft-start capacitor is discharged. The converter output is monitored and protected against over-current, over-voltage, under-voltage, and hightemperature conditions. Startup on Pre-Bias Over-Current Protection (OCP) The FAN23SV20MA uses current information through the LS to implement valley-current limiting. While an OC event is detected, the HS is prevented from turning on and the LS is kept on until the current falls below the user-defined set point. Once the current is below the set point, the HS is allowed to turn on. FAN23SV20MA allows the regulator to start on a prebias output, VOUT, and ensures VOUT is not discharged during the soft-start operation. To guarantee no glitches on VOUT at the beginning of the soft-start ramp, the LS is disabled until the first positivegoing edge of the PWM signal. The regulator is also forced into PFM Mode during soft-start to ensure the inductor current remains positive, reducing the possibility of discharging the output voltage. During an OC event, the output voltage may droop if the load current is greater than the current the converter is providing. If the output voltage drops below the UV threshold, an overload condition is triggered. During an overload condition, the SS clamp voltage is reduced to 40 mV and the on-time is fixed at the steady-state duration. By nature of the control method; as VOUT drops, the switching frequency is lower due to the reduced rate of inductor current decay during the off-time. The ILIM pin has an open-detection circuit to provide protection against operation without a current limit. Under-Voltage Protection (UVP) If VFB is below the under-voltage threshold of -11% VREF (534 mV), the part enters UVP and PGOOD pulls LOW. Over-Voltage Protection (OVP) There are two levels of OV protection: +11% and +22%. During an OV event, PGOOD pulls LOW. Internal Linear Regulator The FAN23SV20MA includes a linear regulator to facilitate single-supply operation for self-biased applications. PVCC is the linear regulator output and supplies power to the internal gate drivers. The PVCC pin should be bypassed with a 2.2 F ceramic capacitor. The device can operate from a 5 V rail if the VIN, PVIN, and PVCC pins are connected together to bypass the internal linear regulator. VCC Bias Supply and UVLO The VCC rail supplies power to the controller. It is generally connected to the PVCC rail through a lowpass filter of a 10 resistor and 0.1 F capacitor to minimize any noise sources from the driver supply. When VFB is > +11% of VREF (666 mV), both HS and LS turn off. By turning off the LS during an OV event, V OUT overshoot can be reduced when there is positive inductor current by increasing the rate of discharge. An Under-Voltage Lockout (UVLO) circuit monitors the VCC voltage to ensure proper operation. Once the VCC voltage is above the UVLO threshold, the part begins operation after an initialization routine of 50 s. There is no UVLO circuitry on either the PVCC or VIN rails. (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 12 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator To reduce VOUT ripple and achieve a smoother ramp of the output voltage, tON is modulated during soft-start. tON starts at 50% of the steady-state on-time (PWM Mode) and ramps up to 100% gradually. (12) A second over-voltage detection is implemented to protect the load from more serious failure. When VFB rises +22% above the VREF (732 mV), the HS turns off and the LS is forced on until -11% of VREF and device enters into latch-off mode until a power cycle on VCC. The minimum value of C5 can be selected to minimize the capacitive component of ripple appearing on the feedback pin: (13) Over-Temperature Protection (OTP) FAN23SV20MA incorporates an over-temperature protection circuit that disables the converter when the controller die temperature reaches 155C. The IC restarts when the die temperature falls below 140C. Using the minimum value of C5 generally offers the best transient response, and 100 pF is a good initial value in many applications. Under some operating conditions, excessive pulse jitter may be observed. To reduce jitter and improve stability, the value of C5 can be increased: Power Good (PGOOD) The PGOOD pin serves as an indication to the system that the output voltage of the regulator is stable and within regulation. Whenever VOUT is outside the regulation window or the regulator is at overtemperature (UV, OV, and OT), the PGOOD pin is pulled LOW. (14) 5 V PVCC Application Information The PVCC is the output of the internal regulator that supplies power to the drivers and VCC. It is crucial to keep this pin decoupled to PGND with a 1 F X5R or X7R ceramic capacitor. Because VCC powers internal analog circuit, it is filtered from PVCC with a 10 resistor and 0.1 F X7R decoupling ceramic capacitor to AGND. Stability Setting the Output Voltage (VOUT) Constant on-time stability consists of two parameters: stability criterion and sufficient signal at VFB. The output voltage VOUT is regulated by initiating a highside MOSFET on-time interval when the valley of the divided output voltage appearing at the FB pin reaches VREF. Since this method regulates at the valley of the output ripple voltage, the actual DC output voltage on VOUT is offset from the programmed output voltage by the average value of the output ripple voltage. The initial VOUT setting of the regulator can be programmed from 0.6 V to 5.5 V by an external resistor divider (R3 and R4): PGOOD is an open-drain output that asserts LOW when VOUT is out of regulation or when OT is detected. Stability criterion is given by: (9) Sufficient signal requirement is given by: (10) where IIND is the inductor current ripple and VFB is the ripple voltage on VFB, which should be 12 mV. (15) In certain applications, especially designs utilizing only ceramic output capacitors, there may not be sufficient ripple magnitude available on the feedback pin for stable operation. In this case, an external circuit consisting of 2 resistors (R2 and R6) and 2 capacitors (C4 and C5) can be added to inject ripple voltage into the FB pin (see Figure 1). where VREF is 600 mV. For example; for 1.2 V VOUT and 10 k R3, then R4 is 10 k. For 600 mV VOUT, R4 is left open. VFB is trimmed to a value of 596 mV when VREF=600 mV, so the final output voltage, including the effect of the output ripple voltage, can be approximated by the equation: There are some specific considerations when selecting the RCC ripple injector circuit. For typical applications, use 4.99 k for R6; the value of C4 can be selected as 0.1 F and approximate values for R2 and C5 can be determined using the following equations. (16) Setting the Switching Frequency (fSW) fSW is programmed through external RFREQ as follows: R2 must be small enough to develop 12 mV of ripple: (17) (11) where CtON=2.2 pF internal capacitor that generates tON. For example; for fSW=500 kHz and VOUT=1.2 V, select a standard value for RFREQ=54.9 k. R2 must be selected such that the R2C4 time constant enables stable operation: (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 13 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Once the VFB voltage falls below VREF, the latched OV signal is cleared and operation returns to normal. (21) The inductor is typically selected based on the ripple current (IL), which is usually selected as 25% to 45% of the maximum DC load. The inductor current rating should be selected such that the saturation and heating current ratings exceed the intended currents encountered in the application over the expected temperature range of operation. Regulators that require fast transient response use smaller inductance and higher current ripple; while regulators that require higher efficiency keep ripple current on the low side. where IMAX and IMIN are maximum and minimum load steps, respectively and VOUT is the voltage overshoot, usually specified at 3 to 5%. Setting the Current Limit Current limit is implemented by sensing the inductor valley current across the LS MOSFET VDS during the LS on-time. The current limit comparator prevents a new on-time from being started until the valley current is less than the current limit. The inductor value is given by: The set point is configured by connecting a resistor from the ILIM pin to the SW pin. A trimmed current is output onto the ILIM pin, which creates a voltage across the resistor. When the voltage on ILIM goes negative, an over-current condition is detected. (18) Input Capacitor Selection Input capacitor CIN is selected based on voltage rating, RMS current ICIN(RMS) rating, and capacitance. For capacitors having DC voltage bias derating, such as ceramic capacitors, higher rating is strongly recommended. RMS current rating is given by: RILIM is calculated by: (22) where KILIM is the current source scale, and IVALLEY is the inductor valley current when the current limit threshold is reached. The factor 1.08 accounts for the temperature offset of the LS MOSFET compared to control circuit (19) where ILOAD-MAX is the maximum load current and D is the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs at 50% duty cycle. With the constant on-time architecture, HS is always turned on for a fixed on-time; this determines the peakto-peak inductor current. The capacitance is given by: Current ripple I is given by: (20) where VIN is the input voltage ripple, normally 1% of VIN. (23) From the equation above, the worst-case ripple occurs during an output short circuit (where VOUT is 0 V). This should be taken into account when selecting the current limit set point. Select four 10 F 25 V-rated ceramic capacitors with X7R or similar dielectric, recognizing that the capacitor DC bias characteristic indicates that the capacitance value falls approximately 40% at VIN=12 V, with a resultant small increase in VIN ripple voltage above 120 mV used in the calculation. Also, each 10 F can carry over 3 ARMS in the frequency range from 100 kHz to 1 MHz, exceeding the input capacitor current rating requirements. An additional 1 F capacitor may be needed to suppress noise generated by high frequency switching transitions. The FAN23SV20MA uses valley-current sensing; the current limit (IILIM) set point is the valley (IVALLEY). The valley current level for calculating RILIM is given by: (24) where ILOAD (CL) is the DC load current when the current limit threshold is reached. Output Capacitor Selection Output capacitor COUT is selected based on voltage rating, RMS current ICOUT(RMS) rating, and capacitance. For capacitors having DC voltage bias derating, such as ceramic capacitors, higher rating is highly recommended. Boot Resistor In some applications, especially with higher input voltage, the VSW ring voltage may exceed derating guidelines of 80% to 90% of absolute rating for VSW. In this situation a resistor can be connected in series with boot capacitor (C3 in Figure 1) to reduce the turn-on speed of the high side MOSFET to reduce the amplitude of the VSW ring voltage. When calculating COUT, usually the dominant requirement is the current load step transient. If the unloading transient requirement (IOUT transitioning from HIGH to LOW), is satisfied, then the load transient (IOUT transitioning LOW to HIGH), is also usually satisfied. The unloading COUT calculation, assuming COUT has negligible parasitic resistance and inductance in the circuit path, is given by: (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 14 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Inductor Selection The following points should be considered before beginning a PCB layout using the FAN23SV20MA. A sample PCB layout from the evaluation board is shown in Figure 24-Figure 27 following the layout guidelines. The current return path from PGND at the low-side MOSFET source to the negative terminal of the input capacitor can be routed under the inductor and also through vias that connect the input capacitor and lowside MOSFET source to the PGND region under the power portion of the IC. Power components consisting of the input capacitors, output capacitors, inductor, and FAN23SV20MA device should be placed on a common side of the PCB in close proximity to each other and connected using surface copper. The SW node trace which connects the source of the high-side MOSFET and the drain of the low-side MOSFET to the inductor should be short and wide. Sensitive analog components including SS, FB, ILIM, FREQ, and EN should be placed away from the highvoltage switching circuits such as SW and BOOT, and connected to their respective pins with short traces. To control the voltage across the output capacitor, the output voltage divider should be located close to the FB pin, with the upper FB voltage divider resistor connected to the positive side of the output capacitor, and the bottom resistor should be connected to the AGND portion of the FAN23SV20MA device. The inner PCB layer closest to the FAN23SV20MA device should have Power Ground (PGND) under the power processing portion of the device (PVIN, SW, and PGND). This inner PCB layer should have a separate Analog Ground (AGND) under the P1 pad and the associated analog components. AGND and PGND should be connected together near the IC between PGND pins 18-21 and AGND pin 23 which connects to P1 thermal pad. When using ceramic capacitor solutions with external ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and C4 should be connected near the inductor, and coupling capacitor C5 should be placed near FB pin to minimize FB pin trace length. Decoupling capacitors for PVCC and VCC should be located close to their respective device pins. The AGND thermal pad (P1) should be connected to AGND plane on inner layer using four 0.25 mm vias spread under the pad. No vias are included under PVIN (P2) and SW (P3) to maintain the PGND plane under the power circuitry intact. SW node connections to BOOT, ILIM, and ripple injection resistor R2 should be made through separate traces. Power circuit loops that carry high currents should be arranged to minimize the loop area. Primary focus should be directed to minimize the loop for current flow from the input capacitor to PVIN, through the internal MOSFETs, and returning to the input capacitor. The input capacitor should be placed as close to the PVIN terminals as possible. (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 15 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator PCB (Printed Circuit Board) Layout Guidelines FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Figure 24. Evaluation Board Top Layer Figure 25. Evaluation Board Inner Layer 1 Copper (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 16 FAN23SV20MAMPX -- 20 A Synchronous Buck Regulator Figure 26. Evaluation Board Inner Layers 2,3, and 4 Copper Figure 27. Evaluation Board Bottom Layer Copper (c) 2015 Fairchild Semiconductor Corporation FAN23SV20MAMPX * Rev. 1.1 www.fairchildsemi.com 17 5.500.10 26 18 1.050.10 17 27 0.250.05 (30X) 5.000.10 34 0.250.05 0.0250.025 10 1 9 SEATING PLANE PIN#1 INDICATOR SEE DETAIL 'A' 1.580.01 (0.35) SCALE: 2:1 2.180.01 (0.43) 0.500.01 9 1 (0.25) 0.400.01 (30X) (0.35) 34 10 0.680.01 (0.35) 3.500.01 2.580.01 (1.75) 17 (0.75) (0.33) (0.35) 27 0.430.01 18 26 (0.35) NOTES: UNLESS OTHERWISE SPECIFIED A) NO INDUSTRY REGISTRATION APPLIES. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E) DRAWING FILE NAME: MKT-PQFN34AREV2 F) FAIRCHILD SEMICONDUCTOR (0.25) (0.28) (3X) (0.24) 1.750.01 5.70 2.18 1.58 0.55 (30X) 2.10 (0.35) 1.80 26 18 0.55 17 27 (1.75) 2.58 4.10 3.50 3.60 (1.85) 0.68 34 10 0.75 1 (0.30) 9 (0.35) 0.500.05 0.43 (0.08) 4.10 LAND PATTERN RECOMMENDATION 0.20 0.30 (30X) 5.20 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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