1. Product profile
1.1 General description
The LD6806 series is a small-size Low-DropOut regulator (LDO) family with a typical
voltage drop of 60 mV at 200 mA current rating.
The device is available in three different surface-mounted packages, one 0.4 mm pitch
CSP, one leadless plastic package SOT886 and one gull wing package SOT753.
The operating voltage ranges from 2.3 V to 5.5 V and the output voltage ranges from
1.2 V to 3.6 V.
LD6806x/xxH devices show a high-ohmic state at the output pin, while the LD6806x/xxP
contains a pull-down switching transistor, to provide a low-ohmic output stage when the
device is disabled. All devices use the same regulator design and are manufactured in
monolithic silicon technology.
These features make the LD6806 ser ies ideal for u se in applica tions requiring co mponent
miniaturization, such as mob ile phone han dsets, cordle ss telephones and pe rsonal digit al
devices.
1.2 Features and benefits
Input voltage range 2.3 V to 5.5 V
Output voltage range 1.2 V to 3.6 V
Dropout voltage 60 mV at 200 mA outpu t ra ting
Low quiescent current in shutdown mode (typical 1.0 A)
30 V RMS output noise voltage (typical value) at 10 Hz to 100 kHz
Turn-on time just 200 s
55 dB Power Supply Rejection Ratio (PSRR) at 1 kHz
Temperature watchdog
Current limiter
LD6806xxxH: high-ohmic (3-state) output state when disabled
LD6806xxxP: low-ohmic output state when disabled
Integrated ESD protection of 10 kV Human Body Model
WLCSP with 0.4 mm pitch and package size of 0.76 mm 0.76 mm 0.47 mm
SOT886 leadless package 1.0 mm 1.45 mm 0.5 mm
SOT753 plastic surface-mounted device
Pb-free, RoHS compliant and free of Halogen and Antimony (dark green compliant)
LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
Rev. 3 — 9 December 2011 Product data sheet
LD6806_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 9 December 2011 2 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
1.3 Applications
Analog and digital interfaces requiring lower than standard supply voltage in mobile
appliances such as mobile phones, media players and so on.
2. Pinning information
2.1 Pinning
2.2 Pin description
Fig 1. Configuration for SOT 753 Fig 2. Configuratio n for WLCSP4 Fig 3. Configurat ion for SOT886
132
45
001aao10
7
transparent top view,
solder balls facing down
B
A
21
bump A1
index area
LD6806
n.c.
001aao333
OUT
GND
n.c.
IN
EN
Transparent top view
2
3
1
5
4
6
Table 1. Pin description for SOT 753
Symbol Pin Description
IN 1 supply voltage input
GND 2 supply ground
EN 3 device enable input; active HIGH
n.c. 4 not connected
OUT 5 regulator output voltage
Table 2. Pin description for WL CSP4
Symbol Pin Description
GND A1 supply ground
EN A2 device enable input; active HIGH
OUT B1 regulator output voltage
IN B2 supply voltage input
Table 3. Pin description for SOT 886
Symbol Pin Description
OUT 1 regulator output voltage
n.c. 2 not connected
GND 3 supply ground
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Product data sheet Rev. 3 — 9 December 2011 3 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
3. Ordering information
[1] Size 0.76 mm 0.76 mm.
3.1 Ordering options
Further information on output voltage is available on request; see Section 21Contact
information.
EN 4 device enable input; active HIGH
n.c. 5 not connected
IN 6 supply voltage input
Table 3. Pin description for SOT 886
Symbol Pin Description
Table 4. Ordering info rmation
Type number Package
Name Description Version
LD6806CX4/xxx WLCSP4 wafer level chip-size package; 4 bumps (2 2)[1] -
LD6806CX4/C/xxx WLCSP4 wafer level chip-size package; 4 bumps (2 2)
with backside coating[1] -
LD6806F/xxx XSON6 plastic extremely thin small outline package; no
leads; 6 terminals; body 1 1.45 0.5 mm SOT886
LD6806TD/xxx TSOP5 plastic surface-mounted package; 5 leads SOT753
Table 5. Type number and nominal output voltage of high-ohmic output
Type number Nominal
output
voltage
Type number Nominal
output
voltage
LD6806[CX4, CX4/C, F, TD]/12H 1.2 V LD6806[CX4, CX4/C, F, TD]/23H 2.3 V
LD6806[CX4, CX4/C, F, TD]/13H 1.3 V LD6806[CX4, CX4/C, F, TD]/25H 2.5 V
LD6806[CX4, CX4/C, F, TD]/14H 1.4 V LD6806[CX4, CX4/C, F, TD]/28H 2.8 V
LD6806[CX4, CX4/C, F, TD]/16H 1.6 V LD6806[CX4, CX4/C, F, TD]/29H 2.9 V
LD6806[CX4, CX4/C, F, TD]/18H 1.8 V LD6806[CX4, CX4/C, F, TD]/30H 3.0 V
LD6806[CX4, CX4/C, F, TD]/20H 2.0 V LD6806[CX4, CX4/C, F, TD]/33H 3.3 V
LD6806[CX4, CX4/C, F, TD]/22H 2.2 V LD6806[CX4, CX4/C, F, TD]/36H 3.6 V
Table 6. Type number and nominal output voltage of low.ohmic output
Type number Nominal
output
voltage
Type number Nominal
output
voltage
LD6806[CX4, CX4/C, F, TD]/12P 1.2 V LD6806[CX4, CX4/C, F, TD]/23P 2.3 V
LD6806[CX4, CX4/C, F, TD]/13P 1.3 V LD6806[CX4, CX4/C, F, TD]/25P 2.5 V
LD6806[CX4, CX4/C, F, TD]/14P 1.4 V LD6806[CX4, CX4/C, F, TD]/28P 2.8 V
LD6806[CX4, CX4/C, F, TD]/16P 1.6 V LD6806[CX4, CX4/C, F, TD]/29P 2.9 V
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Product data sheet Rev. 3 — 9 December 2011 4 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
4. Block diagram
LD6806[CX4, CX4/C, F, TD]/18P 1.8 V LD6806[CX4, CX4/C, F, TD]/30P 3.0 V
LD6806[CX4, CX4/C, F, TD]/20P 2.0 V LD6806[CX4, CX4/C, F, TD]/33P 3.3 V
LD6806[CX4, CX4/C, F, TD]/22P 2.2 V LD6806[CX4, CX4/C, F, TD]/36P 3.6 V
Table 6. Type number and nominal output voltage of low.ohmic output …continued
Type number Nominal
output
voltage
Type number Nominal
output
voltage
Fig 4. Block diagram of LD6806x/xxH
Fig 5. Block diagram of LD6806x/xxP
001aan756
THERMAL
PROTECTION
OVERCURRENT
PROTECTION
Vreference
GENERATOR
VIN VOUT
GND
R2
R1
VEN
001aan299
THERMAL
PROTECTION
OVER CURRENT
PROTECTION
Vreference
GENERATOR
VIN VOUT
GND
R2
R1
VEN
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Product data sheet Rev. 3 — 9 December 2011 5 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
5. Limiting values
[1] The (absolute) maximum power dissipation depends on the junction temperature Tj. Higher power dissipation is allowed with lower
ambient temperatures. The conditions to determine the specified values are Tamb = 25 C and the use of a two layer PCB.
[2] According to IEC 61340-3-1.
[3] According to JESD22-A115C.
6. Recommended operating conditions
[1] See Section 10.1 “Output capacitor values.
Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VIN voltage on pin IN 4 ms transient 0.5 +6.0 V
Ptot total power dissipation LD6806CX4/xxx,
LD6806CX4/Cxxx [1] -770mW
LD6806F/xxx [1] -450mW
LD6806TD/xxx [1] -800mW
Tstg storage temperature 55 +150 C
Tjjunctio n te mp erature 40 +125 C
Tamb ambient temperature 40 +85 C
VESD electrostatic discharge voltage human body model level 6 [2] 10 kV
machine model class 3 [3] -400 V
Table 8. Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
Tamb ambient temperature 40 +85 C
Tjjunction temperature - +125 C
Pin IN
VIN voltage on pin IN 2.3 5.5 V
Pin EN
VEN voltage on pin EN 0 VIN V
Pin OUT
CL(ext) external load capacitance [1] 1.0 - F
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Product data sheet Rev. 3 — 9 December 2011 6 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
7. Thermal characteristics
[1] The overall Rth(j-a) can vary depending on the board layout. To minimize the effective Rth(j-a), all pins must have a solid connection to
larger Cu layer areas for example to the power and ground layer. In multi-layer PCB applications, the second layer should be used to
create a large heat spreader area directly below the LDO. If this layer is either ground or power , it should be connected with several vias
to the top layer connecting to the device ground or supply. Avoid the use of solder-stop varnish under the chip.
[2] Use the measurement data given for a rough estimation of the Rth(j-a) in your application. The actual Rth(j-a) value can vary in applications
using different layer stacks and layouts.
8. Characteristics
Table 9. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient LD6806CX4/xxx,
LD6806CX4/Cxxx [1][2] 130 K/W
LD6806F/xxx [1][2] 220 K/W
LD6806TD/xxx [1][2] 125 K/W
Table 10. Electrical characteristics
At recommended input voltages and Tamb =
40
Cto+85
C; voltages are referenced to GND (ground = 0 V);
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VOoutput voltage variation VOUT < 1.8 V; IOUT = 1 m A
Tamb = +25 C30.5 +3 %
30 C Tamb +85 C4- +4 %
VOUT 1.8 V; IOUT = 1 mA
Tamb = +25 C20.5 +2 %
30 C Tamb +85 C3- +3 %
Line regulation error
VO/(VOxVI) rel ative output voltage
variation with input voltage VIN = (VO(nom) + 0.2 V) to 5.5 V [1] 0.1 - +0.1 %/V
Load regulation error
VO/(VOxIO) relative output voltage
variation with output current 1mA IOUT 200 mA
LD6806CX4/xxx, LD6806CX4/Cxxx - 0.0025 0.01 %/mA
LD6806F/xxx, LD6806TD/xxx - 0.005 0.02 %/mA
Vdo dropout voltage IOUT = 200 mA; VIN >V
O(nom) [1]
LD6806CX4/xxx, LD6806CX4/Cxxx - 60 100 mV
LD6806F/xxx, LD6806TD/xxx - 80 130 mV
VIL LOW-level input voltage pin EN 0 - 0.4 V
VIH HIGH-level input voltage pin EN 1.4 - 5.5 V
IOUT current on pin OUT - - 200 mA
IOM peak output current VIN =(V
O(nom) + 0.2 V) to 5.5 V [1]
VO(nom) > 1.8 V ;
VOUT 0.95 VO(nom)
300 - - mA
VO(nom) < 1.8 V ;
VOUT 0.9 VO(nom)
300 - - mA
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Product data sheet Rev. 3 — 9 December 2011 7 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
[1] VO(nom) = nominal output voltage (device specific).
[2] The junction temperature must decrease by Tsd(hys) to enable the device after Tsd was reached and the device was disabled.
[3] LD6806x/xxP only.
9. Dynamic behavior
All results described in Section 9 are based on measurements of types LD6806CX4xxx
and LD6806Fxxx from the LD6806 product series within Section 6 “Recommended
operating cond itio ns .
9.1 Dropout
The dropout voltage is defined as the smallest input to output voltage difference at a
specified load current when the regulator operates within its linear region with the pass
transistor functioning as a plain resistor. This means that the input voltage is below the
nominal output vo ltage value .
A small dropout volt age guarantie s lower power consumption and ef ficiency maximization.
Isc short-circuit current pin OUT - 600 - mA
Iqquiescent current VEN = 1.4 V; IOUT = 0 mA - 70 100 A
VEN = 1.4V; 1mA IOUT 200 mA - 155 250 A
VEN 0.4 V - 0.1 1.0 A
Tsd shutdown temperature - 160 - C
Tsd(hys) shutdown temperature
hysteresis [2] -20 - K
PSRR power supply rejection ratio VIN = VO(nom) + 1 V; IOUT = 30 mA;
fripple = 1 kHz [1] -55 - dB
Vn(o)(RMS) RMS output noise voltage bandwidth = 1 0 Hz to 100 kHz;
CL(ext) =1F-30 - V
tstartup(reg) regulator start-up time VIN = 5.5 V; VOUT = 0.95 VO(nom);
IOUT = 200 mA; C L(ext) =1F[1] - - 200 s
tsd(reg) regulator shutdown time VIN = 5.5 V; CL(ext) =1F[3] -300- s
Rpd pull-down resistance [3] -100-
Table 10. Electrical characteristics continued
At recommended input voltages and Tamb =
40
Cto+85
C; voltages are referenced to GND (ground = 0 V);
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 3 — 9 December 2011 8 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
(1) +85 C
(2) +25 C
(3) 40 C
(1) +85 C
(2) +25 C
(3) 40 C
Fig 6. Dropout as a function of temperature for
LD6806CX4/25H Fig 7. Drop out as a function of temperat ure for
LD6806F/25H
IOUT (mA)
0 20016080 12040
001aan929
40
60
20
80
100
Vdo
(mV)
0
(1)
(2)
(3)
IOUT (mA)
0 20016080 12040
001aan930
40
60
20
80
100
Vdo
(mV)
0
(1)
(2)
(3)
(1) +85 C
(2) +25 C
(3) 40 C
(1) +85 C
(2) +25 C
(3) 40 C
Fig 8. Dropout as a function of temperature for
LD6806CX4/36H Fig 9. Drop out as a function of temperat ure for
LD6806F/36H
IOUT (mA)
0 20016080 12040
001aan935
40
60
20
80
100
Vdo
(mV)
0
(1)
(2)
(3)
IOUT (mA)
0 20016080 12040
001aan936
40
60
20
80
100
Vdo
(mV)
0
(1)
(2)
(3)
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Product data sheet Rev. 3 — 9 December 2011 9 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
9.2 Output voltage variation
The guaranteed output voltages are specified in Table 10.
(1) +85 C
(2) +25 C
(3) 40 C
Fig 10. Dropout as a function of tempe rature for LD6806TD/36P
IOUT (mA)
0 20016080 12040
018aaa223
40
60
20
80
100
Vdo
(mV)
0
(1)
(2)
(3)
(1) IOUT =1mA
(2) IOUT = 100 mA
(3) IOUT = 200 mA
(1) IOUT =1mA
(2) IOUT = 100 mA
(3) IOUT = 200 mA
Fig 11. Output voltage variation for LD6806CX4/12H Fig 12. Output voltage variation for LD6806CX4/25H
Tamb (°C)
-60 14010020 60-20
001aan942
1.20
1.18
1.22
1.24
VOUT
(V)
1.16
(1)
(2)
(3)
Tamb (°C)
-60 14010020 60-20
001aan943
2.50
2.48
2.52
2.54
VOUT
(V)
2.46
(1)
(2)
(3)
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Product data sheet Rev. 3 — 9 December 2011 10 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
9.3 Quiescent current
Quiescent or ground current is the difference between the input and the output current of
the regulator.
(1) IOUT =10mA
(2) IOUT =0mA (1) IOUT =10mA
(2) IOUT =0mA
Fig 13. Quiescent current for LD6806CX4/12H Fig 14. Quiescent current for LD6806CX4/25H
Tamb (°C)
-60 14010020 60-20
001aao106
IGND
(µA)
60
65
70
75
80
(1)
(2)
Tamb (°C)
-60 14010020 60-20
001aan944
75
80
85
IGND
(µA)
70
(1)
(2)
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Product data sheet Rev. 3 — 9 December 2011 11 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
9.4 Noise
Output noise voltage of an LDO circu i t is given as noise density or RMS output noise
voltage o ver a defined range of fr equencies (10 Hz to 100 kHz). Permanent conditions are
a constant output curren t an d a rip ple-free input voltage. The output noise voltage is
generated by the LDO regulator.
(1) 0 mA
(2) 1 mA
(3) 50 mA
(4) 100 mA
(5) 150 mA
(6) 200 mA
(1) 0 mA
(2) 1 mA
(3) 50 mA
(4) 100 mA
(5) 150 mA
(6) 200 mA
Fig 15. Noise density for LD6806CX4/25H Fig 16. Noise density for LD6806CX4/36H
001aan941
1
10-1
10
10-2
10 105
104
102103
(1)
(2)
(3)
(4)
(5)
(6)
noise
(μV/√Hz)
frequency (Hz)
001aao104
1
10-1
10
noise
(μV/√Hz)
10-2
frequency (Hz)
10 105
104
102103
(1)
(2)
(3)
(4)
(5)
(6)
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Product data sheet Rev. 3 — 9 December 2011 12 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
9.5 Line regulation
Line regulation response is the capability of the circuit to maintain the nominal output
voltage while varying the input voltage.
Regulation % VVOUT
VIN
-----------------100
VOUT
-------------
=
(1) VIN
(2) VOUT
(1) VIN
(2) VOUT
Fig 17. Line regulation for LD6806CX4/12H Fig 18. Line regulation for LD6806F/12H
time (ms)
0 0.80.60.2 0.4
001aan925
2
4
6
VIN
(V)
0
1.4
1.8
1.2
1.6
2.0
VOUT
(V)
1.0
(1)
(2)
time (ms)
0 0.2 0.4 0.6 0.70.50.30.1
001aan926
2
4
6
VIN
(V)
0
1.4
1.8
1.2
1.6
2.0
VOUT
(V)
1.0
(1)
(2)
(1) VIN
(2) VOUT
(1) VIN
(2) VOUT
Fig 19. Line regulation for LD6806CX4/25H Fig 20. Line regulation for LD6806F/25H
time (ms)
0 0.40.30.1 0.2
001aan931
2
4
6
VIN
(V)
0
2.51
2.54
2.47
2.53
2.55VOUT
(V)
2.45
2.49
2.46
2.52
2.48
2.50
(1)
(2)
time (ms)
0 0.40.30.1 0.2
001aan932
2
4
6
VIN
(V)
0
2.51
2.54
2.47
2.53
2.55VOUT
(V)
2.45
2.49
2.46
2.52
2.48
2.50
(1)
(2)
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Product data sheet Rev. 3 — 9 December 2011 13 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
9.6 Load regulation
Load regulation is the capability of the circuit to maintain the nominal output voltage while
varying the output load current.
(1) VIN
(2) VOUT
(1) VIN
(2) VOUT
Fig 21. Line regulation for LD6806CX4/36H Fig 22. Line regulation for LD6806F/36H
time (ms)
0 0.80.60.2 0.4
001aan937
2
4
6
VIN
(V)
0
3.55
3.65
3.75
VOUT
(V)
3.45
(1)
(2)
time (ms)
0 0.70.60.2 0.40.1 0.3 0.5
001aan938
2
4
6
VIN
(V)
0
3.55
3.65
3.75
VOUT
(V)
3.45
(1)
(2)
Load regulation % mA
VOUT
VO nom
------------------- 100
IOUT max
-----------------------------------
=
(1) IOUT
(2) VOUT
(1) IOUT
(2) VOUT
Fig 23. Load regulation for LD6806 CX4/12H Fig 24. Load regulation for LD 6806F/12H
time (ms)
0 0.2 0.4 0.6 0.70.50.30.1
001aan927
0.1
0.3
0.5
IOUT
(A)
-0.1
0.9
1.2
0.7
1.1
1.3 VOUT
(V)
0.5
0.8
0.6
1.0
(1)
(2)
time (ms)
0 0.80.60.2 0.4
001aan928
0.1
0.3
0.5
IOUT
(A)
-0.1
1.10
1.25
1.00
1.20
1.30
VOUT
(V)
0.90
1.05
0.95
1.15
(1)
(2)
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Product data sheet Rev. 3 — 9 December 2011 14 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
(1) IOUT
(2) VOUT
(1) IOUT
(2) VOUT
Fig 25. Load regulation for LD6806 CX4/25H Fig 26. Load regulation for LD 6806F/25H
time (ms)
0 0.40.30.1 0.2
001aan933
0.1
0.3
0.5
IOUT
(A)
-0.1
2.4
2.5
2.6
VOUT
(V)
2.3
(1)
(2)
time (ms)
0 0.40.30.1 0.2
001aan934
0.1
0.3
0.5
IOUT
(A)
-0.1
2.4
2.5
2.6
VOUT
(V)
2.3
(1)
(2)
(1) IOUT
(2) VOUT
(1) IOUT
(2) VOUT
Fig 27. Load regulation for LD6806 CX4/36H Fig 28. Load regulation for LD 6806F/36H
time (ms)
0 0.70.60.2 0.40.1 0.3 0.5
001aan939
0.1
0.3
0.5
IOUT
(A)
-0.1
3.5
3.6
3.7
VOUT
(V)
3.4
(1)
(2)
time (ms)
0 0.70.60.2 0.40.1 0.3 0.5
001aan940
0.1
0.3
0.5
IOUT
(A)
-0.1
3.5
3.6
3.7
VOUT
(V)
3.4
(1)
(2)
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Product data sheet Rev. 3 — 9 December 2011 15 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
9.7 Start-up and shut down
Start-up time defines the time needed for the LDO to achieve 95 % of its typical output
voltage level after activation via the enable pin.
Shut down time defines the time needed for the LDO to pull-down the output voltage to
10% of its nominal output voltage after deactivation via the enable pin.
(1) VEN.
(2) VOUT.(1) VEN.
(2) VOUT.
Fig 29. Start-up for LD6806CX4/23H Fig 30. Shut down for LD 6806F/25P
time (ms)
0 0.20.150.05 0.1
001aan946
0.8
0.4
1.2
1.6
Venable
(V)
0
VOUT
(V)
0.5
1
1.5
2
2.5
3
0
(1)
(2)
time (ms)
0 0.40.30.1 0.2
001aan947
0.8
1
0.6
0.4
0.2
1.2
1.4
Venable
(V)
0
(1) (2)
VOUT
(V)
0.5
1
1.5
2
2.5
3
0
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Product data sheet Rev. 3 — 9 December 2011 16 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
9.8 Power Supply Rejection Ratio (PSRR)
PSRR stands for the capability of the regulator to suppress unwanted signals on the input
voltage like noise or ripples.
for all frequencies
PSRR dB 20 Vout ripple
Vin ripple
--------------------------
log=
(1) 1 mA
(2) 50 mA
(3) 100 mA
(4) 200 mA
(1) 1 mA
(2) 50 mA
(3) 100 mA
(4) 200 mA
Fig 31. PSRR for LD6806CX4/25H Fig 32. PSRR for LD6806CX4/36H
001aan945
0
PSRR
(dB)
-70
frequency (Hz)
102105
104
103
-60
-50
-40
-30
-20
-10
(1)
(2)
(3)
(4)
001aao105
-40
-20
0
PSSR
(dB)
-60
frequency (Hz)
102105
104
103
(1)
(2)
(3)
(4)
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Product data sheet Rev. 3 — 9 December 2011 17 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
9.9 Enable threshold voltage
An active HIGH signal enables the LDO when the signal exceeds th e minimum input
HIGH voltage threshold. The device is in Off state as long the signal is below the
maximum LOW threshold. The input voltage threshold is independent from the LDO
supply voltage.
(1) LOW to HIGH
(2) HIGH to LOW
Fig 33. Enable threshold voltage
VEN (V)
0.3 1.51.10.70.5 1.30.9
001aan808
1.5
0.5
2.5
3.5
VOUT
(V)
-0.5
(2) (1)
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Product data sheet Rev. 3 — 9 December 2011 18 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
10. Application information
10.1 Output capacitor values
The LD6806 series requires external capacitors at the output to guarantee a stable
regulator behavior. Also an input capacitor is recommended to keep the input voltage
stable. These capacitors should not under-run the specified minimum Equivalent Series
Resistance (ESR).
The absolute value of the total capacitance attached to the output pin OUT influences the
shutdown time (tsd(reg)) of the LD6806 series.
[1] The minimum value of capacitance for stability and correct operation is 0.7 F. The capacitor tolerance
should be 30 % or better over the temperature range. The full range of operating conditions for the
capacitor in the application should be considered during device selection to ensure that this minimum
capacitance specification is met. The recommended capacitor type is X7R to meet the full device
temperature specification of 40 C to +125 C.
11. Test information
11.1 Quality information
This product has been qualified in accordance with NX2-00001 NXP Semiconductors
Quality and Reliability Specification and is suitable for use in consumer applications.
Table 11. External load capacitor
Symbol Parameter Conditions Min Typ Max Unit
CL(ext) external load capacitance [1] -1.0-F
ESR equivalent series resistance 5 - 500 m
Fig 34. Application di agram
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Product data sheet Rev. 3 — 9 December 2011 19 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
12. Package outline
Fig 35. Package outline WLCSP4
wlcsp4_2x2_po
European
projection
WLCSP4: wafer level chip-size package; 4 bumps (2 x 2)
bump A1
index area
D
E
X
detail X
A
A1
A2
b
e
e
12
A
B
Table 12. Dimensions of LD6806CX4/xxx for package outline WLCSP4; see Figure 35
Symbol Min Typ Max Unit
A 0.44 0.47 0.50 mm
A10.18 0.20 0.22 mm
A20.26 0.27 0.28 mm
b 0.21 0.26 0.31 mm
D 0.71 0.76 0.81 mm
E 0.71 0.76 0.81 mm
e-0.4-mm
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Product data sheet Rev. 3 — 9 December 2011 20 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
Fig 36. Package outline WLCSP4 with backside coating
European
projection
bump A1
index area
D
E
b
e
e
12
A
B
WLCSP4: wafer level chip-size package with backside coating; 4 bumps (2 x 2)
detail X
A
A1
A2
A3
wlcsp4_2x2_c_po
X
Table 13. Dimensions of LD6806CX4/Cxxx for package outline WLCSP4 with backside coating; see Figure 36
Symbol Min Typ Max Unit
A 0.47 0.51 0.55 mm
A10.18 0.20 0.22 mm
A20.26 0.27 0.28 mm
A30.03 0.04 0.05 mm
b 0.21 0.26 0.31 mm
D 0.71 0.76 0.81 mm
E 0.71 0.76 0.81 mm
e-0.4-mm
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Product data sheet Rev. 3 — 9 December 2011 21 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
Fig 37. Package outline SOT886 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT886 MO-252
SOT886
04-07-15
04-07-22
DIMENSIONS (mm are the original dimensions)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17 1.5
1.4 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
6
2
5
3
4
6×
(2)
4×
(2)
A
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Product data sheet Rev. 3 — 9 December 2011 22 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
Fig 38. SOT753; Plastic surface-mounted package; 5 leads
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT753 SC-74A
wBM
bp
D
e
A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
45
Plastic surface-mounted package; 5 leads SOT753
UNIT A1bpcDEHELpQywv
mm 0.100
0.013 0.40
0.25 3.1
2.7
0.26
0.10 1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2 0.33
0.23
A
1.1
0.9
02-04-16
06-03-16
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Product data sheet Rev. 3 — 9 December 2011 23 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
13. Soldering
Fig 39. Soldering footprint WLCSP4
wlcsp4_2x2_fr
solder resist
occupied area
solder paste = solderland
Dimensions in mm
e
D
Ee
c
(4×)
f
(4×)
Table 14. Dimensions of soldering footprint WLCSP4; see Figure 39
Symbol Min Typ Max Unit
c - 0.25 - mm
D 0.71 0.76 0.81 mm
E 0.71 0.76 0.81 mm
e-0.4-mm
f - 0.325 - mm
Fig 40. Soldering footprint SOT886 (XSON6)
sot886_fr
solder resist
occupied area
solder paste = solderland
Dimensions in mm
0.425
(6×)
1.250
0.675
1.700
0.325
(6×)
0.270
(6×)
0.370
(6×)
0.500
0.500
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Product data sheet Rev. 3 — 9 December 2011 24 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
14. Soldering of WLCSP packages
14.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
Fig 41. SOT753 (TSOP5); Reflow soldering footprint
Fig 42. SOT753 (TSOP5); Wave soldering footprint
solder lands
solder resist
occupied area
solder paste
sot753_fr
2.8253.3
0.45
(5×)0.55
(5×)
0.7
(5×)
0.8
(5×)
3.45
1.95
0.95
0.95
2.4 Dimensions in mm
sot753_fw
5.3
5.05 0.45
1.5
(4×)
1.45
(5×)2.85
1.475
1.475
solder lands
solder resist
occupied area
preferred transport
direction during soldering
Dimensions in mm
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Product data sheet Rev. 3 — 9 December 2011 25 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
All NXP WLCSP packages are lead-free.
14.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
14.3 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 43) than a PbSn process, thus
reducing the process window
Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characterist ic) while be ing low enou g h th at th e packages an d/ or boa rd s ar e no t
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 15.
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 43.
Table 15. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature ( C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
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Product data sheet Rev. 3 — 9 December 2011 26 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
14.3.1 Stand off
The stand off between the substrate and the chip is determined by:
The amount of printed solder on the substrate
The size of the solder land on the substrate
The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
14.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
14.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is remo ved from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
MSL: Moisture Sensitivity Level
Fig 43. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
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Product data sheet Rev. 3 — 9 December 2011 27 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
Device removal can be done when the substrate is heated until it is certai n that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on th e solder land s. Ap ply flu x on th e bu mps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
14.3.4 Cleaning
Cleaning can be done after reflow soldering.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
W ave soldering is a joinin g technology in which the joint s are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circu it board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
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Product data sheet Rev. 3 — 9 December 2011 28 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 44) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 16 and 17
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Table 16. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature ( C)
Volume (mm3)
< 350 350
< 2.5 2 35 220
2.5 220 220
Table 17. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature ( C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
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Product data sheet Rev. 3 — 9 December 2011 29 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 44.
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Mounting
16.1 PCB design guidelines
It is recommended, for optimum performance, to use a Non-Solder Mask Defined
(NSMD), also known as a copper-defined design, incorporating laser-drilled micro-vias
connecting the ground pads to a buried ground-plane layer. This results in the lowest
possible ground inductance and provides the best high frequency and ESD performance.
Refer to Table 18 for the recommended PCB design parameters.
MSL: Moisture Sensitivity Level
Fig 44. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
Table 18. Recommended PCB design parameters
Parameter Value or specification
PCB pad diameter 250 m
Micro-via diameter 100 m (0.004 inch)
Solder mask aperture diameter 325 m
Copper thickness 20 m to 40 m
Copper finish AuNi or OSP
PCB material FR4
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Product data sheet Rev. 3 — 9 December 2011 30 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
16.2 PCB assembly guidelines for Pb-free soldering
Table 19. Assembly recommen dations
Parameter Value or specification
Solder screen aperture diameter 250 m
Solder screen thickness 100 m (0.004 inch)
Solder paste: Pb-free SnAg (3 % to 4 %); Cu (0.5 % to 0.9 %)
Solder to flux ratio 50 : 50
Solder reflow profile see Figure 45
The device is capable of withstanding at least three reflows at this profile.
Fig 45. Pb-free solder refl ow profile
Table 20. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Treflow(peak) peak reflow temperature 230 - 260 C
t1time 1 soak time 60 - 180 s
t2time 2 time during T 250 C--30s
t3time 3 time during T 230 C10-50s
t4time 4 time durin g T > 217 C 30 - 150 s
t5time 5 - - 540 s
dT/dt rate of change of
temperature cooling rate - - 6C/s
preheat 2.5 - 4.0 C/s
001aai943
Treflow(peak)
250
230
217
T
(°C)
cooling rate
preheat
t1
t5
t4
t3
t2t (s)
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Product data sheet Rev. 3 — 9 December 2011 31 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
17. Abbreviations
18. References
[1] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[2] IEC 61340-3-1 — Methods for simulation of electrostatic effects - Hu man body
model (HBM) electrostatic discharge test waveforms
[3] JESD22-A115C — Electrostatic discharg e (ESD) Sensitivity Testing Machine
Model (MM)
[4] NX2-00001 — NXP Semiconductors Quality and Reliability Specification
[5] AN10439 — Wafer Level Chip Size Package
[6] AN10365 — Surface mount reflow soldering description
Table 21. Abbreviations
Acronym Description
CSP Chip-Size Package
DUT Device Under Test
EMI ElectroMagnetic Interference
ESD ElectroStatic Discharge
FR4 Flame Retard 4
HBM Human Body Model
LDO Low DropOut
MM Machine Model
NSMD Non-Solder Mask Design
OSP Organic Solderability Preservation
PCB Printed-Circuit Board
PSRR Power Supply Rejection Ratio
PSU Power Supply Unit
QRS Quality and Reliability Specification
RMS Root Mean S qu a re
WLCSP Wafer Level Chip-Si ze Packa ge
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Product data sheet Rev. 3 — 9 December 2011 32 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
19. Revision history
Table 22. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LD6806_SER v.3 20111209 Product data sheet - LD6806_SER v.2
Modifications: WLCSP4 package with backside coating added
SOT753 package added
Subtype LD6806x/xxP introduced
Minor text changes
LD6806_SER v.2 20110719 Product data sheet - LD6806_SER v.1
Modifications: Descriptive title updated
Table 5: title changed
Table 10: three parameters updated
Table 3: pin number updated
Section 9.4 and Section 9.8 drawings updated
Section 16: values updated
Minor text changes
LD6806_SER v.1 20110516 Preliminary data sheet - -
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Product data sheet Rev. 3 — 9 December 2011 33 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
20. Legal information
20.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full dat a
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io nThe information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-crit ical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, paten ts or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
LD6806_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 9 December 2011 34 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
20.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LD6806_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 9 December 2011 35 of 36
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
22. Tables
Table 1. Pin description for SOT753 . . . . . . . . . . . . . . . .2
Table 2. Pin description for WLCSP4. . . . . . . . . . . . . . . .2
Table 3. Pin description for SOT886 . . . . . . . . . . . . . . . .2
Table 4. Ordering information . . . . . . . . . . . . . . . . . . . . .3
Table 5. Type number and nominal output voltage of
high-ohmic output . . . . . . . . . . . . . . . . . . . . . . .3
Table 6. Type number and nominal output voltage of
low.ohmic output . . . . . . . . . . . . . . . . . . . . . . . .3
Table 7. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 8. Operating conditions . . . . . . . . . . . . . . . . . . . . .5
Table 9. Thermal characteristics . . . . . . . . . . . . . . . . . . .6
Table 10. Electrical characteristics . . . . . . . . . . . . . . . . . .6
Table 11. External load capacitor. . . . . . . . . . . . . . . . . . .18
Table 12. Dimensions of LD6806CX4/xxx for package
outline WLCSP4 ; s ee Figure 35 . . . . . . . . . . . 19
Table 13. Dimensions of LD6806CX4/Cxxx for package
outline WLCSP4 with backside coating;
see Figure 36 . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. Dimensions of soldering footprint WLCSP4;
see Figure 39 . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Lead-free process (from J-STD-020C) . . . . . . 25
Table 16. SnPb eutectic pr oce ss (fro m J-STD -0 2 0C) . . . 28
Table 17. Lead-free process (from J-STD-020C) . . . . . . 28
Table 18. Recommended PCB design parameters . . . . 29
Table 19. Assembly recommendations . . . . . . . . . . . . . . 30
Table 20. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 22. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32
23. Figures
Fig 1. Configuration for SOT753 . . . . . . . . . . . . . . . . . . .2
Fig 2. Configuration for WLCSP4 . . . . . . . . . . . . . . . . . .2
Fig 3. Configuration for SOT886 . . . . . . . . . . . . . . . . . . .2
Fig 4. Block diagram of LD6806x/xxH . . . . . . . . . . . . . . .4
Fig 5. Block diagram of LD6806x/xxP . . . . . . . . . . . . . . .4
Fig 6. Dropout as a function of temperature for
LD6806CX4/25H . . . . . . . . . . . . . . . . . . . . . . . . . .8
Fig 7. Dropout as a function of temperature for
LD6806F/25H . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Fig 8. Dropout as a function of temperature for
LD6806CX4/36H . . . . . . . . . . . . . . . . . . . . . . . . . .8
Fig 9. Dropout as a function of temperature for
LD6806F/36H . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Fig 10. Dropout as a function of temperature for
LD6806TD/36P . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Fig 11. Ou tput voltage variation for LD6806CX4/12H . . . .9
Fig 12. Outp ut voltage variation for LD6806CX4/25H . . . .9
Fig 13. Quiescent current fo r LD6806CX4/12H. . . . . . . .10
Fig 14. Quiescent current fo r LD6806CX4/25H. . . . . . . .10
Fig 15. Noise density for LD6806 CX4/25H . . . . . . . . . . .11
Fig 16. Noise density for LD6806 CX4/36H . . . . . . . . . . .11
Fig 17. Line regulation for LD6806CX4/12H . . . . . . . . . .12
Fig 18. Line regulation for LD6806F/12H. . . . . . . . . . . . .12
Fig 19. Line regulation for LD6806CX4/25H . . . . . . . . . .12
Fig 20. Line regulation for LD6806F/25H. . . . . . . . . . . . .12
Fig 21. Line regulation for LD6806CX4/36H . . . . . . . . . .13
Fig 22. Line regulation for LD6806F/36H. . . . . . . . . . . . .13
Fig 23. Load regulation for LD68 06CX4/12H. . . . . . . . . .13
Fig 24. Load regulation for LD68 06F/12H . . . . . . . . . . . .13
Fig 25. Load regulation for LD68 06CX4/25H. . . . . . . . . .14
Fig 26. Load regulation for LD68 06F/25H . . . . . . . . . . . .14
Fig 27. Load regulation for LD68 06CX4/36H. . . . . . . . . .14
Fig 28. Load regulation for LD68 06F/36H . . . . . . . . . . . .14
Fig 29. Start-up for LD6806CX4/23H. . . . . . . . . . . . . . . .15
Fig 30. Shut down for LD6806F/25P . . . . . . . . . . . . . . . .15
Fig 31. PSRR for LD6806CX4/25H . . . . . . . . . . . . . . . .16
Fig 32. PSRR for LD6806CX4/36H . . . . . . . . . . . . . . . .16
Fig 33. Enable threshold voltage . . . . . . . . . . . . . . . . . . .17
Fig 34. Application diagram. . . . . . . . . . . . . . . . . . . . . . . 18
Fig 35. Package outline WLCSP4. . . . . . . . . . . . . . . . . . 19
Fig 36. Package outline WLCSP4 with ba ckside
coating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Fig 37. Package outline SOT886 (XSON6). . . . . . . . . . . 21
Fig 38. SOT753; Plastic surface-mounted package;
5 leads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fig 39. Soldering footprint WLCSP4 . . . . . . . . . . . . . . . . 23
Fig 40. Soldering footprint SOT886 (XSON6). . . . . . . . . 23
Fig 41. SOT753 (TSOP5); Reflow sol dering footprint. . . 24
Fig 42. SOT753 (TSOP5); Wave soldering footprint. . . . 24
Fig 43. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Fig 44. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fig 45. Pb-free solder reflow profile . . . . . . . . . . . . . . . . 30
NXP Semiconductors LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 December 2011
Document identifier: LD6806_SER
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
24. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
2.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Recommended operating conditions. . . . . . . . 5
7 Thermal characteristics . . . . . . . . . . . . . . . . . . 6
8 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Dynamic behavior . . . . . . . . . . . . . . . . . . . . . . . 7
9.1 Dropout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
9.2 Output voltage variation . . . . . . . . . . . . . . . . . . 9
9.3 Quiescent current. . . . . . . . . . . . . . . . . . . . . . 10
9.4 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.5 Line regulation . . . . . . . . . . . . . . . . . . . . . . . . 12
9.6 Load regulation. . . . . . . . . . . . . . . . . . . . . . . . 13
9.7 Start-up and shut down. . . . . . . . . . . . . . . . . . 15
9.8 Power Supply Rejection Ratio (PSRR). . . . . . 16
9.9 Enable threshold voltage . . . . . . . . . . . . . . . . 17
10 Application information. . . . . . . . . . . . . . . . . . 18
10.1 Output capacitor values . . . . . . . . . . . . . . . . . 18
11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 18
11.1 Quality information . . . . . . . . . . . . . . . . . . . . . 18
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14 Soldering of WLCSP packages. . . . . . . . . . . . 24
14.1 Introduction to soldering WLCSP packages. . 24
14.2 Board mounting . . . . . . . . . . . . . . . . . . . . . . . 25
14.3 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 25
14.3.1 Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14.3.2 Quality of solder joint . . . . . . . . . . . . . . . . . . . 26
14.3.3 Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14.3.4 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
15 Soldering of SMD packages . . . . . . . . . . . . . . 27
15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 27
15.2 Wave and reflow soldering . . . . . . . . . . . . . . . 27
15.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 28
15.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 28
16 Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
16.1 PCB design guidelines. . . . . . . . . . . . . . . . . . 29
16.2 PCB assembly guidelines for Pb-free
soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 31
18 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32
20 Legal information . . . . . . . . . . . . . . . . . . . . . . 33
20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 33
20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33
20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34
21 Contact information . . . . . . . . . . . . . . . . . . . . 34
22 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
23 Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36