LT7101
1
Rev. 0
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TYPICAL APPLICATION
FEATURES DESCRIPTION
105V, 1A Low EMI
Synchronous Step-Down Regulator
with Fast Current Programming
The LT
®
7101 is a high efficiency, monolithic synchro-
nous step-down DC/DC converter utilizing a constant
frequency, average current mode control architecture. It
operates from an input voltage range of 4.4V to 105V and
provides an adjustable regulated output voltage from 1V
to VIN while delivering up to 1A of output current.
The LT7101 features high frequency operation and a low
minimum on-time that reduce inductor size and enable
constant-frequency operation even at very high step-
down ratios. In addition, the LT7101 achieves the lowest
possible dropout voltage with 100% maximum duty cycle
operation. During light load operation, converter efficiency
and output ripple can be optimized by selecting Burst
Mode, pulse-skipping or forced continuous operation.
The LT7101 includes accurate, high speed average cur-
rent programming and monitoring without the need for
an external sense resistor. Additional features include a
bypass LDO to maximize efficiency, fixed or adjustable
output voltage and loop compensation, and a wide array
of protection features to enhance reliability.
5V to 105V Input to 5V/1A Output Step-Down Regulator
Efficiency vs Load Current
APPLICATIONS
n Wide VIN Range: 4.4V to 105V (110V Abs Max)
n Ultralow EMI/EMC Emissions: CISPR 25 Compliant
n 2µA IQ When Regulating 48VIN to 3.3VOUT
n Fast and Accurate Output Current Programming and
Monitoring with No External RSENSE
n Brick Wall Current Limit
n Low Minimum On-Time: 35ns
n Wide VOUT Range: 1V to VIN
n 100% Maximum Duty Cycle Operation
n Programmable Fixed Frequency: 200kHz to 2MHz
n Eight, Pin-Selectable Fixed (1.2V to 15V) or
Adjustable Output Voltages
n Selectable Continuous, Pulse-Skipping, or Low
Ripple Burst Mode
®
Operation at Light Loads
n PLL Synchronization to External Clock
n EXTVCC LDO Powers Chip from VOUT = 3.3V to 40V
n OPTI-LOOP
®
or Fixed Internal Compensation
n Input and Output Overvoltage Protection
n Thermally Enhanced (5mm × 6mm) QFN Package
All registered trademarks and trademarks are the property of their respective owners.
n Battery Chargers and CC/CV Supplies
n Automotive and Military Systems
n Industrial, Avionics and Heavy Equipment
n Medical Instruments and Telecommunication
Systems
7101 TA01a
VFB
EXTVCC
VPRG2
FREQ
BOOST
SW
VIN
RUN
ICTRL
IMON CURRENT
MONITOR
4.7µF
1µF
VOUT
5V
1A
VIN
5V TO 105V
OVLO
PLLIN/MODE
LT7101
INTVCC
ITH
PGNDSGND
47µF
0.1µF 47µH
LOAD CURRENT (mA)
0.1
1
10
100
1000
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 72V
f
SW
= 300kHz
FIGURE 14 CIRCUIT
LT7101
2
Rev. 0
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN Supply Voltage ....................................–0.3V to 110V
INTVCC, (BOOST-SW) Voltages .................... –0.3V to 6V
BOOST Voltage .........................................–0.3V to 110V
RUN Voltage..............................................–0.3V to 110V
VFB, PGOOD Voltages ................................ –0.3V to 16V
EXTVCC Voltage ..........................................–0.3V to 41V
RIND, VPRG1, VPRG2 Voltages .................–0.3V to INTVCC
ICTRL, SS Voltages ................................–0.3V to INTVCC
FREQ, ITH, PLLIN/MODE, OVLO Voltages..... –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3, 4)
LT7101E, LT7101I............................... –40°C to 125°C
LT7101H............................................. –40°C to 150°C
LT7101MP .......................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
11 12 13 14
TOP VIEW
PGND
37
UHE36(26) PACKAGE
36-LEAD (5mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 38°C/W, θJC = 5°C/W
EXPOSED PAD (PIN 37) IS PGND, MUST BE SOLDERED TO PCB
15 16 17 18
36 35 32 31 30
21
24
25
26
27
8
7
6
3
RUN
SGND
OVLO
RIND
ITH
VFB
BOOST
SW
SW
SW
INTVCC
EXTVCC
VPRG2
PGND
PGND
VIN
VIN
VIN
FREQ
PLLIN/MODE
CLKOUT
PGOOD
SS
ICTRL
IMON
VPRG1
20
19
9
10
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT7101EUHE#PBF LT7101EUHE#TRPBF 7101 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
LT7101IUHE#PBF LT7101IUHE#TRPBF 7101 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
LT7101HUHE#PBF LT7101HUHE#TRPBF 7101 36-Lead (5mm × 6mm) Plastic QFN –40°C to 150°C
LT7101MPUHE#PBF LT7101MPUHE#TRPBF 7101 36-Lead (5mm × 6mm) Plastic QFN –55°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ORDER INFORMATION
LT7101
3
Rev. 0
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PIN CONFIGURATION ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Regulator and Voltage Loop
VIN Operating Input Voltage Range 4.4 105 V
VIN(UVLO) VIN Undervoltage Lockout VIN Rising
VIN Falling
l
l
4.36
4.11 4.50
4.25 4.64
4.39 V
V
VOUT Operating Output Voltage Range (Note 9) 1.0 105 V
IQVIN Input DC Supply Current (Note 8)
Pulse-Skipping Mode VFB = 1.04V, EXTVCC = 3.3V
VFB = 1.04V, EXTVCC = 0V 200
4.4 µA
mA
Sleep Mode VFB = 1.04V, EXTVCC = 3.3V
VFB = 1.04V, EXTVCC = 0V 1.0
9.0 µA
µA
Shutdown RUN = 0V 0.7 1.5 µA
VIN Input Current In Regulation Figure14 Circuit, VIN = 48V, IOUT = 500μA
Figure16 Circuit, VIN = 48V, IOUT = 0μA 64
275 µA
µA
VFB Regulated Feedback Voltage (Note 5)
ITH Voltage = 0.5V to 1.2V, VIN = 4.5V to 105V
VPRG1 = VPRG2 = FLOAT
VPRG1 = VPRG2 = INTVCC
VPRG1 = FLOAT, VPRG2 = INTVCC
VPRG1 = VPRG2 = SGND
VPRG1 = SGND, VPRG2 = FLOAT
VPRG1 = SGND, VPRG2 = INTVCC
VPRG1 = FLOAT, VPRG2 = SGND
VPRG1 = INTVCC, VPRG2 = FLOAT
VPRG1 = INTVCC, VPRG2 = SGND
l
l
l
l
l
l
l
l
l
0.990
1.182
1.770
2.455
3.234
3.528
4.900
11.75
14.70
1.000
1.200
1.800
2.500
3.300
3.600
5.000
12.00
15.00
1.010
1.218
1.827
2.537
3.350
3.654
5.075
12.24
15.30
V
V
V
V
V
V
V
V
V
Feedback Input Bias Current VPRG1 = VPRG2 = FLOAT
VPRG1 or VPRG2 Tied to SGND or INTVCC
±2
1.25 ±10
1.6 nA
µA
gmError Amplifier gmITH = 1V, Sink/Source = 5µA (Note 5) 1.52 mS
tON,MIN Minimum Controllable ON-Time (Note 7) l35 55 ns
RDS(ON)TOP Top Switch On-Resistance 580 mΩ
RDS(ON)BOT Bottom Switch On-Resistance 300 mΩ
Current Control and Monitoring
ILIM(AVG) Average Output Current Limit (Note 6)
ICTRL = FLOAT
ICTRL = 0.58V
1.00
0.16
1.11
0.22
1.21
0.28
A
A
IPK Top Switch Peak Current Limit ICTRL = FLOAT
ICTRL = 0.58V
l
l
1.43
0.63 1.64
0.75 1.85
0.87 A
A
VIMON Current Monitor Output Voltage (Note 6)
ISW = 1.0A
ISW = 0.25A
1.13
0.552
1.21
0.603
1.29
0.654
V
V
ICTRL Pin Pull-Up Current VICTRL = 0.5V l18 20 22 µA
Start-Up and Shutdown
ISS Soft-Start Charge Current SS = 0V l8 11 15 µA
tSS(INT) Internal Soft-Start Ramp Time SS = FLOAT 1.2 ms
VFB(OV) Feedback Overvoltage Protection Relative to Regulated VFB 7 10 13 %
VRUN(ON) RUN Pin ON Threshold VRUN Rising
VRUN Falling
l
l
1.16
1.06 1.21
1.11 1.26
1.16 V
V
RUN Pin Hysteresis 100 mV
RUN Pin Leakage Current RUN = 1.5V –10 0 10 nA
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V unless otherwise noted.
LT7101
4
Rev. 0
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOV(R) OVLO Pin Rising Threshold VOVLO Rising l1.16 1.21 1.26 V
OVLO Pin Hysteresis 65 mV
OVLO Pin Leakage Current OVLO = 1.5V –10 0 10 nA
Bias Regulators and Housekeeping
INTVCC Undervoltage Lockout INTVCC Rising
INTVCC Falling
3.00
2.80 V
V
VEXTVCC EXTVCC Switchover Voltage EXTVCC Rising
EXTVCC Falling
l
l
3.03
2.95 3.10
3.00 3.17
3.07 V
V
Regulated INTVCC Voltage from VIN 3.37 3.50 3.63 V
Regulated INTVCC Voltage from EXTVCC 3.37 3.50 3.63 V
Oscillator and Phase-Locked Loop
Programmable Frequency Accuracy RFREQ = 12.5k (200kHz) to 57.5k (2MHz)
PLLIN/MODE = 0V
l–15 15 %
fLOW Low Preset Frequency VFREQ = 0V;
PLLIN/MODE = 0V
l270 300 330 kHz
fHIGH High Preset Frequency VFREQ = INTVCC;
PLLIN/MODE = 0V
l0.9 1.0 1.1 MHz
Synchronizable Frequency PLLIN/MODE = External Clock l200 2000 kHz
PLLIN/MODE Input High Level for Clocking PLLIN/MODE = External Clock l2.0 V
PLLIN/MODE Input Low Level for Clocking PLLIN/MODE = External Clock l0.8 V
PGOOD Output
PGOOD Voltage Low IPGOOD = 1mA 0.3 0.5 V
PGOOD Leakage Current VPGOOD = 12V –1 1 µA
PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Positive 7 10 13 %
Hysteresis 2.5 %
VFB Ramping Negative –13 –10 –7 %
Hysteresis 2.5 %
TPG Delay for Reporting a Fault 24 µs
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT7101E is guaranteed to meet specifications from 0°C to
85°C with specifications over the –40°C to 125°C operating junction
temperature range assured by design, characterization and correlation with
statistical process controls. The LT7101I is guaranteed over the –40°C to
125°C operating junction temperature range, the LT7101H is guaranteed
over the –40°C to 150°C operating junction temperature range, and the
LT7101MP is tested and guaranteed over the –55°C to 150°C operating
junction temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • qJA°C/W)
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device. The overtemperature protection level is not production tested.
Note 5: The LT7101 is tested in a feedback loop that servos VFB to a
voltage near the internal reference voltage to obtain the specified ITH
voltage.
Note 6: The Average Output Current Limit, the Top Switch Peak Current
Limit and the Current Monitor Output Voltage are measured in a test circuit
that simulates operation in a typical application.
Note 7: The minimum controllable on-time is measured in a test mode.
(See Minimum ON-Time Considerations in the Applications Information
section.)
Note 8: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 9: See Operating at VOUT>6V in Applications Information section for
details about additional design constraints that may apply.
LT7101
5
Rev. 0
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TYPICAL PERFORMANCE CHARACTERISTICS
Pulse-Skipping Mode Efficiency
at 5VOUT
Pulse-Skipping Mode Efficiency
at 12VOUT
Pulse-Skipping Mode Efficiency
at 3.3VOUT
Burst Mode Efficiency at 5VOUT
TA = 25°C, unless otherwise noted.
Burst Mode Efficiency at 12VOUT Burst Mode Efficiency at 3.3VOUT
LOAD CURRENT (mA)
0.1
1
10
100
1000
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
7101 G01
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 72V
f
SW
= 300kHz
FIGURE 14 CIRCUIT
LOAD CURRENT (mA)
0.1
1
10
100
1000
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
7101 G03
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 72V
f
SW
= 300kHz
FIGURE 16 CIRCUIT
LOAD CURRENT (mA)
10
100
1000
30
40
50
60
70
80
90
100
EFFICIENCY (%)
7101 G04
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 72V
f
SW
= 300kHz
FIGURE 14 CIRCUIT
LOAD CURRENT (mA)
10
100
1000
30
40
50
60
70
80
90
100
EFFICIENCY (%)
7101 G05
VIN = 24V
VIN = 48V
VIN = 72V
VIN = 100V
f
SW
= 300kHz
FIGURE 15 CIRCUIT
LOAD CURRENT (mA)
0.1
1
10
100
1000
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
7101 G02
VIN = 24V
VIN = 48V
VIN = 72V
VIN = 100V
f
SW
= 300kHz
FIGURE 15 CIRCUIT
LOAD CURRENT (mA)
10
100
1000
30
40
50
60
70
80
90
100
EFFICIENCY (%)
7101 G06
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 72V
f
SW
= 300kHz
FIGURE 16 CIRCUIT
Forced Continuous Mode
Efficiency at 5VOUT
Forced Continuous Mode
Efficiency at 12VOUT
Forced Continuous Mode
Efficiency at 3.3VOUT
LOAD CURRENT (mA)
10
100
1000
30
40
50
60
70
80
90
100
EFFICIENCY (%)
7101 G07
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 72V
f
SW
= 300kHz
FIGURE 14 CIRCUIT
LOAD CURRENT (mA)
10
100
1000
30
40
50
60
70
80
90
100
EFFICIENCY (%)
7101 G09
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 72V
f
SW
= 300kHz
FIGURE 16 CIRCUIT
LOAD CURRENT (mA)
10
100
1000
30
40
50
60
70
80
90
100
EFFICIENCY (%)
7101 G08
VIN = 24V
VIN = 48V
VIN = 72V
VIN = 100V
f
SW
= 300kHz
FIGURE 15 CIRCUIT
LT7101
6
Rev. 0
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Regulated Feedback Voltage vs
Temperature
Average Output Current vs VIN,
ICTRL
Average Output Current vs
Temperature
Peak Current Limit vs
Temperature
Output Current Monitor vs
Average Output Current
Output Current Monitor Error vs
Average Output Current
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
V
PRG1
= FLOAT
V
PRG2
= FLOAT
TEMPERATURE (°C)
–55
–25
5
35
65
95
125
155
0.995
0.996
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
REGULATED FEEDBACK VOLTAGE (V)
7101 G13
I
CTRL
= 1.3V OR FLOAT
I
CTRL
= 0.94V
I
CTRL
= 0.58
FIGURE 14 CIRCUIT
V
IN
VOLTAGE (V)
0
20
40
60
80
100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
AVERAGE OUTPUT CURRENT (A)
7101 G14
V
ICTRL
= 1V
TEMPERATURE (°C)
–55
–25
5
35
65
95
125
155
1.50
1.55
1.60
1.65
1.70
1.75
1.80
PEAK CURRENT LIMIT (A)
7101 G16
FIGURE 14 CIRCUIT
AVERAGE OUTPUT CURRENT (A)
0
0.2
0.4
0.6
0.8
1.0
1.2
0.4
0.6
0.8
1.0
1.2
1.4
I
MON
VOLTAGE (V)
7101 G17
VIN = 24V
VIN = 48V
VIN = 72V
V
ICTRL
= 0.76V
V
ICTRL
= 1.3V OR FLOAT
FIGURE 14 CIRCUIT
TEMPERATURE (°C)
–55
–25
5
35
65
95
125
155
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
AVERAGE OUTPUT CURRENT (A)
7101 G15
FIGURE 14 CIRCUIT
AVERAGE OUTPUT CURRENT (A)
0
0.2
0.4
0.6
0.8
1.0
1.2
–2.0
–1.0
0
1.0
2.0
I
MON
VOLTAGE ERROR (%)
7101 G18
VIN = 72V
VIN = 48V
VIN = 24V
Efficiency vs Input Voltage
VOUT = 5V, Burst Mode Operation Efficiency vs Frequency at 1A
VIN Input Current in Regulation vs
Input Voltage
I
LOAD
= 1A
I
LOAD
= 500mA
I
LOAD
= 100mA
I
LOAD
= 10mA
INPUT VOLTAGE (V)
0
20
40
60
80
100
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
7101 G10
f
SW
= 300kHz
FIGURE 14 CIRCUIT
V
OUT
= 3.3V
I
LOAD
= 0
FIGURE 16 CIRCUIT
V
IN
VOLTAGE (V)
0
10
20
30
40
50
60
70
80
90
100
0
2
4
6
8
10
V
IN
SUPPLY CURRENT (µA)
7101 G12
I
LOAD
= 0.5A
FIGURE 14 CIRCUIT
FREQUENCY (MHz)
0.2
1
2
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
7101 G11
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 72V
LT7101
7
Rev. 0
For more information www.analog.com
Quiescent Input Current vs Input
Voltage
VIN Quiescent Current vs
Temperature Inductor Current at Light Load
Top and Bottom Switch
Resistance vs Temperature
Minimum On-Time vs
Temperature
Oscillator Frequency vs
Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
TOP SWITCH
BOTTOM SWITCH
TEMPERATURE (°C)
–55
–25
5
35
65
95
125
155
150
300
450
600
750
900
1050
1200
1350
RESISTANCE (mΩ)
7101 G19
TEMPERATURE (°C)
–55
–25
5
35
65
95
125
155
25
30
35
40
45
50
MINIMUM ON-TIME (ns)
7101 G20
FREQ = GND (300kHz)
FREQ = 12.5k (200kHz)
FREQ = 57.5k (2MHz)
FREQ = INTV
CC
(1MHz)
TEMPERATURE (°C)
–55
–25
5
35
65
95
125
155
–3
–2
–1
0
1
2
3
CHANGE IN FREQUENCY (%)
7101 G21
SLEEP, EXTV
CC
= GND
SHUTDOWN
V
IN
VOLTAGE (V)
0
15
30
45
60
75
90
105
0.0
2.0
4.0
6.0
8.0
10.0
V
IN
SUPPLY CURRENT (µA)
7101 G22
SLEEP
SHUTDOWN
EXTV
CC
= GND
V
IN
= 100V
TEMPERATURE (°C)
–55
–25
5
35
65
95
125
155
0
5
10
15
20
25
V
IN
SUPPLY CURRENT (uA)
7101 G23
V
IN
= 48V
I
LOAD
= 200µA
FIGURE 14 CIRCUIT
10µs/DIV
BURST MODE
500mA/DIV
PULSE–SKIPPING
MODE
500mA/DIV
FORCED
CONTINUOUS
MODE
500mA/DIV
7101 G24
LT7101
8
Rev. 0
For more information www.analog.com
Output Current Programming
Current Loop Step Response
ICTRL Voltage to Inductor Current
Gain vs Frequency
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
V
ICTRL
= 0.76V TO 1.12V PULSE
V
IN
= 48V, V
OUT
= 4V
FIGURE 14 CIRCUIT
40µs/DIV
V
ICTRL
500mV/DIV
I
L
250mA/DIV
7101 G32
V
IN
= 24V
V
OUT
= 4V
R
ICTRL
= 40.2k
I
OUT(AVG)
= 500mA
f
SW
= 300kHz
FIGURE 14 CIRCUIT
BW = 93kHz
FREQUENCY (kHz)
0.1
1
10
100
300
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
I
CTRL
VOLTAGE TO INDUCTOR CURRENT GAIN (A/V)
7101 G33
Synchronization to External ClockSW Node Waveform at Full Load Start-Up from Shutdown
Short-Circuit and Recovery
V
IN
= 48V
Burst Mode OPERATION
FIGURE 14 CIRCUIT
200µs/DIV
V
OUT
2V/DIV
I
L
500mA/DIV
V
RUN
5V/DIV
7101 G30
V
IN
= 48V
PULSE–SKIPPING MODE
FIGURE 14 CIRCUIT
100µs/DIV
V
OUT
2V/DIV
I
L
500mA/DIV
7101 G31
V
IN
= 48V
I
LOAD
= 500mA
FIGURE 14 CIRCUIT
15µs/DIV
V
SW
20V/DIV
EXTERNAL
CLOCK ON
PLLIN/MODE
1V/DIV
7101 G29
V
IN
= 48V
I
LOAD
= 1A
FIGURE 14 CIRCUIT
50ns/DIV
V
SW
10V/DIV
7101 G28
Load Step Burst Mode Operation Load Step Pulse-Skipping Mode
Load Step Forced Continuous
Mode
LOAD STEP = 50mA TO 500mA
V
IN
= 48V
FIGURE 14 CIRCUIT
40µs/DIV
V
OUT
100mV/DIV
I
L
500mA/DIV
7101 G25
LOAD STEP = 50mA TO 500mA
V
IN
= 48V
FIGURE 14 CIRCUIT
40µs/DIV
V
OUT
100mV/DIV
I
L
500mA/DIV
7101 G26
LOAD STEP = 50mA TO 500mA
V
IN
= 48V
FIGURE 14 CIRCUIT
40µs/DIV
V
OUT
100mV/DIV
I
L
500mA/DIV
7101 G27
LT7101
9
Rev. 0
For more information www.analog.com
PIN FUNCTIONS
RUN (Pin 3): Run Control Input. Holding this pin below
1.1V shuts off the switching regulator. Holding this pin
below 0.7V reduces the quiescent current to approxi-
mately 0.7µA. Place a resistor divider between V
IN
and
this pin to use as an undervoltage lockout. Tie this pin to
VIN to always enable the LT7101.
SGND (Pin 6): Signal Ground.
OVLO (Pin 7): Overvoltage Shutdown Input. If the voltage
on this pin exceeds 1.21V, then the switching regulator
is shut down and the SS pin is internally grounded. Tie
this pin to SGND to allow operation with VIN up to 105V.
RIND (Pin 8): Sets the current used to create an internal
ramp that replicates the inductor current up-slope for low
duty cycle operation. This pin generates a voltage that
varies with the switching frequency. Place a resistor to
SGND on this pin equal to 1/(3.3 • L) to set the internal
ramp current. This pin can be left floating if fixed output
voltage mode is selected using the VPRG1 and VPRG2 pins.
If VPRG1 and VPRG2 are both floating, then a resistor from
RIND to SGND must be used.
ITH (Pin 9): Error Amplifier Output and Switching Regulator
Compensation Point. Place compensation components
between the ITH pin and SGND. Tie this pin to INTVCC for
fixed internal compensation.
VFB (Pin 10): Regulator Feedback Input. When set to
adjustable mode, use an external resistor divider between
the regulator output voltage and the V
FB
pin. For fixed out-
put voltage mode, tie VFB directly to the regulator output.
FREQ (Pin 11): The frequency control pin for the internal
VCO. Connect this pin to SGND for 300kHz operation or
to INTVCC for 1MHz operation. Place a resistor to SGND
on this pin to set the operating frequency between 200kHz
and 2MHz. Minimize the capacitance on this pin if Burst
Mode operation is used. This pin sources 40µA.
Radiated EMI Performance (CISPR25 Radiated
Emission Test with Class 5 Peak Limits)
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
FIGURE 17 CIRCUIT
48V
IN
TO 5V
OUT
AT 1A
f
SW
= 400kHz
VERTICAL POLARIZATION
CLASS 5 PEAK LIMIT
LT7101
FREQUENCY (MHz)
0
100
200
300
400
500
600
700
800
900
1000
0
10
20
30
40
50
AMPLITUDE (dBµV/m)
7101 G34
LT7101
10
Rev. 0
For more information www.analog.com
PIN FUNCTIONS
PLLIN/MODE (Pin 12): External Synchronization Input
to Phase Detector and Burst Mode Control Input. When
an external clock is applied to this pin, the phase-locked
loop will force the rising edge of the SW signal to be syn-
chronized with the rising edge of the external clock, and
the LT7101 operates in forced continuous mode. When
not synchronizing to an external clock, this input deter-
mines how the LT7101 operates at light loads. Tie this
pin to SGND or float to select Burst Mode operation or to
INTVCC to force continuous inductor current operation.
Tie this pin to INTVCC through a 100k resistor to select
pulse-skipping operation. This pin sinks 10μA to SGND.
CLKOUT (Pin 13): Output clock signal available to syn-
chronize additional regulators for parallel operation. The
rising edge of CLKOUT is 180° out of phase with respect
to the rising edge of the SW pin. The output level swings
from SGND to INTVCC.
PGOOD (Pin 14): Open-Drain Power Good Output. The
VFB pin is monitored to ensure that the output is in regu-
lation. When the output is not in regulation, the PGOOD
pin is pulled low.
SS (Pin 15): Soft-Start and Regulator Timeout Input. The
voltage on the SS pin limits the regulated output voltage
when the SS voltage is less than 1V. An internal 10μA
pull-up current source is connected to this pin. A capaci-
tor to ground at this pin sets the ramp time to final regu-
lated output voltage. Leave this pin floating to use the
internal 1.2ms soft-start ramp. The SS pin also serves
as a timeout to disable switching if the EXTVCC voltage
is too low. To disable the regulator timeout feature, tie a
75k resistor between SS and INTVCC. See Soft-Start and
LDO Regulator Timeout in the Applications Information
section.
ICTRL (Pin 16): Programs the Average Output Current in
Constant Current Mode. The voltage on this pin deter-
mines the maximum ITH voltage, which in turn sets the
average output current in constant-current mode. The
peak current limit tracks 0.53A above the average current
limit set point. Tie this pin to a voltage between 0.4V and
1.3V to program the average output current to a value
between 0A and 1.11A. An internal 20μA pull-up on this
pin allows a single resistor to SGND to be used to set the
voltage. Float this pin to set the average output current to
1.11A and the peak current limit to 1.64A.
IMON (Pin 17): Average Output Current Monitor. This pin
generates a voltage between 0.4V and 1.3V that corre-
sponds to an average output current between 0A and1.11A.
V
PRG1
, V
PRG2
(Pins 18,19): Output Voltage Programming
Pins. These pins set the regulator to adjustable output
mode or to fixed output mode. Floating both pins allows
the output to be programmed through the VFB pin using
external resistors, regulating VFB to the 1V reference.
Tying one of these pins to SGND or INTV
CC
while the other
is tied to SGND, INTVCC or floating programs the output
to one of eight fixed output voltages. See Output Voltage
Programming in the Applications Information section.
EXTVCC (Pin 20): External Power Input to an Internal
LDO that Generates INTVCC. This LDO supplies INTVCC
power from EXTVCC, bypassing the internal LDO pow-
ered from V
IN
whenever EXTV
CC
is between 3.1V and
40V. If EXTV
CC
is not used, the regulator timeout feature
must be disabled by tying a 75k resistor between SS
and INTVCC. See INTVCC Regulations in the Applications
Information section.
INTVCC (Pin 21): Output of the Internal LDO regulator. The
driver and control circuits are powered from this voltage
source. Must be decoupled to PGND with a 1µF to 4.7μF
ceramic capacitor.
SW (Pins 24, 25, 26): SW Node connection from the
internal MOSFET power switches to the output inductor.
BOOST (Pin 27): Bootstrapped Supply to the High Side
Floating Gate Driver. Connect a 0.1µF ceramic capacitor
between the BOOST and SW pins.
VIN (Pins 30, 31, 32): Power Input Supply. This is the
power input to the integrated high side MOSFET switch as
well as the input to the internal LDO that generates INTVCC
voltage. Decouple this pin with a capacitor to PGND.
PGND/Exposed Pad (Pin 35, 36, 37): Power Ground.
Connect to power ground plane. The exposed pad must
be connected to PCB ground for rated electrical and ther-
mal performance.
LT7101
11
Rev. 0
For more information www.analog.com
FUNCTIONAL DIAGRAM
+
–
+
–
+
+
–
+
+
–
+
–
+
–
+
–
BURST
COMPARATOR REVERSE
CURRENT
COMPARATOR
SLEEP
ITHMIN
INTERNAL ITH
INTERNAL VFB (VFBI)
VSNS
VOUT
SELECT
VIN
CVIN
SHDN
SOFT-START
ERROR
AMP
VOUT
R2
R1
1V
0.9V
1.1V
OV
UV
10µA
VOSC
ITH
SS
SGND
PGOOD
FREQ PLLIN/MODE CLKOUT
VFB
BOOST
SW
PGND
7101 BD
OVLO
VIN
ICTRL IMON RIND EXTVCC
VOUT CVCC
3.1V
1.2V
SHDN
RUN
VPRG1
VPRG2
+
–
+
40µA
PRESET
HI/LO SYNC
DET
PFD
VCO
VOSC
VRAMP
PK CURR
COMP
PWM
COMP
AVG CURR
GM AMP
VDUTY
ITHMIN
VSNS
2 • BG
INTVCC
OV
0.42V
ITH
10µA
MODE
CONTROL
–
+
–
+
VSNS
INTVCC
BG
SW
VOSC
VPK
RCA
PWM
R
S
Q
SHDN
LOGIC
CCA
ISENSE
RECONSTRUCTION
∫dt
ITH
CLAMP
20µA
INTVCC
CHARGE
PUMP
3.5V
LDO
–
+
EN
3.5V
LDO
EN
CBST
COUT
VOUT
L
+
–
LT7101
12
Rev. 0
For more information www.analog.com
OPERATION
Main Control Loop
The LT7101 is a high efficiency, monolithic, synchronous
step-down DC/DC converter utilizing a constant frequency,
average current mode control architecture. Average cur-
rent mode control enables fast and precise control of the
output current without the need for an external sense
resistor or current sense amplifier. Instead, the induc-
tor current is sensed internally by losslessly monitoring
the top and bottom power switch currents. The LT7101
also contains a unique circuit that replicates the induc-
tor current immediately after the top switch turn-on and
combines this with the sensed switch currents to fully
reconstruct the inductor current signal internally. This
technique allows for direct control and monitoring of the
average output current as well as clean operation at very
low duty cycles.
During normal operation, the internal top power switch
(N-channel MOSFET) is turned on at the beginning of each
clock cycle, causing the inductor current to increase. The
sensed inductor current is then delivered to the average
current amplifier, whose output (VDUTY) is compared with
a saw-tooth ramp (VRAMP). When the VRAMP voltage
exceeds the VDUTY voltage, the PWM comparator trips
and turns off the top power MOSFET.
After the top power MOSFET turns off, the synchronous
power switch (N-channel MOSFET) turns on, causing the
inductor current to decrease. The bottom switch stays
on until the beginning of the next clock cycle, unless the
reverse current limit is reached and the reverse current
comparator trips. The reverse current limit is 0.4A for
forced continuous mode and 0A for burst and pulse-
skipping modes.
In closed-loop operation, the average current amplifier
creates an average current loop that forces the average
sensed current signal to be equal to the internal ITH volt-
age. Note that the DC gain and compensation of this aver-
age current loop is automatically adjusted to maintain
an optimum current-loop response. The error amplifier
adjusts the ITH voltage by comparing the divided-down
output voltage (VFBI) with a 1.0V reference voltage. If the
load current changes, the error amplifier adjusts the aver-
age inductor current as needed to keep the output voltage
in regulation.
The LT7101 has been optimized to provide the fastest pos-
sible average current loop. To achieve this, the filter on the
average current amplifier output (CCA, RCA) is set to provide
high DC gain (provided by integrator capacitor CCA) while
allowing the inductor current signal to pass through unfil-
tered. This is accomplished by resistor RCA, which intro-
duces a zero that is well below the switching frequency. The
resulting typical PWM comparator waveforms are shown in
Figure1. Note that the VDUTY signal is an inverted reflec-
tion of the inductor current signal, which is essential for
obtaining a high speed average current loop.
Figure1. Typical Current Loop Operating Waveforms
7101 F01
VRAMP
VDUTY
INDUCTOR CURRENT
Voltage loop compensation can be set externally using
the ITH pin, taking advantage of OPTI-LOOP compensa-
tion to optimize the loop response. The compensation of
the voltage loop is essentially the same as for peak cur-
rent mode control. Alternatively, the ITH pin can be tied
to INTVCC to select internal voltage loop compensation.
When internal voltage loop compensation is selected,
the LT7101 automatically adjusts the internal compensa-
tion based on switching frequency to maintain a fast and
stable voltage loop.
Power and Bias Supplies (VIN, SW, BOOST, INTVCC,
EXTVCC Pins)
The VIN pins on the LT7101 are used to supply voltage
to the drain terminal of the internal high side N-channel
LT7101
13
Rev. 0
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MOSFET. These pins also supply bias voltage for an internal
LDO regulator (the VIN LDO) that generates 3.5V at INTVCC.
The voltage on INTVCC in turn is used for internal chip bias
as well as gate drive for the bottom power MOSFETs. The
gate drive for the top power MOSFET is supplied by a float
-
ing supply (CBST) between the BOOST and SW pins, which
is charged by an internal synchronous diode from INTVCC.
In addition, an internal charge pump allows for 100% duty
cycle operation by maintaining the BOOST to SW voltage
when the top MOSFET is on continuously.
To improve efficiency and limit power dissipation in the
VIN LDO regulator, a second LDO regulator (the EXTVCC
LDO) allows the INTVCC voltage to be derived from the
lower-voltage EXTVCC pin. In most applications, the
EXTVCC pin is simply tied directly to the regulated output
voltage of the DC/DC converter to enable operation in a
high efficiency, bootstrapped configuration. In order to
ensure that the power dissipation on the internal VIN LDO
is limited to a safe level, the LT7101 incorporates a special
regulator timeout feature into the soft-start pin.
Start-Up and Shutdown (RUN, SS, OVLO Pins)
When the RUN pin is below 0.7V, the LT7101 enters a low
current shutdown state, reducing the DC supply current to
0.7µA. When the RUN pin is above 0.7V and the VIN pin is
above than the internal undervoltage threshold (VIN(UVLO))
of 4.55V, the INTVCC LDO regulators are enabled. However,
switching is inhibited until the RUN pin is greater than
VRUN(ON) = 1.21V. This allows the RUN pin to be used to
implement a VIN undervoltage lockout function so that the
power supply will not operate below a user-adjustable level.
In addition, switching is also inhibited if the voltage on
the OVLO pin exceeds VOV(R) = 1.21V. This feature can be
used to implement an input overvoltage lockout function
to prevent power supply operation during an overvoltage
condition on the input supply.
When appropriate voltages are present on the VIN, RUN
and OVLO pins, the LT7101 will begin switching and ini-
tiate a soft-start ramp of the output voltage. An internal
soft-start ramp of 1.2ms will limit the ramp rate of the
output voltage to prevent excessive input current dur-
ing start-up. If a longer ramp time is desired, a capacitor
can be placed from the SS pin to ground. The 10μA cur-
rent that is sourced from the SS pin will create a smooth
voltage ramp on the capacitor. If this external ramp rate
is slower than the internal 1.2ms soft-start, then the out-
put voltage will be limited by the ramp rate on the SS
pin instead. Once both the external and internal soft-start
ramps have exceeded 1V, the output voltage will be in
regulation. The internal and external soft-start functions
are reset during initial start-up and after an undervoltage
or overvoltage condition on the input supply.
The soft-start pin is also used to implement a regulator
timeout feature. This feature limits die temperature rise
due to power dissipation in the internal VIN LDO regulator
by disabling the top and bottom power MOSFETs after a
timeout, if EXTVCC voltage is not present. This is useful,
for example, if EXTVCC is tied to the output of the DC/DC
converter, but the converter output gets shorted to ground.
During start-up, a regulator timeout begins after both the
internal and external soft-start ramps have exceeded 1V,
and EXTVCC < 3V. If this condition persists for a period of
time (approximately 1.4 times the normal soft-start time),
then a regulator timeout fault occurs and all switching
stops. After a long restart delay (approximately 46 times
the normal soft-start time), a restart is initiated. If the
regulator timeout feature is not needed, the SS pin should
be tied to INTVCC through a 75k resistor. See Soft-Start
and LDO Regulator Timeout in the Applications Section
for more information.
Output Voltage Programming (VPRG1, VPRG2, VFB Pins)
The VPRG1 and VPRG2 pins provide a great deal of flex-
ibility in programming the output voltage of the power
supply. Floating both pins selects adjustable VOUT mode.
In this mode, the output is programmed using external
resistors on the VFB pin, and the VFB voltage is regu-
lated to the 1V reference. If one of the pins is tied either
to SGND or INTVCC, then fixed output voltage mode is
selected. In this mode, precision internal resistor dividers
are used to program the output voltage to one of eight
fixed voltage levels. See Output Voltage Programming in
the Applications Information Section.
Inductor Current Replication (RIND Pin)
The LT7101 contains a unique circuit that replicates the
inductor current immediately after the top switch turn-
on and combines this with the sensed switch currents
OPERATION
LT7101
14
Rev. 0
For more information www.analog.com
to fully reconstruct the inductor current signal internally.
This technique allows for direct control and monitoring of
the average output current as well as clean operation at
very short top switch on-times. In order to replicate the
inductor current, the LT7101 needs to know the approxi-
mate value of the inductor. This is achieved by placing a
resistor on the RIND pin that is equal to 1/(3.3•L). The
LT7101 uses the current in the RIND resistor in conjunc-
tion with the voltage on the VIN and SW pins to generate
a replicated inductor current signal. In addition, the RIND
pin current is also used in conjunction with the voltages
on VIN and SW to set the DC gain of the average current
amplifier. This is done to maintain optimum current loop
performance over all operating conditions.
Note that if fixed output voltage mode is selected using
the VPRG1 and VPRG2 pins, then the RIND pin can be left
floating. In this case, the LT7101 will assume a particular
inductor value based on output voltage and switching fre-
quency. See Inductor Value and RIND Resistor Selection
in the Applications Information section.
Light Load Operation: Forced Continuous, Burst and
Pulse-Skipping Modes (PLLIN/MODE Pin)
The LT7101 can be set to enter high efficiency Burst Mode
operation, constant frequency pulse-skipping mode or
forced continuous mode at low load currents. To select
Burst Mode operation, tie the PLLIN/MODE pin to ground.
To select forced continuous operation, tie the PLLIN/
MODE pin to INTVCC. To select pulse-skipping mode, tie
the PLLIN/MODE pin to INTVCC through a 100k resistor.
When the LT7101 is set for Burst Mode operation, the
minimum output current is set to approximately 100mA
even though the voltage on the ITH pin might indicate
a lower value. If the average inductor current is higher
than the load current, the error amplifier will decrease the
voltage on the ITH pin. When the ITH voltage drops below
0.4V, the internal sleep signal goes high (enabling sleep
mode) and both MOSFETs are turned off. The ITH pin is
then disconnected from the output of the error amplifier
and parked at 0.43V.
In sleep mode, much of the internal circuitry is turned
off, reducing the total quiescent current that the LT7101
draws to 9μA.When EXTV
CC
is present, the majority of
this quiescent current (8μA) is drawn from the EXTVCC
supply and only 1μA is drawn from the VIN supply. This
dramatically reduces the sleep mode VIN supply current
in bootstrapped applications where EXTVCC is tied to VOUT
and VIN >> VOUT. In sleep mode, the load current is sup-
plied by the output capacitor. As the output voltage VOUT
decreases, the error amplifier output begins to rise. When
the VOUT voltage drops enough, the ITH pin is reconnected
to the output of the error amplifier, the sleep signal goes
low, and normal operation is resumed by turning on the
top MOSFET on the next cycle of the internal oscillator.
When the LT7101 is set for Burst Mode operation, the
inductor current is not allowed to reverse. The reverse
current comparator turns off the bottom MOSFET just
before the inductor current reaches zero, preventing it
from reversing and going negative. Thus, the converter
operates with discontinuous inductor current (DCM).
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. This maintains continuous inductor current
operation (CCM) down to no load, and the average induc-
tor current is always determined by the voltage on the ITH
pin. In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to audio circuitry. In forced continuous mode,
the output ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skip-
ping mode, the LT7101 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads,
the PWM comparator may remain tripped for several
cycles and force the top MOSFET to stay off for the same
number of cycles (i.e., skipping pulses). The inductor cur-
rent is not allowed to reverse (discontinuous operation).
This mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference as compared to Burst Mode operation. It pro-
vides higher low current efficiency than forced continuous
mode, but not nearly as high as Burst Mode operation.
OPERATION
LT7101
15
Rev. 0
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When operating with discontinuous inductor current
(DCM) in either burst or pulse-skipping mode, the LT7101
smoothly transitions from average current to peak current
control. This feature eases compensation of the voltage
loop in light load DCM operation by removing the pole
associated with the average current loop.
To avoid spurious changes in the operating mode, the
LT7101 incorporates a 20μs delay before changing from
one mode to another. This is particularly helpful since the
PLLIN/MODE pin can be used to select an initial operating
mode, and subsequently be used to receive an external
clock for synchronization. The 20μs delay avoids changes
in mode while the synchronizing signal is recognized.
When synchronized, the LT7101 operates in forced con-
tinuous mode.
Frequency Selection and Phase-Locked Loop (FREQ,
PLLIN/MODE Pins)
The switching frequency of the LT7101 can be selected
using the FREQ pin, which can be tied to SGND, tied to
INTVCC, or programmed through an external resistor.
Tying FREQ to SGND selects 300kHz while tying FREQ to
INTVCC selects 1MHz. Placing a resistor between FREQ
and SGND sends the FREQ pin voltage into the input of
the voltage controlled oscillator (VCO), allowing the fre-
quency to be programmed between 200kHz and 2MHz.
A phase-locked loop (PLL) is available on the LT7101 to
synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LT7101’s phase detector (PFD) and low pass filter adjust
the voltage of the VCO input to align the turn-on of the top
MOSFET to the rising edge of the synchronizing signal.
When an external clock is detected, the PFD low pass
filter is quickly prebiased to the operating frequency set
by the FREQ pin before the PLL is allowed to take over
the VCO. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the top MOSFET turn-on. The ability
to prebias the loop filter allows the PLL to lock in rapidly
without deviating far from the desired frequency.
The typical capture range of the phase-locked loop is from
approximately 160kHz to 2.3MHz, with a guarantee over
all manufacturing variations to be between 200kHz and
2MHz. In other words, the LT7101’s PLL is guaranteed
to lock to an external clock source whose frequency is
between 200kHz and 2MHz.
After the PLL has locked to an external clock, if the exter-
nal clock is stopped, the LT7101 will immediately detect
this condition and prevent the PFD from adjusting the
loop, so that the internal oscillator continues operating
at the external clock frequency. After approximately 9μs,
the LT7101 will detect a loss of SYNC, and the oscilla-
tor operating frequency returns to the level set by the
FREQ pin. This feature prevents the oscillator frequency
from dipping momentarily when the external clock is
stopped, and enables smooth transitions into and out of
synchronization.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.5V rising and 1.1V falling, and this input is TTL
compatible.
The CLKOUT pin supplies a reference clock that is helpful
for synchronizing other switching circuits to the LT7101
switching frequency. The output high level of this signal is
equal to INTVCC (3.5V typical), and the rising edge of the
CLKOUT signal is 180° out of phase with respect to the
top MOSFET turn-on. This makes it easy to synchronize
two LT7101 converters and operate them out of phase to
minimize input current, or to use two LT7101’s together
for a higher current, 2-Phase converter. See 2-Phase
Operation in the Applications Information section.
Setting and Monitoring Output Current (ICTRL, IMON
Pins)
Because the LT7101 utilizes average current mode con-
trol, in which the ITH voltage is proportional to average
output current, the setting and monitoring of the average
output current is straight-forward.
The average output current limit is set using the ICTRL
pin, whose voltage directly clamps the ITH voltage to a
maximum level. Tie this pin to a voltage between 0.4V
and 1.3V to program the average output current to a value
OPERATION
LT7101
16
Rev. 0
For more information www.analog.com
between 0A and 1.11A. An internal 20μA pull-up on this
pin allows a single resistor to SGND to be used to set the
voltage. This pin can be floated to set the average output
current to 1.11A and the peak current limit to 1.64A.
By maintaining a fast and optimized current loop over all
operating conditions, the LT7101 responds to changes
in the ICTRL pin voltage with the greatest possible speed.
This is orders of magnitude faster than most competing
solutions, where a slow, average current loop is placed
outside of the voltage regulation loop. By placing the aver-
age current loop inside of the voltage regulation loop,
the LT7101 allows for current programming on a nearly
cycle-by-cycle basis.
The average output current can be monitored at the IMON
pin. The reconstructed inductor current signal (VSNS) is
run through a low pass filter (fc = 10kHz), buffered, and
then delivered to the IMON pin. The voltage on the IMON
normally varies between 0.4V and 1.3V, corresponding
to an average output current between 0A and 1.11A.
The IMON voltage may momentarily be less than 0.4V or
greater than 1.3V, but eventually is limited to these levels
by the average current loop. During SLEEP, this pin is held
at 0.4V.
Short-Circuit Protection and Minimum On-Time
The architecture of the LT7101 provides inherent protec-
tion against short-circuit conditions, without the need for
folding back either the output current or the oscillator
frequency. This is made possible because the PWM com-
parator is continuously receiving inductor current infor-
mation from the average current amplifier. This results in
automatic cycle skipping under short-circuit conditions
if the minimum on-time of the top switch is too long to
maintain control of the inductor current at the full switch-
ing frequency. Because a given switching cycle is skipped
only as needed to satisfy the high speed average current
loop, this creates a brick-wall style current limit without
any foldback or hiccups in the operation down to VOUT =
0V. Figure2 illustrates the typical operation of this brick-
wall current limit.
Figure2.
LOAD CURRENT (A)
0
0
OUTPUT VOLTAGE (V)
2
1
3
4
5
1
7101 F02
1.5
0.5
Typical Current Limit Operation
While the average current loop is extremely fast, a failsafe
peak current limit (IPK) comparator has also been incor-
porated to ensure that the inductor current cannot exceed
a safe level even momentarily. The peak current limit is
internally set to 0.53A above the average current limit,
and tracks with the average current limit set by the volt-
age on the ICTRL pin. In practice, this peak current limit
comparator is only needed when there is an abnormal
voltage on the average current amplifier output filter and
a short-circuit is simultaneously applied. In this case, the
peak current limit comparator may be needed for a few
cycles while the average current amplifier filter settles.
When operating at a high step-down ratio from VIN to
VOUT, care should be taken to choose a switching fre-
quency that is low enough to avoid operation at minimum
on-time. However, in the event that a high step-down ratio
requires an on-time that is less than the minimum, the
LT7101 architecture offers inherent protection against
output overvoltage. Once again, the PWM comparator
will automatically cause the skipping of a cycle as needed
to maintain regulation of the output voltage. While this
avoids output overvoltage, operation in this mode is unde-
sirable as it increases inductor current ripple.
In addition to this inherent protection, a separate output
overvoltage comparator monitors the VFB voltage and pre-
vents top MOSFET turn-on if an overvoltage condition is
present (VFB exceeds VFB(OV)).
OPERATION
LT7101
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Boost Supply and Dropout Operation
By making use of an internal charge pump, the LT7101
is capable of operating at 100% duty cycle, providing the
lowest possible dropout voltage and zero switching noise
while in dropout. This charge pump delivers the small
current required to maintain the static gate voltage on
the top MOSFET switch when operating in dropout. When
not operating in dropout, the gate drive voltage required
for switching the top MOSFET switch is supplied by the
charge pump formed by the BOOST capacitor (CBST),
the bottom MOSFET switch, and an internal switch from
INTVCC to BOOST. As dropout is approached, the on-time
of the bottom MOSFET switch is lengthened as needed
to maintain an adequate supply to the floating gate driver
between BOOST and SW.
Power Good (PGOOD Pin)
The PGOOD pin is connected to the open drain of an inter-
nal N-channel MOSFET. The MOSFET turns on and pulls
the PGOOD pin low when the internal feedback voltage
(VFBI) is not within ±10% of the 1V reference voltage. The
PGOOD pin is also pulled low when the RUN pin is low
(shutdown). When VFBI is within the ±10% requirement,
the MOSFET is turned off and the pin is allowed to be
pulled up by an external resistor to a source no greater
than 16V. There is a 24μs delay (TPG) before the PGOOD
pin goes low in response to the V
FBI
voltage going outside
of the ±10% window.
Overtemperature and Overvoltage Protection
In addition to the OVLO pin, which provides a user-
adjustable protection against V
IN
overvoltage, the LT7101
contains an internal VIN overvoltage shutdown feature. If
the VIN pin voltage exceeds 118.5V rising (112V falling),
then the top and bottom MOSFETs are held off and all
switching stops. Likewise, if the internal die temperature
exceeds 171°C rising (155°C falling), then the LT7101
disables switching until the temperature drops. Note that
the internal overvoltage and overtemperature protection
features are activated outside of the absolute maximum
range of operation, and therefore should not be relied
upon operationally. These features are only intended as
a secondary failsafe to improve overall system reliability
and safety.
OPERATION
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A general LT7101 application circuit is shown on the first
page of this data sheet. External component selection is
largely driven by the load requirement and begins with
the selection of the operating frequency and light load
operating mode. Next, the inductor L is chosen, which
also determines the value of resistor RIND. After the induc-
tor is chosen, the input capacitor CIN, the output capaci-
tor COUT, the internal regulator capacitor CVCC, and the
boost capacitor CBST, can be selected. Next, either a fixed
output voltage or feedback resistors are selected to set
the desired output voltage. Finally, the remaining optional
external components can be selected for functions such
as VIN undervoltage/overvoltage lock-out, external soft-
start, LDO regulator timeout, external loop compensation,
average output current monitor and limit, and PGOOD.
Setting the Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge and transition losses, but
requires larger inductance values and/or capacitance to
maintain low output ripple voltage.
Figure3.
V
OUT
= 5V
FIGURE 13 CIRCUIT
I
LOAD
= 1A
I
LOAD
= 0.5A
INPUT VOLTAGE (V)
0
20
40
60
80
100
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
MAX RECOMMENDED FREQUENCY (MHz)
7101 F03
Maximum Recommended Frequency vs Input Voltage
For most LT7101 applications, a good balance between
size and efficiency is achieved with a switching frequency
between 300kHz and 750kHz. Operating at higher switch-
ing frequencies up to 2MHz is readily possible, but switch-
ing losses generally limit the input voltage to lower levels.
This is illustrated in Figure3, which shows the maximum
recommended switching frequency versus input volt-
age at 0.5A and 1A loads for the application circuit of
Figure14. These lines correspond to a power loss of 2.5W
in the LT7101, which will result in a junction temperature
rise of approximately 85°C without air flow. See Efficiency
Considerations and Thermal Considerations sections for
more information on calculating the power loss and tem-
perature rise.
An additional constraint on operating frequency is the
minimum controllable on-time of the LT7101. While the
architecture of the LT7101 inherently maintains out-
put voltage regulation even if the minimum on-time is
exceeded, cycle-skipping will result in increased inductor
current ripple. To avoid this, chose a switching frequency
such that:
f<
V
OUT
VIN(MAX) • tON(MIN)
When operating at VOUT>6V, additional constraints on
the switching frequency may also apply. See Operating at
VOUT>6V section for more information.
The switching frequency is set using the FREQ and/or
PLLIN/MODE pins as shown in Table1.
Table1. Frequency Setting
FREQ PIN PLLIN/MODE PIN FREQUENCY(F)
SGND DC Voltage 300kHz
INTVCC DC Voltage 1MHz
R = (f/40 + 7.5k) to
SGND DC Voltage 200kHz to 2MHz
Any of the Above External Clock Phase-Locked
to External Clock
(200kHz to 2MHz)
Tying the FREQ pin to SGND selects 300kHz while tying
FREQ to INTVCC selects 1MHz. Since the FREQ pin sources
40μA, placing a resistor between FREQ and SGND allows
the frequency to be programmed anywhere between
200kHz and 2MHz. Choose a FREQ pin resistor such that:
RFREQ =
f
40
+7.5k
APPLICATIONS INFORMATION
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A phase-locked loop (PLL) is also available on the LT7101
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. Once
synchronized, the turn-on of the top MOSFET is aligned
to the rising edge of the synchronizing signal. See Phase-
Locked Loop and Frequency Synchronization section
fordetails.
Setting the Light-Load Operating Mode
The LT7101 can be set to enter high efficiency Burst Mode
operation, constant frequency pulse-skipping mode or
forced continuous conduction mode at light load currents.
To select Burst Mode operation, tie the PLLIN/MODE pin
to ground. To select forced continuous operation, tie the
PLLIN/MODE pin to INTVCC. To select pulse-skipping
mode, tie the PLLIN/MODE pin to INTVCC through a 100k
resistor. When synchronized, the LT7101 operates in
forced continuous mode. Table2 summarizes the use of
the PLLIN/MODE pin to select light-load operating mode.
Table2. Mode Selection
PLLIN/MODE PIN LIGHT-LOAD OPERATING MODE
SGND Burst Mode Operation
INTVCC Forced Continuous Mode
R = 100k to INTVCC Pulse-Skipping Mode
External Clock Forced Continuous Mode
In general, the requirements of each application will dic-
tate the appropriate choice for light-load operating mode.
In Burst Mode operation, the inductor current is not
allowed to reverse. The reverse current comparator turns
off the bottom MOSFET just before the inductor current
reaches zero, preventing it from reversing and going
negative. Thus, the converter operates in discontinuous
operation. In addition, when the average output current
falls below approximately 100mA, the inductor current
will begin bursting at frequencies lower than the switching
frequency, and entering a low current SLEEP mode when
not switching. As a result, Burst Mode operation has the
highest possible efficiency at light loads.
In forced continuous mode, the inductor current is
allowed to reverse at light loads and switches at the same
frequency regardless of load. In this mode, the efficiency
at light loads is considerably lower than in Burst Mode
operation. However, continuous operation has the advan-
tage of lower output voltage ripple and less interference
to audio circuitry. in forced continuous mode, the output
ripple is independent or load current.
In pulse-skipping mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the PWM
comparator may remain tripped for several cycles and
force the top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output rip-
ple as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
low current efficiency than forced continuous mode, but
not nearly as high as Burst Mode operation. Consequently,
pulse-skipping mode represents a compromise between
light load efficiency, output ripple and EMI.
In some applications, it may be desirable to change light-
load operating mode based on the conditions present in
the system. For example, if a system is inactive, one might
select high efficiency Burst Mode operation by keeping the
PLLIN/MODE pin set to 0V. When the system wakes, one
might send an external clock to PLLIN/MODE to switch to
forced continuous mode. Such on-the-fly mode changes
can allow an individual application to benefit from the
advantages of each light-load operating mode.
Inductor Value Selection
For a given input and output voltage, the inductor value
and operating frequency determine the inductor ripple
current. More specifically, the inductor ripple current
decreases with higher inductor value or higher operating
frequency according to the following equation:
∆IL=VOUT
f •L
⎛
⎝
⎜⎞
⎠
⎟1– VOUT
V
IN
⎛
⎝
⎜⎞
⎠
⎟
For proper operation, always use an inductor value that
is greater than:
LMIN > 520nH • VOUT
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Note that in applications with VOUT>6V, additional con-
straints on the inductance value may also apply. See
Operating at VOUT>6V section for more information.
A trade-off between component size, efficiency and oper-
ating frequency can be seen from this equation. Accepting
larger values of ΔIL allows the use of lower value induc-
tors, but results in greater core loss in the inductor, greater
ESR loss in the output capacitor, and larger output ripple.
Generally, highest efficiency operation is obtained at low
operating frequency with small ripple current.
A reasonable starting point for setting the ripple current
is approximately 0.35A
P-P
. Note that the largest ripple
current occurs at the highest VIN. To guarantee the ripple
current does not exceed a specified maximum, the induc
-
tance should be chosen according to:
L=VOUT
f • ΔIL(MAX)
⎛
⎝
⎜⎞
⎠
⎟1– VOUT
VIN(MAX)
⎛
⎝
⎜⎞
⎠
⎟
The LT7101 contains a fast, average current limit loop
that limits the DC output current to a value determined by
the voltage on the ICTRL pin. (See Average Output Current
Limit and Monitor section for details.) However, some
applications may experience inductor current transients
that are limited by the peak current limit comparator,
which tracks nominally 0.53A above the average current
limit set point. To avoid saturation, choose an inductor
with a saturation current ISAT such that:
ISAT >
V
ICTRL
– 0.4
0.77 +
0.68A
This enables the use of an inductor with a current rating
that fits the needs of a given application. If the average
output current limit is set to the default value of 1.11A,
then an inductor with ISAT > 1.9A is required. However, if
the average current limit is set to 0.6A (VICTRL=0.89V),
then an inductor with ISAT > 1.4A may be used. Note that
if there is a varying voltage on the ICTRL pin, always use
the highest value present on ICTRL when calculating the
required inductor saturation current. See Average Output
Current Limit and Monitor section for details on setting
the average current limit.
If fixed VOUT operation is selected using the VPRG1 and
VPRG2 pins, the RIND pin can be left floating, but only if
the inductance value is chosen according to Table3. Since
the RIND pin resistor indicates the inductance value being
used, the LT7101 will automatically assume an inductance
value as shown in Table3 when this pin is left floating.
These inductance values will provide an inductor ripple
current that is approximately 30% to 40% of the full load
current. If the nominal value of the inductance used differs
by more than 10% from the values specified in Table3,
a resistor must be placed on the RIND pin to indicate this
value.
Table3. Required Inductor Values with RIND Pin Floating
FIXED VOUT
REQUIRED INDUCTANCE VALUE (RIND = FLOAT)
f = 300kHz f = 1MHz f = ADJ
1.2V 10μH 3.3µH L = 3.1/f
1.8V 15µH 4.7µH L = 4.6/f
2.5V 22µH 6.8µH L = 6.7/f
3.3V 33µH 10µH L = 9.9/f
3.6V 33µH 10µH L = 9.9/f
5V 47µH 15µH L = 14.6/f
12V 100µH 33µH L = 31.5/f
15V 100µH 33µH L = 31.5/f
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. Actual core loss is independent of core size for a
fixed inductor value but is very dependent on the induc-
tance selected. As the inductance increases, core loss
decreases. Unfortunately, increased inductance requires
more turns of wire leading to increased copperloss.
Ferrite designs exhibit very low core loss and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core materials saturate hard, meaning the induc-
tance collapses abruptly when the peak design current is
exceeded. This collapse will result in an abrupt increase
in inductor ripple current, so it is important to ensure the
core will not saturate.
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RIND Resistor Selection
The resistor on the RIND pin is used to indicate to the
LT7101 what inductance value is being used. This is
required for the internal reconstruction of the inductor
current waveform and to set the DC gain of the current
loop. Once the inductor value is selected, the R
IND
pin
resistor is chosen according to:
RIND =
1
3.3 •L
If fixed VOUT operation is selected using the VPRG1 and
VPRG2 pins, the RIND pin can be left floating, but only if
the inductance value is chosen according to Table3. Do
not leave the R
IND
pin floating when adjustable V
OUT
mode
is selected. If the RIND pin is left floating and adjustable
VOUT mode selected (VPRG1 and VPRG2 are both floating),
the LT7101 will detect this as a fault condition and will
not operate.
The allowable current range on the RIND pin is between
8μA and 220μA, which means that:
2.5 ≤ f • L ≤ 67
In practice, the above constraint does not normally affect
the choice of inductor value.
CIN Selection
The input capacitance, C
IN
, is needed to filter the trap
-
ezoidal current at the drain of the top power MOSFET. CIN
should be sized to do this without causing a large variation
in input voltage. In addition, the input capacitor needs
to have a very low ESR and must be rated to handle the
worst-case RMS input current of:
I
RMS =
I
OUT(MAX)
2
Note that capacitor manufacturers’ ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor, or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may be paralleled to meet size or height
requirements in the design. Due to the high operating
frequency of the LT7101, ceramic capacitors can also be
used for CIN. In many applications, an X7R capacitor of
4.7μF or greater is a suitable choice. Always consult the
manufacturer if there is any question.
The input capacitor, CIN, should be placed as close as
possible to the VIN pins, with a low inductance connec-
tion to the PGND (paddle) of the IC. In addition to a larger
bulk capacitor, a smaller case-size (0603 or 0805) ceramic
decoupling capacitor can be placed closer to the VIN pins
to reduce EMI.
Using an LC Input Filter
Figure4.
7101 F04
VIN
VIN
ZOUT
ZIN
RD
SW
LT7101
CD
CF
LF
CBULK
OPTIONAL
Input Filter with Optional Damping Network
For high voltage applications, it can be costly to use bulk
capacitance that is rated to handle the required RMS input
current. Moreover, when using a simple capacitor to filter
the AC input current, it is difficult to determine exactly
where this AC current is flowing when a power supply is
placed into a larger system. To avoid these issues, an LC
filter can be used on the power supply input as shown in
Figure4. This keeps the higher AC currents contained in
a relatively small and inexpensive capacitor (CF) whose
RMS current rating is known to be adequate. Choose an
LC filter such that:
1
2πL
F
C
F
<
f
5
where f is the switching frequency. This will attenuate the
RMS input current by a factor of approximately 5X, greatly
alleviating the RMS input requirements of the larger bulk
capacitor CBULK. The filter inductor LF should have a satu-
ration current of at least:
ISAT(LF) ≥1.3 •
V
OUT
I
OUT(MAX)
VIN(MIN)
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In order to keep the ripple voltage at the filter output to
a reasonable level, choose a value of LF and CF that also
satisfies:
LF
CF
<2.9 • VRIPPLE
IOUT(MAX)
+RESR
2
⎛
⎝
⎜⎞
⎠
⎟
where VRIPPLE is the desired ripple voltage at the output
of the input filter and RESR is the ESR of capacitor CF. A
reasonable target for VRIPPLE is 3% of nominal VIN.
When using an LC input filter, the output impedance of the
LC filter (ZOUT) must never be greater in magnitude than
the input impedance looking into the power stage of the
DC/DC converter (ZIN). This is necessary to avoid ringing
and possible voltage loop instability. In many applications,
this condition is naturally satisfied because the ESR of
the bulk input capacitance CBULK is high enough to lower
the Q of the LC input filter. In some situations, a series
damping network must be added as shown in Figure4.
In order to provide critical damping, choose CD and RD
according to:
CD≈4 •CF
RD=LF
C
F
COUT Selection
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔVOUT) is approximated by:
ΔVOUT ≈ΔILESR +1
8 • f • C
OUT
⎛
⎝
⎜⎞
⎠
⎟
where f is the operating frequency, C
OUT
is the output
capacitance and ΔIL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage.
If internal voltage loop compensation is selected, than a
minimum amount of bulk output capacitance is required to
ensure stability. Loop stability can be checked by viewing
the load transient response. See Internal/External Loop
Compensation in the Applications Information section.
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now avail-
able in small case sizes. Their high voltage rating and low
ESR make them ideal for switching regulator applications.
However, due to the self-resonant and high-Q character-
istics of some types of ceramic capacitors, care must be
taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input,
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
VIN input. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part. For a more detailed discussion, refer to Application
Note 88.
When choosing the input and output ceramic capaci-
tors select the X5R or X7R dielectric formulations. These
dielectrics provide the best temperature and voltage
characteristics for a given value and size. In addition,
be careful to consider the voltage coefficient of ceramic
capacitors when choosing the value and case size. Most
ceramic capacitors lose 50% or more of their rated value
when used near their rated voltage.
INTVCC Regulators
The LT7101 features two separate internal low dropout
linear regulators (LDO) that supply power at the INTVCC
pin from either the VIN pin or the EXTVCC pin depending
on the EXTVCC pin voltage available. INTVCC powers the
internal MOSFET gates and most of the internal circuitry.
The VIN LDO and the EXTVCC LDO each regulate INTVCC
to 3.5V.
The INTVCC pin must be bypassed to ground with a mini-
mum of 1μF ceramic capacitor, placed as close as possible
to the INTVCC pin. In order to minimize noise and ripple
on the INTV
CC
supply, always use a capacitor C
VCC
on
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INTV
CC
that is at least 10x greater than the capacitor C
BST
from BOOST to SW:
CVCC > 10 • CBST
Be careful to account for the voltage coefficient of ceramic
capacitors when choosing the value and case size. Many
ceramic capacitors lose 50% or more of their rated value
when used near their rated voltage.
For high VIN applications it is advantageous to tie EXTVCC
to V
OUT
(bootstrapping), as this will improve efficiency
and reduce power dissipation in the V
IN
LDO. This can
be done with any V
OUT
voltage between 3.3V and 40V.
Alternatively, the EXTV
CC
pin can be tied to any DC voltage
between 3.3V and 40V that is capable of delivering the
required INTVCC bias current, which varies with switch-
ing frequency and operating mode. At full-load operation,
which is the worst case, the INTVCC bias current is given
approximately by:
IINTVCC =3.5mA +1nC 4+
V
IN
31
⎛
⎝
⎜⎞
⎠
⎟• f
When EXTVCC is not present, the LDO timeout feature lim-
its the junction temperature rise due to the V
IN
LDO power
dissipation. See Soft-Start and LDO Regulator Timeout
section for more information.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC left open (or grounded). This will cause
INTVCC to be powered from the VIN LDO resulting in an
efficiency penalty at high input voltages.
2. EXTVCC connected directly to the output voltage VOUT.
This is the normal connection for a 3.3V to 40V regula-
tor and provides the highest efficiency.
3. EXTVCC connected to an external supply. If an external
supply is available in the 3.3V to 40V range, it may
be used to power EXTVCC providing it can supply the
required INTVCC current. Operating with EXTVCC > VIN
is allowed.
4. EXTVCC connected to an output-derived boost or
charge-pump network. For 2.5V and other low voltage
buck regulators, efficiency gains can still be realized by
connecting EXTVCC to an output-derived voltage that
has been boosted to greater than 3.05V.
Most applications will simply tie EXTVCC to VOUT for
high efficiency bootstrapping. In this configuration, with
Burst Mode operation selected, the no-load VIN current
in regulation can be calculated using:
IVIN =1µA +VOUT
0.8 • V
IN
•VOUT
R
D
+VOUT
6MΩ+8µA
⎛
⎝
⎜⎞
⎠
⎟
where RD is the total resistance of the feedback resistive
divider from VOUT to GND. In fixed output voltage mode,
where VOUT is programmed using VPRG1 and VPRG2, use
RD = VOUT/1.25µA. For adjustable VOUT mode (Figure5),
use RD = R1 +R2.
Topside MOSFET Driver Supply (CBST)
The boost capacitor, CBST, on the Functional Diagram
is used to create a voltage rail above the applied input
voltage, VIN. Specifically, the boost capacitor is charged
through an internal MOSFET switch to a voltage equal
to approximately INTVCC each time the bottom power
MOSFET is turned on. The charge on this capacitor is then
used to supply the required current during the remainder
of the switching cycle. When the top MOSFET is turned
on, the BOOST pin voltage will be equal to approximately
VIN + 3.5V. For most applications a 0.1μF, X7R ceramic
capacitor will provide adequate performance.
The LT7101 also contains an internal charge pump that
supplies a small amount of current to the BOOST pin to
allow for continuous operation at 100% duty cycle. This
charge pump is adequate to support internal biasing
needs and to keep the top MOSFET fully enhanced. Note
that the total external leakage on the BOOST pin (includ-
ing the CBST capacitor leakage) must be less than 4µA to
ensure continuous operation at 100% duty cycle.
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Output Voltage Programming
The VPRG1 and VPRG2 pins provide a great deal of flexibility
in programming the output voltage of the power supply.
Floating both pins selects adjustable VOUT mode. In this
mode, the output is programmed using external resistors
on the VFB pin as shown in Figure5. The regulated output
voltage is determined by:
VOUT =1V 1+R1
R2
⎛
⎝
⎜⎞
⎠
⎟
Figure5.
R1 CFF
R2
7101 F05
V
OUT
VFB
LT7101
Setting the Output Voltage
Place resistors R1 and R2 very close to the VFB pin to
minimize PCB trace length and noise. Great care should
be taken to route the VFB trace away from noise sources,
such as the inductor or the SW trace. To improve frequency
response, a feedforward capacitor (CFF) may be used.
If either VPRG1 or VPRG2 is tied to SGND or INTVCC, then
fixed output voltage mode is selected. In this mode,
precision internal resistor dividers are used to program
the output voltage to one of eight fixed voltage levels as
shown in Table4.
Table4. Output Voltage Programming
VPRG1 VPRG2 VOUT
INTVCC INTVCC 1.2V
OPEN INTVCC 1.8V
SGND SGND 2.5V
SGND OPEN 3.3V
SGND INTVCC 3.6V
OPEN SGND 5V
INTVCC OPEN 12V
INTVCC SGND 15V
OPEN OPEN Adjustable 1V to VIN
To avoid excessively large values of R1 in high output
voltage applications (VOUT ≥ 15V), a combination of external
and internal resistors can be used to set the output voltage.
Figure6 shows the LT7101 with the VFB pin configured for
a 15V fixed output with an external divider to generate a
higher output voltage. The internal 12M resistance appears
in parallel with R2, and the value of R2 must be adjusted
accordingly. R2 should be chosen to be less than 400k to
keep the output voltage variation less than 1% due to the
tolerance of the LT7101’s internal resistor.
Figure6.
7101 F06
VFB
INTVCC
VOUT
LT7101
VPRG1
VPRG2
R1
R2
15V
11.2M
800k
1V
Setting the Output Voltage with External and
Internal Resistors
RUN Pin and Overvoltage/Undervoltage Lockout
The LT7101 has a low power shutdown mode controlled
by the RUN pin. Pulling the RUN pin below 0.7V puts
the LT7101 into a low quiescent current shutdown mode
(IQ = 0.7µA). When the RUN pin is greater than VRUN(ON)
= 1.21V, switching is enabled. Figure7 shows examples
of configurations for driving the RUN pin from logic. Note
that the RUN pin can only be directly controlled as shown
in Figure7 for applications with VOUT≤6V. See Operating
at VOUT>6V section for more information.
Figure7.
RUN
SUPPLY LT7101
RUN
7101 F07
4.7M
1k
VIN
LT7101
1k
RUN Pin Interface to Logic
LT7101
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The RUN and OVLO pins can alternatively be configured
as precise undervoltage (UVLO) and overvoltage (OVLO)
lockouts on the V
IN
supply with a resistor divider from V
IN
to ground. A simple resistor divider can be used as shown
in Figure8 to meet specific VIN voltage requirements. For
applications with VOUT>6V that require direct RUN pin
control, an open-drain pull-down must be used as shown
in Figure8. See Operating at VOUT>6V section for more
information.
Figure8.
RUN
7101 F08
R3
VIN
LT7101
R4
R5
OVLO
4.7V
OPTIONAL
OPTIONAL
Adjustable UV and OV Lockout
The current that flows through the R3-R4-R5 divider will
directly add to the shutdown, sleep, and active current
of the LT7101, and care should be taken to minimize the
impact of this current on the overall efficiency of the appli-
cation circuit. Resistor values in the MΩ range may be
required to keep the impact on quiescent shutdown and
sleep currents low. To pick resistor values, the sum total
of R3 + R4 + R5 (RTOTAL) should be chosen first based on
the allowable DC current that can be drawn fromVIN. The
individual values of R3, R4 and R5 can then be calculated
from the following equations:
R5 =RTOTAL •
1.21V
RISING VIN OVLO THRESHOLD
R4 =RTOTAL •1.21V
RISING VIN UVLO THRESHOLD – R5
R3 =R
TOTAL
–R5 – R4
For applications that do not need a precise external OVLO,
the OVLO pin should be tied directly to ground. The RUN
pin in this type of application can be used as an external
UVLO using the previous equations with R5 = 0Ω.
Similarly, for applications that do not require a precise
UVLO, the RUN pin can be tied to VIN. In this configura-
tion, the UVLO threshold is limited to the internal VIN
UVLO thresholds as shown in the Electrical Characteristics
table. The resistor values for the OVLO can be computed
using the previous equations with R3 = 0Ω. Be aware that
the OVLO pin cannot be allowed to exceed its absolute
maximum rating of 6V. To keep the voltage on the OVLO
pin from exceeding 6V, the following relation should be
satisfied:
VIN(MAX) •R5
R3+R4+R5
⎛
⎝
⎜⎞
⎠
⎟<6V
If this equation cannot be satisfied in the application, con-
nect a 4.7V Zener diode between the OVLO pin and ground
to clamp the OVLO pin voltage as shown in Figure8.
Note that in applications with VOUT>6V, additional
constraints on the use of the RUN pin also apply. See
Operating at VOUT>6V section for more information.
Soft-Start and LDO Regulator Timeout
An internal soft-start ramp of 1.2ms will limit the ramp
rate of the output voltage to prevent excessive input cur-
rent during start-up. If a longer ramp time is desired,
a capacitor can be placed from the SS pin to ground.
The value of the soft-start capacitor needed to provide a
desired soft-start time (tSS) can be calculated by:
CSS = tSS • 10µA
Note that the value of CSS must be greater than 12nF to
provide a soft-start time that is greater than the internal
default of tSS(INT) = 1.2ms.
The LT7101 also includes an LDO regulator timeout
feature that is essential for limiting die temperature rise
due to power dissipation in the VIN LDO. This is useful
in high V
IN
applications, where EXTV
CC
is tied to V
OUT
,
and VOUT gets shorted to ground. When this occurs, the
VIN LDO will take over the INTVCC current, resulting in
potentially high power dissipation (>1W) in the VIN LDO
pass device. If this condition persists, an LDO timeout
occurs, disabling the switching of the top and bottom
MOSFETs. Once switching is disabled, the INTVCC bias
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current is reduced to approximately 4mA, thereby lower-
ing the power dissipation in the LDO. After a long restart
delay, a soft-start is again initiated.
The LDO regulator timeout and restart time are dependent
on the length of the soft-start time selected, tSS, which
is either the default of 1.2ms or set externally. After the
soft-start is complete, a timeout will occur if EXTVCC < 3V
for a time given by:
tTIMEOUT = 1.4 • tSS
At this point, switching will stop, and a restart delay timer
will be activated. A restart will occur after a delay given by:
tRESTART = 46 • tSS
As long as this condition persists (EXTVCC < 3V), the
LT7101 will continue operating in a hiccup restart mode.
This yields an effective duty cycle of power dissipation
in the VIN LDO of approximately 2%, which prevents any
significant rise in die temperature. Note, however, that
the LDO regulator timeout feature precludes operation
in constant output current mode in applications where
EXTVCC is tied to VOUT, and VOUT < 3V.
If the LDO regulator timeout feature is not needed, the
SS pin can be tied to INTVCC through a 75k resistor. This
will prevent the LDO timeout from occurring, allowing
continuous operation even with EXTVCC = 0V. The addi-
tion of this resistor also affects the soft-start time when
an external capacitor is used (the internal 1.2ms soft-
start is not affected). With SS tied to INTV
CC
through 75k,
the value of the soft-start capacitor needed to provide a
desired soft-start time (tSS) can be calculated by:
CSS(75k) = tSS • 51µA
If the LDO regulator timeout feature is defeated, care
must be taken to avoid exceeding the maximum junc-
tion temperature. See Thermal Considerations for more
information.
Phase-Locked Loop and Frequency Synchronization
The LT7101 contains a phase-locked loop (PLL) to syn-
chronize the internal oscillator to an external clock source
that is connected to the PLLIN/MODE pin. Once synchro-
nized, the turn-on of the top MOSFET is aligned to the
rising edge of the synchronizing signal.
The typical capture range of the PLL is from 160kHz to
2.3MHz, with a guarantee over all manufacturing varia-
tions to be between 200kHz and 2MHz. The typical input
clock thresholds on the PLLIN/MODE pin are 1.5V rising
and 1.1V falling, and this input is TTL compatible.
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired syn-
chronization frequency. Before synchronization, the VCO’s
filter voltage is prebiased to a level that corresponds to the
frequency set by the FREQ pin. Consequently, the PLL only
needs to make minor adjustments to achieve phase-lock
and synchronization. Although it is not required that the
free-running frequency be near external clock frequency,
doing so will prevent the operating frequency from pass-
ing through a large range of frequencies as the PLL locks.
After the PLL has locked to an external clock, if the exter-
nal clock is stopped, the LT7101 will immediately detect
this condition and momentarily prevent the PLL from
adjusting the loop, so that the internal oscillator continues
operating at the external clock frequency. After approxi-
mately 9μs, the LT7101 will detect a loss of SYNC, and
the oscillator frequency will return to the level set by the
FREQ pin. This feature enables smooth transitions into
and out of synchronization.
The CLKOUT pin supplies a reference clock that is helpful
for synchronizing other switching circuits to the LT7101
switching frequency. The output high level of this signal is
equal to INTVCC (3.5V typical), and the rising edge of the
CLKOUT signal is 180° out of phase with respect to the
top MOSFET turn-on. This makes it easy to synchronize
two LT7101 converters and operate them out of phase to
minimize input current, or to use two LT7101’s together
for a higher current, 2-Phase converter. See 2-Phase
Operation Section.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LT7101 is capable of turning on the top MOSFET.
It is determined by internal timing delays. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to avoid this by operating at
a sufficiently low switching frequency. See Setting the
Operating Frequency section.
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If the duty cycle does fall below what can be accommo-
dated by the minimum on-time, the LT7101 will begin to
skip cycles, regardless of the mode of operation (burst
pulse-skipping or forced continuous modes). The output
voltage will continue to be regulated, but the ripple voltage
and current will increase.
The minimum on-time for the LT7101 is approximately
40ns. If the duty cycle drops below the minimum on-time
limit in this situation, cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
Operating at VOUT>6V
The LT7101 contains circuitry to automatically charge the
boost supply for the topside MOSFET driver by activating
the bottom MOSFET for short periods of time when nec-
essary. This feature ensures the boost supply is always
charged and ready under all operating conditions. When
starting up or operating near dropout (VIN≈VOUT) and
with VOUT>6V, however, care must be taken to avoid the
accumulation of negative inductor current that can arise
from the automatic boost charging circuitry.
There are two optional configurations allowable for appli-
cations with VOUT>6V.
Option 1: 100% Duty Cycle Allowed. Use this option when
operation at or near 100% duty cycle is required or if RUN
pin control is not needed. For this option, the RUN pin
must be tied to the VIN pin directly and operation at higher
switching frequencies is prohibited. The switching fre-
quency set point must be limited to a maximum value of
f ≤ 550kHz
and the inductance value must be a minimum of
L≥4.5µH•(VOUT–3)–10µH
Option 2: High Switching Frequency Allowed. Use this
option when either high switching frequency or RUN pin
control is needed. In this case, operation near drop-out
is prohibited and a RUN pin divider is required to set the
minimum operating input voltage to a value of:
V
IN,MIN ≥
V
OUT
1– f • 260ns
As shown in Figure9, this constraint on minimum operat-
ing input voltage establishes a maximum allowable duty
cycle that varies with switching frequency. Note that the
minimum operating input voltage can be set to any volt-
age higher than the value for VIN,MIN given above.
Figure9.
FREQUENCY (MHz)
0.2
1
2
30
40
50
60
70
80
90
100
MAXIMUM DUTY CYCLE (%)
7101 F09
Maximum Allowable Duty Cycle vs Frequency
for VOUT>6V and Option 2 Configuration
When selecting the resistors for the RUN pin divider to
limit the minimum operating V
IN
voltage, use the RUN pin
falling threshold minimum value of 1.06V. This ensures
that the LT7101 will not operate below the minimum oper-
ating input voltage requirement given in Option 2 above.
Referring to Figure8, calculate the RUN pin divider resis-
tors as:
R4 =RTOTAL •1.06V
VIN,MIN
R3 =R
TOTAL
–R4 –R5
The rising VIN voltage at which the LT7101 will begin
switching is determined by the rising RUN pin threshold
of 1.21V (1.26V maximum). The typical rising V
IN
turn-on
voltage is therefore:
VIN(ON,TYP)=1.14•VIN,MIN
Note that for direct RUN pin control in all applications
with VOUT>6V, an open-drain pull-down must be used in
conjunction with a RUN pin divider as shown in Figure8.
Since Option 2 allows for higher switching frequency
and smaller size inductors, this option is preferred for
LT7101
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applications with VOUT≥16V or where space is lim-
ited, provided that high duty cycle operation is not
required. Option1 is a better choice for applications with
6V<VOUT<16V or whenever high duty cycle operation
is required, provided that RUN pin control is not needed.
Internal/External Loop Compensation
The LT7101 provides the option to use a fixed internal
loop compensation network to reduce both the required
external component count and design time. The internal
loop compensation network can be selected by connect-
ing the ITH pin to the INTVCC pin. Internal compensation
can be used at any switching frequency from 200kHz
to 2MHz. The LT7101 automatically adjusts the internal
compensation based on switching frequency to maintain
an optimum transient response. When using internal
compensation, a reasonable starting point for the mini-
mum amount of output capacitance necessary for stability
can be found as the greater of either 4.7µF or COUT defined
by the equation:
COUT ≈40
f • VOUT
where COUT is the capacitance value at voltage VOUT,
noting that most ceramic capacitors lose 50% or more
of their rated value when used at their rated voltage.
Alternatively, the user may choose specific external loop
compensation components to optimize the main control
loop transient response as desired. External loop com-
pensation is chosen by simply connecting the desired
network to the ITH pin.
Typical compensation component values are shown in
Figure10. For a 500kHz application, for example, an R-C
(RCOMP and CCOMP in Figure10) network of 2.2nF and
10kΩ provides a good starting point. The bandwidth of
the loop increases with decreasing C. If R is increased by
the same factor that C is decreased, the zero frequency
will be kept the same, thereby keeping the phase the same
in the most critical frequency range of the feedback loop.
A 10pF bypass capacitor (CBYP in Figure10) on the ITH
pin can be used to filter out high frequency coupling
from stray board capacitance. In addition, a feedforward
capacitor, CF F, can be added to improve the high frequency
response, as previously shown in Figure5. Capacitor CFF
provides phase lead by creating a high frequency zero
with R1 which improves the phase margin.
Figure10.
ITH
7101 F10
RCOMP
10k
RCOMP
2.2nF
LT7101
SGND
CBYP
Compensation Components
Checking the Transient Response
The regulator loop response can be checked by observing
the response of the system to a load step. When con-
figured for external compensation, the availability of the
ITH pin not only allows optimization of the control loop
behavior but also provides a DC-coupled and AC-filtered
closed-loop response test point. The DC step, rise time,
and settling behavior at this test point reflect the sys-
tem’s closed loop response. Assuming a predominantly
second order system, the phase margin and/or damping
factor can be estimated by observing the percentage of
overshoot seen at this pin with a high impedance, low
capacitance probe.
The ITH external components shown in Figure10 will pro-
vide an adequate starting point for most applications. The
series R-C filter sets the pole-zero loop compensation.
The values can be modified to optimize transient response
once the final PC layout is done and the particular out-
put capacitor type and value have been determined. The
specific output capacitors must be selected because their
various types and values determine the loop feedback
factor, gain, and phase. An output current pulse of 20%
to 100% of full load current, with a rise time of 1μs to
10μs, will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
LT7101
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When observing the response of VOUT to a load step, the
initial output voltage step may not be within the bandwidth
of the feedback loop. As a result, the standard second
order overshoot/DC ratio cannot be used to estimate
phase margin. The output voltage settling behavior is
related to the stability of the closed-loop system and will
demonstrate the actual overall supply performance. For
a detailed explanation of optimizing the compensation
components, including a review of control loop theory,
refer to Analog Devices Application Note 76.
In some applications, severe transients can be caused
by switching in loads with large (>1μF) supply bypass
capacitors. The discharged input capacitors are effectively
put in parallel with COUT, causing a rapid drop in VOUT.
No regulator can deliver enough current to prevent this
output droop if the switch connecting the load has low
resistance and is driven quickly. The solution is to limit
the turn-on speed of the load switch driver. A Hot Swap™
controller is designed specifically for this purpose and
usually incorporates current limit, short-circuit protection
and soft-start functions.
Average Output Current Limit and Monitor
The LT7101 contains a fast and accurate average cur-
rent limit that can be externally controlled and monitored.
This fast current loop is useful in applications such as the
charging of batteries and capacitors or current program-
ming in LEDs and laser diodes. The average output current
limit is set using the ICTRL pin. The voltage on the ICTRL
pin sets the average output current limit accordingto:
ILIM(AVG) =
V
ICTRL
– 0.4
0.811
This allows for the average current limit to be set anywhere
between 0A and 1.11A by adjusting the I
CTRL
voltage from
0.4V to 1.3V. If the ICTRL voltage is less than 0.4V, it will
be internally limited to 0.4V, so that the average output
current cannot be set to a negative value. Likewise, the
ICTRL voltage is internally limited to 1.3V if the ICTRL pin
is floated or tied to a voltage greater than 1.3V.
An internal 20μA pull-up on this pin allows a single resis-
tor to SGND to be used to set the voltage. To program
a particular fixed average output current limit ILIM(AVG),
chose a resistor according to:
RICTRL =
0.811•I
LIM(AVG) +
0.4
20µA
Since the LT7101 uses average current mode control with
a high speed inner current loop, there are no stability
concerns when operating in constant current mode. In
addition, the LT7101 automatically optimizes the cur-
rent loop based on switching frequency and operating
condition. The unity-gain bandwidth of the average cur-
rent loop is maintained at approximately 1/3 of the switch-
ing frequency. This enables the LT7101 to respond to
changes in the ITH pin voltage on a nearly cycle-by-cycle
basis. This is orders of magnitude faster than competing
solutions, where a slow, average current loop is placed
outside of the voltage regulation loop.
When operating in constant current mode with a low volt-
age on I
CTRL
, the inductor current will become discontinu-
ous. In this situation, the LT7101 average current loop
maintains good output current programming accuracy
down to no load.
The average output current can be monitored at the IMON
pin. This pin generates a voltage that represents a filtered
version (f
C
= 10kHz) of the internally sensed inductor cur-
rent. The DC voltage on IMON normally varies between
0.4V and 1.3V, corresponding to an average output cur-
rent between 0A and 1.11A according to:
VIMON = 0.811 • IOUT(AVG) + 0.4
The IMON voltage may momentarily be less than 0.4V or
greater than 1.3V, but eventually is limited to these levels
by the average current loop. During SLEEP, this pin is held
at 0.4V. To ensure stability of the internal I
MON
buffer,
place a 2k or higher resistor in series with any capacitive
load that is greater than 100pF.
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2-Phase Operation
The LT7101 supports parallel operation in order to pro-
duce a higher output current. 2-Phase operation is easily
implemented as shown in Figure11. In this figure, the
upper LT7101 operates as the master, and handles volt-
age regulation. The lower (slave) LT7101 operates as a
current source, the value of which is determined by the
demand of the average current loop of the master. The
slave is synchronized 180° out of phase with respect to
the master, dramatically reducing input current ripple.
Tying the SS pins together insures that the both parts
start up and shut down together. Tying the VFB pin of the
slave to INTVCC while floating VPRG1 and VPRG2 activates
slave mode. This disables the 20µA pull-up current on the
ICTRL pin and causes the ITH voltage of the slave to track
with the I
CTRL
pin voltage. When operating in slave mode,
a resistor on the RIND pin is always required to indicate the
inductor value being used. Place a 10pF cap from ITH to
GND on the slave to eliminate any high frequency noise.
Figure11.
7101 F11
VFB
VFB
EXTVCC
SW
L1
VIN
VIN
VPRG1
VPRG2
RIND
ITH
CIN2
COUT
V
OUT
VIN
SS
SS
ITH
INTVCC
EXTVCC
INTVCC
LT7101
(MASTER)
CLKOUT
ICTRL
PLLIN/MODE
SW
L2
LT7101
(SLAVE)
CCRC
CBYP
1µF
1µF
CIN1
10pF
RIND
Connections for 2-Phase Operation
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 +…)
where L1, L2, etc. are the individual loss terms as a per-
centage of input power.
Although all dissipative elements in the circuit produce
losses, three main sources account for the majority of
the losses in the LT7101: 1) I2R loss, 2) INTVCC regula-
tor current, 3) transition losses and other system losses.
1. I2R loss is calculated from the DC resistance of the
internal switches, R
SW
, and external inductor, R
L
. In
continuous current mode, the average output current
will flow through inductor L but is chopped between
the internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both the top and bottom MOSFET’s RDS(ON) and the
duty cycle (DC) as follows:
RSW = (RDS(ON)TOP) • (DC) +(RDS(ON)BOT) • (1 – DC)
The RDS(ON) for both the top and bottom MOSFETs
can be obtained from the Typical Performance
Characteristics curves. Thus to obtain I2R loss:
I2R Loss = IOUT2 • (RSW + RL)
2. The internal LDO supplies the power to the INTVCC
rail. The total power loss here is the sum of the gate
drive losses and quiescent current losses from the
control circuitry. Each time a power MOSFET gate is
switched from low to high to low again, a packet of
charge, dQ, moves from VIN to ground. The resulting
dQ/dt is a current out of INTVCC that is typically much
larger than the DC control bias current. In continuous
current mode, I
GATECHG
= f(Q
T
+ Q
B
), where Q
T
and
Q
B
are the gate charges of the internal top and bot-
tom power MOSFETs and f is the switching frequency.
For estimation purposes, (QT + QB) on the LT7101 is
approximately 4nC, although it varies with VIN voltage.
To calculate the total power loss from the LDO load,
simply add the gate charge current and quiescent cur-
rent and multiply byvoltage:
PLDO =3.5mA +1nC 4+V
IN
31
⎛
⎝
⎜⎞
⎠
⎟• f
⎡
⎣
⎢⎤
⎦
⎥• VX
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where VX = VIN if the VIN LDO is active or VX = EXTVCC
if the EXTVCC LDO is active. Supplying INTVCC from an
output-derived power source through EXTV
CC
will scale
the VIN current required for the gate drive and con-
trol circuits by a factor of (duty cycle)/(efficiency). For
example, in a 48V to 5V application, 10mA of INTVCC
current results in approximately 1.2mA of VIN current.
This reduces the mid-current loss from 10% or more
to less than 2%.
3. Transition losses apply only to the top MOSFET, and
can become significant when operating at high input
voltages (typically 40V or greater) and high frequency.
Transition losses can be estimated from:
Transition Loss = (47pF) • (VIN + 13)2 • (IOUT + 1.3) • f
Other hidden losses such as copper trace resistances,
and internal battery resistances can account for additional
efficiency degradations in the overall power system. Other
losses, including diode conduction losses during dead
time and inductor core losses, generally account for less
than 2% total additional loss.
Fault Conditions: Short-Circuit Protection
The architecture of the LT7101 provides inherent protec-
tion against short-circuit conditions, without the need for
folding back either the output current or the oscillator fre-
quency. A given switching cycle is skipped only as needed
to satisfy the high-speed average current loop, resulting
in a brick-wall style current limit without any foldback or
hiccups in the operation down to VOUT = 0V. Note, how-
ever, that hiccup restart will occur due to the LDO timeout
feature unless EXTVCC > 3V, or this feature is disabled by
tying the SS pin to INTVCC through a 75k resistor.
While the average current loop is extremely fast, a failsafe
peak current limit (IPK) comparator has also been incor-
porated to ensure that the inductor cannot exceed a safe
level, even momentarily. In practice, the peak current limit
comparator is only needed when there is an abnormal
voltage on the average current amplifier output filter and
a short-circuit is applied. In this case, the peak current
limit comparator may be needed for a few cycles while
the average current amplifier filter settles.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self-heating on chip,
the overtemperature shutdown circuitry will shut down
the LT7101. When the junction temperature exceeds
approximately 171°C, the overtemperature circuitry dis-
ables all switching to eliminate internal power dissipation.
Once the junction temperature drops back to approxi-
mately 155°C, the LT7101 turns back on and re-initiates
a start-up. Long term overstress (TJ > 150°C) should be
avoided as it can degrade the performance or shorten the
life of the part.
Thermal Considerations
The LT7101 requires the exposed package backplane
metal (PGND) to be well soldered to the PC board to pro-
vide both electrical and thermal contact. This gives the
QFN package exceptional thermal properties, compared
to other packages of similar size. In many applications,
the LT7101 does not generate much heat due to its high
efficiency and low thermal resistance package backplane.
However, in applications in which the LT7101 is running at
a high ambient temperature and high input voltage or high
switching frequency, the generated heat may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 171°C, both power
switches will be turned off until temperature decreases
by approximately 16°C.
Thermal analysis should always be performed by the user
to ensure the LT7101 does not exceed the maximum junc-
tion temperature.
The temperature rise is given by:
TRISE = PD • qJA
where PD is the power dissipated in the chip and qJA is
the thermal resistance from the junction of the die to the
ambient environment. Consider the example in which an
LT7101 is operating with I
OUT
= 1A, V
IN
= 50V, f = 500kHz,
VOUT = EXTVCC = 5V, and an ambient temperature of 70°C.
From the Typical Performance Characteristics section the
RDS(ON) of the top switch at this temperature is found to
be nominally 760mΩ while that of the bottom switch is
LT7101
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nominally 410mΩ yielding an equivalent power MOSFET
resistance RSW of:
RSW = (760mΩ)(0.1) + (410mΩ)(0.9) = 445mΩ
From the previous section, the I2R losses are (12)(0.445)
= 445mW. INTVCC power dissipation is:
P
LDO =3.5mA +1nC 4+50
31
⎛
⎝
⎜⎞
⎠
⎟•500k
⎡
⎣
⎢⎤
⎦
⎥• 5 =32mW
The transition losses are approximately:
(47pF) • 632 • (1 + 1.3) • 500kHz = 215mW
so the total power dissipation is approximately 0.69W.
The QFN 5mm × 6mm package junction-to-ambient ther-
mal resistance, qJA, is approximately 38°C/W. Therefore,
the junction temperature of the regulator operating in a
70°C ambient temperature is approximately:
TJ = 0.69W • 38°C/W + 70°C = 96°C
which is below the maximum junction temperature
of150°C.
Design Example
As a design example, consider the LT7101 in an appli-
cation with the following specifications: VIN = 36V to
72V, VOUT = 12V, IOUT(MAX) = 1A, IOUT(MIN) = 20mA, and
switching is enabled between 30V and 90V on VIN.
First, because efficiency is important at both high and low
load currents, Burst Mode operation at 500kHz is chosen.
The RFREQ resistor for 500kHz switching frequency is cal-
culated using RFREQ = f/40 + 7.5k = 20k. In addition, the
PLLIN/MODE pin is tied to ground to select Burst Mode
operation.
Next, since the output voltage is available as a prepro-
grammed value (V
PRG1
= INTV
CC
and V
PRG2
= OPEN),
the R
IND
pin is left floating, and the inductor value chosen
according to Table3 as 63μH. Suitable inductors with a
nominal value of 68μH and ISAT ≥ 1.8A are available from
multiple manufacturers, so a value of L = 68μH is chosen.
Next, COUT = 10μF is selected based on the minimum
needed for internal voltage loop compensation and out-
put ripple. CIN is sized to handle a ripple current IRMS =
IOUT/2 = 0.5A. A low ESR, 100V, 4.7μF ceramic capacitor
is chosen. The INTVCC decoupling capacitor is chosen as
1μF and the BOOST capacitor is chosen as 0.1μF. EXTV
CC
is tied to VOUT to minimize loss in the INTVCC LDO.
The undervoltage and overvoltage lockout requirements
on VIN can be satisfied with a resistor divider from VIN
to the RUN and OVLO pins (refer to Figure8). Choose
R3+R4+R5 = 2.5MΩ to minimize the loading on VIN.
Calculate R3, R4 and R5 as follows:
R5 =
1.21V • 2.5M
Ω
90V =33.6k
R4 =1.21V • 2.5MΩ
30V – R5 =67.2k
R3 =2.5MΩ–R5 –R4 =2.4MΩ
Figure12.
7101 F12
VFB
EXTVCC
PLLIN/MODE
BOOST
SW
VIN
RUN
2.2M
4.7µF
VOUT
12V
1A
VIN
36V TO 72V
62k
20k
30.9k
OVLO
VPRG1
ITH
LT7101
FREQ
INTVCC
PGNDSGND
0.1µF
1µF
10µF
68µH
36V to 72V Input to 12V Output, 1A Regulator
LT7101
33
Rev. 0
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APPLICATIONS INFORMATION
Since specific resistor values in the MΩ range are gen-
erally less available, it may be necessary to scale R3,
R4, and R5 to a standard value of R3. For this example,
choose R3 = 2.2M and scale R4 and R5 by 2.2M/2.4M.
Then, R4 = 61.6k and R5 = 30.8k. Choose standard values
of R3 = 2.2M, R4 = 62k, and R5 = 30.9k. Note that the
falling thresholds for the UVLO and OVLO will be 8% and
5% lower than the rising thresholds, or 27.6V and 85.5V
respectively.
Since this application has VOUT>6V and RUN pin control
is desired, Option 2 configuration is selected. The mini-
mum allowed operating input voltage is given by:
VIN,MIN ≥
12
1– 0.13
=13.8V
This requirement is easily satisfied by the RUN pin divider,
which limits operation to input voltage greater than 27.6V.
Internal compensation is selected by tying the ITH pin to
INTVCC. The ICTRL pin is left floating to select a current
limit of 1.11A, and the SS pin is left floating to select
the internal soft-start ramp of 1.2ms. Figure12 shows a
complete schematic for this design example.
Low EMI PCB Layout
The LT7101 is designed specifically to minimize EMI/EMC
emissions by reducing the parasitic inductance associ-
ated with the internal power switches. For optimal perfor-
mance, the LT7101 requires two VIN bypass capacitors.
As shown in Figure13, place a smaller 0.1μF capacitor
(C
IN1
, 0805 case) as close as possible to the LT7101,
and a 4.7μF or larger capacitor (CIN2, 1210 case) just
beyond CIN1.
For the lowest possible EMI/EMC emissions, an input filter
is required. See Figure17 for an example and the LT7101
demo board guide for additional details as well as PCB
design files.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LT7101 (Refer to Figure13):
1. Place the input capacitors, inductor and output capaci-
tors on the same side of the circuit board, and make
their connections on that layer where possible. Place
a local, unbroken ground plane under the application
circuit on the layer closest to the surface layer.
2. Connect capacitor CIN1 to VIN and PGND as close to
the pins as possible. These capacitors provide the AC
current to the internal power MOSFETs. The (–) plate
of CIN1 should be closely connected to PGND and the
(–) plate of COUT.
3. When using adjustable VOUT mode, the resistor divider
(R1 and R2) must be connected between the (+) plate
of C
OUT
and a ground line terminated near SGND. Place
these resistors near the IC, keeping the VFB trace short
and away from either SW or BOOST.
4. Keep sensitive components (attached to RUN, OVLO,
RIND, ITH, VFB, FREQ, IMON and ICTRL) away from the
SW and BOOST pins. Make the SW and BOOST nodes
as small as possible.
5. Use either one ground plane or segregate the signal
and power grounds into two planes connected through
a single, low resistance trace to a common reference
point, typically at the exposed pad.
6. Flood all unused areas on all layers with copper tied
to the exposed pad in order to reduce the temperature
rise of the LT7101.
LT7101
34
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure14. High Efficiency 5V to 100V Input to 5V/1A Output Step-Down Regulator
7101 F14
VFB
EXTVCC
VPRG2
VPRG1
f
sw = 300kHz
L: WURTH 7447714470
FREQ
BOOST
SW
VIN
RUN
4.7µF
100V
X7R
1µF
V
OUT
5V
1A
V
IN
5V TO 100V
OVLO
PLLIN/MODE
LT7101
INTVCC
ITH
PGNDSGND
47µF
6.3V
X5R
0.1µF 47µH
Figure13. Example PCB Layout
VFB
EXTVCC
PLLIN/MODE
BOOST
SW
VIN
RUN
R3
CIN1
VOUT
COUT
VIN
R4
RFREQ
R2
R1
R5
OVLO
FREQ VPRG1
ITH
LT7101
INTVCC
PGNDSGND
CBST
CVCC
L1
7101 F13
VIAS TO GROUND PLANE
VIAS TO OUTPUT SUPPLY (VOUT)
VIAS TO INTVCC
OUTLINE OF GROUND PLANE
L1
CIN1
CIN2
CBST
CVCC
RFREQ
VIN
GND
R1 R2
R5
R4
R3
COUT
VOUT
CIN2
LT7101
35
Rev. 0
For more information www.analog.com
Figure15. High Efficiency 12V to 100V Input to 12V/1A Output Step-Down Regulator
7101 F15
VFB
EXTVCC
fsw = 300kHz
L: WURTH 7447714101
FREQ
BOOST
SW
VIN
RUN
4.7µF
100V
X7R
1µF
V
OUT
12V
1A
V
IN
12V TO 100V
OVLO
PLLIN/MODE
LT7101
INTVCC
ITH
PGNDSGND
22µF
25V
X5R
0.1µF100µH
VPRG1
VPRG2
TYPICAL APPLICATIONS
Figure17. Low EMI 5V to 100V Input to 5V/1A Output Step-Down Regulator
Figure16. High Efficiency 4.4V to 100V Input to 3.3V/1A Output Step-Down Regulator
7101 F16
VFB
EXTVCC
f
sw = 300kHz
L: WURTH 7447714330
FREQ
BOOST
SW
VIN
RUN
4.7µF
100V
X7R
1µF
VOUT
3.3V
1A
V
IN
4.4V TO 100V
OVLO
PLLIN/MODE
LT7101
INTVCC
ITH
PGNDSGND
100µF
6.3V
X5R
0.1µF 33µH
VPRG1
VPRG2
7101 F17
VFB
EXTVCC
fSW = 400kHz
C1: SUNCON 125HVH10M
L2: COILCRAFT XAL6060-333ME
FB1, FB2: MURATA BLM31PG121SN1
VPRG2
FREQ
BOOST
SW
VIN
RUN
4.7µF
100V
X7R
0.1µF
100V
X7R
4.7µF
100V
X7R
1µF
VOUT
5V
1A
VIN
5V TO 100V
OVLO
LT7101
INTVCC
ITH
PLLIN/MODE
RIND
PGNDSGND
47µF
6.3V
X6S
0.1µF 33µH, L2
17.8k
VPRG1
BEAD
FB2
BEAD
FB1
0.22µF
100V
X7R
4.7µF
100V
X7R
C1
10µF
125V
8.87k
+
LT7101
36
Rev. 0
For more information www.analog.com
TYPICAL APPLICATIONS
1.1A, 6-Cell SLA Battery Charger with Charge Termination
VFB
fsw = 500kHz
L: COILCRAFT XFL6060-473ME
OVLO
FREQ
BOOST
SW
VIN
RUN
2.2µF
100V
X7R
1µF
100k
VBAT
13.5V TO 14.3V
1.1A
V
IN
18V TO 72V
PLLIN/MODE
LT7101
INTVCC
IMON
EXTVCC
ITH
PGNDSGND
10µF
25V
X7R
0.1µF47µH
RIND
7101 TA03
20k6.49k R1
115k
115k 10k
IN–
V+
IN+
REF
40.2k
0.1%
100k
0.1%
402k
0.1%
OUT
HYST
V–GND
LTC1440
1.74M
1.1A CHARGING CURRENT
14.3V TOPPING CHARGE VOLTAGE WITH 0.15A TERMINATION
13.4V FLOAT VOLTAGE
R1 = 125k (ITERM + 0.61)
0.96 – ITERM
VPRG1
VPRG2
LT7101
37
Rev. 0
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
5.00 ±0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
1
6
5
4
3
2
10
19
28
27
24
23
22
21
20
1118
363029 32 33 34 35
BOTTOM VIEW—EXPOSED PAD
1.25 REF
0.8 REF
6.00 ±0.10
R = 0.125
TYP
0.25 ±0.05
3.60
±0.10
2.60
±0.10
(UHE36(26)) QFN 0714 REV Ø
0.50 BSC
3.60
±0.05
2.60
±0.05
0.75 ±0.05
0.00 – 0.05
0.200 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.50 REF
0.40 ±0.10
1.75 REF
0.70 ±0.05
0.50 BSC
3.00 REF
4.10 ±0.05
5.50 ±0.05
5.10 ±0.05
6.50 ±0.05
0.25 ±0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 × 45°
CHAMFER
R = 0.10
TYP
UHE Package
Variation: UHE36(26)
36-Lead Plastic QFN (5mm × 6mm)
(Reference LTC DWG # 05-08-1983 Rev Ø)
PACKAGE DESCRIPTION
LT7101
38
Rev. 0
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ANALOG DEVICES, INC. 2019
04/19
www.analog.com
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4.4V to 32V Input to 3.3V/1A Output, 2MHz Automotive
Supply with Overvoltage Lockout and 100V Input Tolerance
Radiated EMI Performance (CISPR25) Radiated
Emission Test with Class 5 Peak Limits
7101 TA04a
VFB
EXTVCC
fSW = 2MHz
OVERVOLTAGE LOCKOUT AT 36V
L: COILCRAFT XFL4020-472ME
FB1, FB2: MURATA BLM31PG601SN1
C1: SUNCON 125HVH10M
VPRG1
FREQ
BOOST
SW
VIN
RUN
4.7µF
100V
X7R
0.1µF
100V
X7R
4.7µF
100V
X7R
×3
1µF
64.9k
2MHz CLK
OR GND
VOUT
3.3V
1A
VIN
4.4V TO 32V
(100V MAX)
OVLO
LT7101
INTVCC
ITH
PLLIN/MODE
RIND
PGNDSGND
10µF
6.3V
X5R
0.1µF 4.7µH
60.4k
57.6k
1.74M
VPRG2
BEAD
FB1
BEAD
FB2
4.7µF
100V
X7R
0.22µF
100V
X7R
+
14V
IN
TO 3.3V
OUT
AT 1A
f
SW
= 2MHz
VERTICAL POLARIZATION
CLASS 5 PEAK LIMIT
LT7101
FREQUENCY (MHz)
0
100
200
300
400
500
600
700
800
900
1000
0
10
20
30
40
50
AMPLITUDE (dBµV/m)
7101 TA04b