LT7101 105V, 1A Low EMI Synchronous Step-Down Regulator with Fast Current Programming DESCRIPTION FEATURES Wide VIN Range: 4.4V to 105V (110V Abs Max) nn Ultralow EMI/EMC Emissions: CISPR 25 Compliant nn 2A I When Regulating 48V to 3.3V Q IN OUT nn Fast and Accurate Output Current Programming and Monitoring with No External RSENSE nn Brick Wall Current Limit nn Low Minimum On-Time: 35ns nn Wide V OUT Range: 1V to VIN nn 100% Maximum Duty Cycle Operation nn Programmable Fixed Frequency: 200kHz to 2MHz nn Eight, Pin-Selectable Fixed (1.2V to 15V) or Adjustable Output Voltages nn Selectable Continuous, Pulse-Skipping, or Low Ripple Burst Mode(R) Operation at Light Loads nn PLL Synchronization to External Clock nn EXTV CC LDO Powers Chip from VOUT = 3.3V to 40V nn OPTI-LOOP(R) or Fixed Internal Compensation nn Input and Output Overvoltage Protection nn Thermally Enhanced (5mm x 6mm) QFN Package nn APPLICATIONS The LT(R)7101 is a high efficiency, monolithic synchronous step-down DC/DC converter utilizing a constant frequency, average current mode control architecture. It operates from an input voltage range of 4.4V to 105V and provides an adjustable regulated output voltage from 1V to VIN while delivering up to 1A of output current. The LT7101 features high frequency operation and a low minimum on-time that reduce inductor size and enable constant-frequency operation even at very high stepdown ratios. In addition, the LT7101 achieves the lowest possible dropout voltage with 100% maximum duty cycle operation. During light load operation, converter efficiency and output ripple can be optimized by selecting Burst Mode, pulse-skipping or forced continuous operation. The LT7101 includes accurate, high speed average current programming and monitoring without the need for an external sense resistor. Additional features include a bypass LDO to maximize efficiency, fixed or adjustable output voltage and loop compensation, and a wide array of protection features to enhance reliability. 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Battery Chargers and CC/CV Supplies nn Automotive and Military Systems nn Industrial, Avionics and Heavy Equipment nn Medical Instruments and Telecommunication Systems nn TYPICAL APPLICATION Efficiency vs Load Current 5V to 105V Input to 5V/1A Output Step-Down Regulator 100 95 VIN 4.7F RUN 90 BOOST 0.1F LT7101 ICTRL VFB OVLO EXTVCC VPRG2 IMON SGND CURRENT MONITOR VOUT 5V 1A 47F ITH PLLIN/MODE FREQ 47H SW 85 80 75 70 65 VIN = 12V VIN = 24V VIN = 48V VIN = 72V 60 INTVCC PGND EFFICIENCY (%) VIN 5V TO 105V fSW = 300kHz FIGURE 14 CIRCUIT 55 1F 50 0.1 7101 TA01a 1 10 100 LOAD CURRENT (mA) 1000 7101 TA01b Rev. 0 Document Feedback For more information www.analog.com 1 LT7101 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) 36 35 VIN VIN VIN PGND PGND TOP VIEW 32 31 30 27 BOOST 26 SW RUN 3 25 SW 24 SW PGND 37 SGND 6 OVLO 7 RIND 8 21 INTVCC ITH 9 20 EXTVCC 19 VPRG2 VFB 10 VPRG1 IMON SS ICTRL PGOOD CLKOUT FREQ 11 12 13 14 15 16 17 18 PLLIN/MODE VIN Supply Voltage.....................................-0.3V to 110V INTVCC, (BOOST-SW) Voltages..................... -0.3V to 6V BOOST Voltage..........................................-0.3V to 110V RUN Voltage..............................................-0.3V to 110V VFB, PGOOD Voltages................................. -0.3V to 16V EXTVCC Voltage...........................................-0.3V to 41V RIND, VPRG1, VPRG2 Voltages.................. -0.3V to INTVCC ICTRL, SS Voltages................................. -0.3V to INTVCC FREQ, ITH, PLLIN/MODE, OVLO Voltages..... -0.3V to 6V Operating Junction Temperature Range (Notes 2, 3, 4) LT7101E, LT7101I............................... -40C to 125C LT7101H............................................. -40C to 150C LT7101MP........................................... -55C to 150C Storage Temperature Range................... -65C to 150C UHE36(26) PACKAGE 36-LEAD (5mm x 6mm) PLASTIC QFN TJMAX = 150C, JA = 38C/W, JC = 5C/W EXPOSED PAD (PIN 37) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT7101EUHE#PBF LT7101EUHE#TRPBF 7101 36-Lead (5mm x 6mm) Plastic QFN -40C to 125C LT7101IUHE#PBF LT7101IUHE#TRPBF 7101 36-Lead (5mm x 6mm) Plastic QFN -40C to 125C LT7101HUHE#PBF LT7101HUHE#TRPBF 7101 36-Lead (5mm x 6mm) Plastic QFN -40C to 150C LT7101MPUHE#PBF LT7101MPUHE#TRPBF 7101 36-Lead (5mm x 6mm) Plastic QFN -55C to 150C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 Rev. 0 For more information www.analog.com LT7101 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C. (Note 2) VIN = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 105 V 4.64 4.39 V V 105 V Main Regulator and Voltage Loop VIN Operating Input Voltage Range VIN(UVLO) VIN Undervoltage Lockout VIN Rising VIN Falling VOUT Operating Output Voltage Range (Note 9) IQ VIN Input DC Supply Current (Note 8) Pulse-Skipping Mode VFB = 1.04V, EXTVCC = 3.3V VFB = 1.04V, EXTVCC = 0V 200 4.4 A mA Sleep Mode VFB = 1.04V, EXTVCC = 3.3V VFB = 1.04V, EXTVCC = 0V 1.0 9.0 A A Shutdown RUN = 0V 0.7 1.5 A VIN Input Current In Regulation Figure14 Circuit, VIN = 48V, IOUT = 500A Figure16 Circuit, VIN = 48V, IOUT = 0A 64 2 75 A A Regulated Feedback Voltage 1.000 1.200 1.800 2.500 3.300 3.600 5.000 12.00 15.00 2 1.25 1.52 1.010 1.218 1.827 2.537 3.350 3.654 5.075 12.24 15.30 10 1.6 V V V V V V V V V nA A mS 35 55 ns VFB 4.4 gm Error Amplifier gm (Note 5) ITH Voltage = 0.5V to 1.2V, VIN = 4.5V to 105V VPRG1 = VPRG2 = FLOAT VPRG1 = VPRG2 = INTVCC VPRG1 = FLOAT, VPRG2 = INTVCC VPRG1 = VPRG2 = SGND VPRG1 = SGND, VPRG2 = FLOAT VPRG1 = SGND, VPRG2 = INTVCC VPRG1 = FLOAT, VPRG2 = SGND VPRG1 = INTVCC, VPRG2 = FLOAT VPRG1 = INTVCC, VPRG2 = SGND VPRG1 = VPRG2 = FLOAT VPRG1 or VPRG2 Tied to SGND or INTVCC ITH = 1V, Sink/Source = 5A (Note 5) tON,MIN Minimum Controllable ON-Time (Note 7) Feedback Input Bias Current l l 4.36 4.11 4.50 4.25 1.0 l l l l l l l l l 0.990 1.182 1.770 2.455 3.234 3.528 4.900 11.75 14.70 l RDS(ON)TOP Top Switch On-Resistance 580 m RDS(ON)BOT Bottom Switch On-Resistance 300 m Current Control and Monitoring ILIM(AVG) Average Output Current Limit (Note 6) ICTRL = FLOAT ICTRL = 0.58V IPK Top Switch Peak Current Limit ICTRL = FLOAT ICTRL = 0.58V VIMON Current Monitor Output Voltage (Note 6) ISW = 1.0A ISW = 0.25A ICTRL Pin Pull-Up Current VICTRL = 0.5V 1.00 0.16 1.11 0.22 1.21 0.28 A A 1.43 0.63 1.64 0.75 1.85 0.87 A A 1.13 0.552 1.21 0.603 1.29 0.654 V V l 18 20 22 A l 8 11 15 A l l Start-Up and Shutdown ISS Soft-Start Charge Current SS = 0V tSS(INT) Internal Soft-Start Ramp Time SS = FLOAT VFB(OV) Feedback Overvoltage Protection Relative to Regulated VFB VRUN(ON) RUN Pin ON Threshold VRUN Rising VRUN Falling 1.2 l l 10 13 % 1.16 1.06 1.21 1.11 100 1.26 1.16 V V mV -10 0 10 nA RUN Pin Hysteresis RUN Pin Leakage Current RUN = 1.5V ms 7 Rev. 0 For more information www.analog.com 3 LT7101 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C. (Note 2) VIN = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOV(R) OVLO Pin Rising Threshold VOVLO Rising l MIN TYP MAX 1.16 1.21 1.26 OVLO Pin Hysteresis OVLO Pin Leakage Current 65 OVLO = 1.5V -10 0 UNITS V mV 10 nA Bias Regulators and Housekeeping VEXTVCC INTVCC Undervoltage Lockout INTVCC Rising INTVCC Falling EXTVCC Switchover Voltage EXTVCC Rising EXTVCC Falling 3.00 2.80 V V 3.03 2.95 3.10 3.00 3.17 3.07 V V Regulated INTVCC Voltage from VIN 3.37 3.50 3.63 V Regulated INTVCC Voltage from EXTVCC 3.37 3.50 3.63 V 15 % l l Oscillator and Phase-Locked Loop Programmable Frequency Accuracy RFREQ = 12.5k (200kHz) to 57.5k (2MHz) PLLIN/MODE = 0V l -15 fLOW Low Preset Frequency VFREQ = 0V; PLLIN/MODE = 0V l 270 300 330 kHz fHIGH High Preset Frequency VFREQ = INTVCC; PLLIN/MODE = 0V l 0.9 1.0 1.1 MHz Synchronizable Frequency PLLIN/MODE = External Clock l 200 2000 kHz PLLIN/MODE Input High Level for Clocking PLLIN/MODE = External Clock l 2.0 PLLIN/MODE Input Low Level for Clocking PLLIN/MODE = External Clock l V 0.8 V PGOOD Output PGOOD Voltage Low IPGOOD = 1mA PGOOD Leakage Current VPGOOD = 12V 0.3 PGOOD Trip Level VFB with Respect to Set Regulated Voltage -1 VFB Ramping Positive 7 10 -13 -10 Hysteresis Hysteresis Delay for Reporting a Fault Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT7101E is guaranteed to meet specifications from 0C to 85C with specifications over the -40C to 125C operating junction temperature range assured by design, characterization and correlation with statistical process controls. The LT7101I is guaranteed over the -40C to 125C operating junction temperature range, the LT7101H is guaranteed over the -40C to 150C operating junction temperature range, and the LT7101MP is tested and guaranteed over the -55C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD * qJAC/W) 4 V 1 A 13 % 2.5 VFB Ramping Negative TPG 0.5 % -7 % 2.5 % 24 s Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. The overtemperature protection level is not production tested. Note 5: The LT7101 is tested in a feedback loop that servos VFB to a voltage near the internal reference voltage to obtain the specified ITH voltage. Note 6: The Average Output Current Limit, the Top Switch Peak Current Limit and the Current Monitor Output Voltage are measured in a test circuit that simulates operation in a typical application. Note 7: The minimum controllable on-time is measured in a test mode. (See Minimum ON-Time Considerations in the Applications Information section.) Note 8: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 9: See Operating at VOUT>6V in Applications Information section for details about additional design constraints that may apply. Rev. 0 For more information www.analog.com LT7101 TYPICAL PERFORMANCE CHARACTERISTICS Burst Mode Efficiency at 5VOUT 100 95 fSW = 300kHz FIGURE 15 CIRCUIT 90 85 85 75 70 65 VIN = 12V VIN = 24V VIN = 48V VIN = 72V 55 50 0.1 1 10 100 LOAD CURRENT (mA) EFFICIENCY (%) 90 80 80 75 70 65 VIN = 24V VIN = 48V VIN = 72V VIN = 100V 60 55 50 0.1 1000 1 10 100 LOAD CURRENT (mA) 7101 G01 100 fSW = 300kHz FIGURE 14 CIRCUIT 50 30 10 100 LOAD CURRENT (mA) 60 100 10 100 LOAD CURRENT (mA) 40 30 30 1000 10 100 LOAD CURRENT (mA) 1000 VIN = 12V VIN = 24V VIN = 48V VIN = 72V 10 Forced Continuous Mode Efficiency at 12VOUT 100 fSW = 300kHz FIGURE 15 CIRCUIT 1000 Forced Continuous Mode Efficiency at 3.3VOUT fSW = 300kHz FIGURE 16 CIRCUIT 90 80 70 60 50 VIN = 24V VIN = 48V VIN = 72V VIN = 100V 40 30 100 LOAD CURRENT (mA) 7101 G06 EFFICIENCY (%) EFFICIENCY (%) VIN = 12V VIN = 24V VIN = 48V VIN = 72V 60 40 80 50 70 50 VIN = 24V VIN = 48V VIN = 72V VIN = 100V 90 80 1000 fSW = 300kHz FIGURE 16 CIRCUIT 90 7101 G05 fSW = 300kHz FIGURE 14 CIRCUIT 60 10 100 LOAD CURRENT (mA) Pulse-Skipping Mode Efficiency at 3.3VOUT 70 30 1000 70 1 80 40 Forced Continuous Mode Efficiency at 5VOUT 90 VIN = 12V VIN = 24V VIN = 48V VIN = 72V 7101 G03 100 7101 G04 100 50 0.1 1000 fSW = 300kHz FIGURE 15 CIRCUIT 50 VIN = 12V VIN = 24V VIN = 48V VIN = 72V 40 65 55 80 EFFICIENCY (%) EFFICIENCY (%) 80 60 70 Pulse-Skipping Mode Efficiency at 12VOUT 90 70 75 7101 G02 Pulse-Skipping Mode Efficiency at 5VOUT 90 80 60 EFFICIENCY (%) 100 fSW = 300kHz FIGURE 16 CIRCUIT 95 85 60 EFFICIENCY (%) Burst Mode Efficiency at 3.3VOUT 100 90 EFFICIENCY (%) EFFICIENCY (%) Burst Mode Efficiency at 12VOUT 100 fSW = 300kHz FIGURE 14 CIRCUIT 95 TA = 25C, unless otherwise noted. 10 100 LOAD CURRENT (mA) 7101 G07 1000 7101 G08 70 60 50 VIN = 12V VIN = 24V VIN = 48V VIN = 72V 40 30 10 100 LOAD CURRENT (mA) 1000 7101 G09 Rev. 0 For more information www.analog.com 5 LT7101 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Input Voltage VOUT = 5V, Burst Mode Operation VIN Input Current in Regulation vs Input Voltage Efficiency vs Frequency at 1A 100 10 90 90 8 85 85 EFFICIENCY (%) ILOAD = 0.5A 95 FIGURE 14 CIRCUIT 80 75 70 65 55 50 80 75 70 65 ILOAD = 1A ILOAD = 500mA ILOAD = 100mA ILOAD = 10mA 60 0 20 40 60 INPUT VOLTAGE (V) 80 VIN = 12V VIN = 24V VIN = 48V VIN = 72V 60 55 50 0.2 100 1 FREQUENCY (MHz) 1.4 1.002 1.001 1.000 0.999 0.998 0.997 0.996 -25 5 35 65 95 TEMPERATURE (C) 125 1.2 ICTRL = 1.3V OR FLOAT 0.8 ICTRL = 0.94V 0.6 0.4 ICTRL = 0.58 0.2 0 Peak Current Limit vs Temperature 1.4 40 60 VIN VOLTAGE (V) 80 1.65 1.60 -25 5 35 65 95 TEMPERATURE (C) 1.0 0.8 0.6 125 155 0.2 7101 G16 5 35 65 95 TEMPERATURE (C) 125 155 7101 G15 2.0 0.8 VIN = 24V VIN = 48V VIN = 72V 0 -25 Output Current Monitor Error vs Average Output Current 1.0 0.4 VICTRL = 0.76V 0.4 7101 G14 FIGURE 14 CIRCUIT 0.6 1.55 VICTRL = 1.3V OR FLOAT 0 -55 100 1.2 IMON VOLTAGE (V) PEAK CURRENT LIMIT (A) 1.75 6 20 FIGURE 14 CIRCUIT 1.2 Output Current Monitor vs Average Output Current VICTRL = 1V 1.50 -55 1.4 1.0 0 155 1.70 10 20 30 40 50 60 70 80 90 100 VIN VOLTAGE (V) Average Output Current vs Temperature FIGURE 14 CIRCUIT 7101 G13 1.80 0 7101 G12 AVERAGE OUTPUT CURRENT (A) 1.003 0.995 -55 2 Average Output Current vs VIN, ICTRL AVERAGE OUTPUT CURRENT (A) REGULATED FEEDBACK VOLTAGE (V) 1.004 4 7101 G11 Regulated Feedback Voltage vs Temperature VPRG1 = FLOAT VPRG2 = FLOAT VOUT = 3.3V ILOAD = 0 FIGURE 16 CIRCUIT 6 0 2 7101 G10 1.005 VIN SUPPLY CURRENT (A) fSW = 300kHz FIGURE 14 CIRCUIT 95 IMON VOLTAGE ERROR (%) 100 EFFICIENCY (%) TA = 25C, unless otherwise noted. 0.2 0.4 0.6 0.8 1.0 AVERAGE OUTPUT CURRENT (A) 1.2 7101 G17 FIGURE 14 CIRCUIT 1.0 0 -1.0 -2.0 VIN = 72V VIN = 48V VIN = 24V 0 0.2 0.4 0.6 0.8 1.0 AVERAGE OUTPUT CURRENT (A) 1.2 7101 G18 Rev. 0 For more information www.analog.com LT7101 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, unless otherwise noted. Top and Bottom Switch Resistance vs Temperature Minimum On-Time vs Temperature 1350 50 1200 45 900 MINIMUM ON-TIME (ns) RESISTANCE (m) 1050 TOP SWITCH 750 600 BOTTOM SWITCH 450 40 35 30 300 150 -55 -25 5 35 65 95 TEMPERATURE (C) 125 25 -55 155 -25 5 35 65 95 TEMPERATURE (C) 125 7101 G19 155 7101 G20 Quiescent Input Current vs Input Voltage Oscillator Frequency vs Temperature 10.0 3 1 0 -1 FREQ = GND (300kHz) FREQ = 12.5k (200kHz) FREQ = 57.5k (2MHz) FREQ = INTVCC (1MHz) -2 -3 -55 -25 5 35 65 95 TEMPERATURE (C) 125 155 VIN SUPPLY CURRENT (A) CHANGE IN FREQUENCY (%) SLEEP, EXTVCC = GND 2 8.0 6.0 4.0 2.0 SHUTDOWN 0.0 7101 G21 VIN Quiescent Current vs Temperature VIN SUPPLY CURRENT (uA) 25 15 30 45 60 75 VIN VOLTAGE (V) 20 BURST MODE 500mA/DIV 15 PULSE-SKIPPING MODE 500mA/DIV SLEEP FORCED CONTINUOUS MODE 500mA/DIV 10 5 SHUTDOWN -25 5 35 65 95 TEMPERATURE (C) 90 105 7101 G22 Inductor Current at Light Load VIN = 100V EXTVCC = GND 0 -55 0 125 155 10s/DIV VIN = 48V ILOAD = 200A FIGURE 14 CIRCUIT 7101 G24 7101 G23 Rev. 0 For more information www.analog.com 7 LT7101 TYPICAL PERFORMANCE CHARACTERISTICS Load Step Burst Mode Operation TA = 25C, unless otherwise noted. Load Step Forced Continuous Mode Load Step Pulse-Skipping Mode VOUT 100mV/DIV VOUT 100mV/DIV VOUT 100mV/DIV IL 500mA/DIV IL 500mA/DIV IL 500mA/DIV 40s/DIV LOAD STEP = 50mA TO 500mA VIN = 48V FIGURE 14 CIRCUIT 7101 G25 40s/DIV LOAD STEP = 50mA TO 500mA VIN = 48V FIGURE 14 CIRCUIT SW Node Waveform at Full Load 7101 G26 40s/DIV LOAD STEP = 50mA TO 500mA VIN = 48V FIGURE 14 CIRCUIT Synchronization to External Clock 7101 G27 Start-Up from Shutdown VOUT 2V/DIV VSW 20V/DIV IL 500mA/DIV EXTERNAL CLOCK ON PLLIN/MODE 1V/DIV 50ns/DIV VIN = 48V ILOAD = 1A FIGURE 14 CIRCUIT 7101 G28 VRUN 5V/DIV 15s/DIV VIN = 48V ILOAD = 500mA FIGURE 14 CIRCUIT 7101 G29 Output Current Programming Current Loop Step Response Short-Circuit and Recovery VICTRL 500mV/DIV VOUT 2V/DIV IL 250mA/DIV IL 500mA/DIV 100s/DIV VIN = 48V PULSE-SKIPPING MODE FIGURE 14 CIRCUIT 7101 G31 40s/DIV VICTRL = 0.76V TO 1.12V PULSE VIN = 48V, VOUT = 4V FIGURE 14 CIRCUIT 7101 G32 200s/DIV VIN = 48V Burst Mode OPERATION FIGURE 14 CIRCUIT ICTRL VOLTAGE TO INDUCTOR CURRENT GAIN (A/V) VSW 10V/DIV 7101 G30 ICTRL Voltage to Inductor Current Gain vs Frequency 1.4 1.2 1.0 BW = 93kHz 0.8 0.6 0.4 0.2 VIN = 24V VOUT = 4V RICTRL = 40.2k IOUT(AVG) = 500mA fSW = 300kHz FIGURE 14 CIRCUIT 0 0.1 1 10 FREQUENCY (kHz) 100 300 7101 G33 8 Rev. 0 For more information www.analog.com LT7101 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, unless otherwise noted. Radiated EMI Performance (CISPR25 Radiated Emission Test with Class 5 Peak Limits) 50 VERTICAL POLARIZATION AMPLITUDE (dBV/m) 40 30 20 10 CLASS 5 PEAK LIMIT LT7101 0 0 100 200 300 400 500 600 FREQUENCY (MHz) 700 800 FIGURE 17 CIRCUIT 48VIN TO 5VOUT AT 1A fSW = 400kHz 900 1000 7101 G34 PIN FUNCTIONS RUN (Pin 3): Run Control Input. Holding this pin below 1.1V shuts off the switching regulator. Holding this pin below 0.7V reduces the quiescent current to approximately 0.7A. Place a resistor divider between VIN and this pin to use as an undervoltage lockout. Tie this pin to VIN to always enable the LT7101. voltage mode is selected using the VPRG1 and VPRG2 pins. If VPRG1 and VPRG2 are both floating, then a resistor from RIND to SGND must be used. SGND (Pin 6): Signal Ground. ITH (Pin 9): Error Amplifier Output and Switching Regulator Compensation Point. Place compensation components between the ITH pin and SGND. Tie this pin to INTVCC for fixed internal compensation. OVLO (Pin 7): Overvoltage Shutdown Input. If the voltage on this pin exceeds 1.21V, then the switching regulator is shut down and the SS pin is internally grounded. Tie this pin to SGND to allow operation with VIN up to 105V. VFB (Pin 10): Regulator Feedback Input. When set to adjustable mode, use an external resistor divider between the regulator output voltage and the VFB pin. For fixed output voltage mode, tie VFB directly to the regulator output. RIND (Pin 8): Sets the current used to create an internal ramp that replicates the inductor current up-slope for low duty cycle operation. This pin generates a voltage that varies with the switching frequency. Place a resistor to SGND on this pin equal to 1/(3.3 * L) to set the internal ramp current. This pin can be left floating if fixed output FREQ (Pin 11): The frequency control pin for the internal VCO. Connect this pin to SGND for 300kHz operation or to INTVCC for 1MHz operation. Place a resistor to SGND on this pin to set the operating frequency between 200kHz and 2MHz. Minimize the capacitance on this pin if Burst Mode operation is used. This pin sources 40A. Rev. 0 For more information www.analog.com 9 LT7101 PIN FUNCTIONS PLLIN/MODE (Pin 12): External Synchronization Input to Phase Detector and Burst Mode Control Input. When an external clock is applied to this pin, the phase-locked loop will force the rising edge of the SW signal to be synchronized with the rising edge of the external clock, and the LT7101 operates in forced continuous mode. When not synchronizing to an external clock, this input determines how the LT7101 operates at light loads. Tie this pin to SGND or float to select Burst Mode operation or to INTVCC to force continuous inductor current operation. Tie this pin to INTVCC through a 100k resistor to select pulse-skipping operation. This pin sinks 10A to SGND. CLKOUT (Pin 13): Output clock signal available to synchronize additional regulators for parallel operation. The rising edge of CLKOUT is 180 out of phase with respect to the rising edge of the SW pin. The output level swings from SGND to INTVCC. PGOOD (Pin 14): Open-Drain Power Good Output. The VFB pin is monitored to ensure that the output is in regulation. When the output is not in regulation, the PGOOD pin is pulled low. SS (Pin 15): Soft-Start and Regulator Timeout Input. The voltage on the SS pin limits the regulated output voltage when the SS voltage is less than 1V. An internal 10A pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. Leave this pin floating to use the internal 1.2ms soft-start ramp. The SS pin also serves as a timeout to disable switching if the EXTVCC voltage is too low. To disable the regulator timeout feature, tie a 75k resistor between SS and INTVCC. See Soft-Start and LDO Regulator Timeout in the Applications Information section. ICTRL (Pin 16): Programs the Average Output Current in Constant Current Mode. The voltage on this pin determines the maximum ITH voltage, which in turn sets the average output current in constant-current mode. The peak current limit tracks 0.53A above the average current limit set point. Tie this pin to a voltage between 0.4V and 1.3V to program the average output current to a value between 0A and 1.11A. An internal 20A pull-up on this 10 pin allows a single resistor to SGND to be used to set the voltage. Float this pin to set the average output current to 1.11A and the peak current limit to 1.64A. IMON (Pin 17): Average Output Current Monitor. This pin generates a voltage between 0.4V and 1.3V that corresponds to an average output current between 0A and1.11A. VPRG1, VPRG2 (Pins 18,19): Output Voltage Programming Pins. These pins set the regulator to adjustable output mode or to fixed output mode. Floating both pins allows the output to be programmed through the VFB pin using external resistors, regulating VFB to the 1V reference. Tying one of these pins to SGND or INTVCC while the other is tied to SGND, INTVCC or floating programs the output to one of eight fixed output voltages. See Output Voltage Programming in the Applications Information section. EXTVCC (Pin 20): External Power Input to an Internal LDO that Generates INTVCC. This LDO supplies INTVCC power from EXTVCC, bypassing the internal LDO powered from VIN whenever EXTVCC is between 3.1V and 40V. If EXTVCC is not used, the regulator timeout feature must be disabled by tying a 75k resistor between SS and INTVCC. See INTVCC Regulations in the Applications Information section. INTVCC (Pin 21): Output of the Internal LDO regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to PGND with a 1F to 4.7F ceramic capacitor. SW (Pins 24, 25, 26): SW Node connection from the internal MOSFET power switches to the output inductor. BOOST (Pin 27): Bootstrapped Supply to the High Side Floating Gate Driver. Connect a 0.1F ceramic capacitor between the BOOST and SW pins. VIN (Pins 30, 31, 32): Power Input Supply. This is the power input to the integrated high side MOSFET switch as well as the input to the internal LDO that generates INTVCC voltage. Decouple this pin with a capacitor to PGND. PGND/Exposed Pad (Pin 35, 36, 37): Power Ground. Connect to power ground plane. The exposed pad must be connected to PCB ground for rated electrical and thermal performance. Rev. 0 For more information www.analog.com LT7101 FUNCTIONAL DIAGRAM VOUT CVCC VIN ICTRL OVLO - 1.2V RIND IMON + EXTVCC INTVCC 20A VIN SHDN CVIN + ITH CLAMP - RUN EN 3.5V LDO EN 3.5V LDO + ITH - 3.1V 10A VOSC SHDN INTVCC SS 2 * BG SOFT-START 1V VOUT + + + - dt INTERNAL ITH INTERNAL VFB (VFBI) VFB R2 SW ITHMIN ERROR AMP R1 UV + 0.9V VOSC AVG CURR GM AMP CCA OV VPRG1 1.1V - + VOUT SELECT VRAMP ISENSE RECONSTRUCTION + R OV SW VSNS - PWM COMP + BOOST CHARGE PUMP CBST PK CURR COMP RCA SGND - + + - VDUTY - VPRG2 VSNS L VPK Q PWM BG LOGIC VCO 40A PGOOD 0.42V + ITH - SLEEP 10A PRESET HI/LO FREQ BURST COMPARATOR MODE CONTROL SYNC DET PLLIN/MODE ITHMIN COUT PGND SHDN VOSC PFD VOUT INTVCC S + REVERSE CURRENT COMPARATOR - VSNS + - CLKOUT 7101 BD Rev. 0 For more information www.analog.com 11 LT7101 OPERATION Main Control Loop The LT7101 is a high efficiency, monolithic, synchronous step-down DC/DC converter utilizing a constant frequency, average current mode control architecture. Average current mode control enables fast and precise control of the output current without the need for an external sense resistor or current sense amplifier. Instead, the inductor current is sensed internally by losslessly monitoring the top and bottom power switch currents. The LT7101 also contains a unique circuit that replicates the inductor current immediately after the top switch turn-on and combines this with the sensed switch currents to fully reconstruct the inductor current signal internally. This technique allows for direct control and monitoring of the average output current as well as clean operation at very low duty cycles. During normal operation, the internal top power switch (N-channel MOSFET) is turned on at the beginning of each clock cycle, causing the inductor current to increase. The sensed inductor current is then delivered to the average current amplifier, whose output (VDUTY) is compared with a saw-tooth ramp (VRAMP). When the VRAMP voltage exceeds the VDUTY voltage, the PWM comparator trips and turns off the top power MOSFET. After the top power MOSFET turns off, the synchronous power switch (N-channel MOSFET) turns on, causing the inductor current to decrease. The bottom switch stays on until the beginning of the next clock cycle, unless the reverse current limit is reached and the reverse current comparator trips. The reverse current limit is 0.4A for forced continuous mode and 0A for burst and pulseskipping modes. In closed-loop operation, the average current amplifier creates an average current loop that forces the average sensed current signal to be equal to the internal ITH voltage. Note that the DC gain and compensation of this average current loop is automatically adjusted to maintain an optimum current-loop response. The error amplifier adjusts the ITH voltage by comparing the divided-down output voltage (VFBI) with a 1.0V reference voltage. If the load current changes, the error amplifier adjusts the average inductor current as needed to keep the output voltage in regulation. 12 The LT7101 has been optimized to provide the fastest possible average current loop. To achieve this, the filter on the average current amplifier output (CCA, RCA) is set to provide high DC gain (provided by integrator capacitor CCA) while allowing the inductor current signal to pass through unfiltered. This is accomplished by resistor RCA, which introduces a zero that is well below the switching frequency. The resulting typical PWM comparator waveforms are shown in Figure1. Note that the VDUTY signal is an inverted reflection of the inductor current signal, which is essential for obtaining a high speed average current loop. INDUCTOR CURRENT VDUTY VRAMP 7101 F01 Figure1. Typical Current Loop Operating Waveforms Voltage loop compensation can be set externally using the ITH pin, taking advantage of OPTI-LOOP compensation to optimize the loop response. The compensation of the voltage loop is essentially the same as for peak current mode control. Alternatively, the ITH pin can be tied to INTVCC to select internal voltage loop compensation. When internal voltage loop compensation is selected, the LT7101 automatically adjusts the internal compensation based on switching frequency to maintain a fast and stable voltage loop. Power and Bias Supplies (VIN, SW, BOOST, INTVCC, EXTVCC Pins) The VIN pins on the LT7101 are used to supply voltage to the drain terminal of the internal high side N-channel Rev. 0 For more information www.analog.com LT7101 OPERATION MOSFET. These pins also supply bias voltage for an internal LDO regulator (the VIN LDO) that generates 3.5V at INTVCC. The voltage on INTVCC in turn is used for internal chip bias as well as gate drive for the bottom power MOSFETs. The gate drive for the top power MOSFET is supplied by a floating supply (CBST) between the BOOST and SW pins, which is charged by an internal synchronous diode from INTVCC. In addition, an internal charge pump allows for 100% duty cycle operation by maintaining the BOOST to SW voltage when the top MOSFET is on continuously. To improve efficiency and limit power dissipation in the VIN LDO regulator, a second LDO regulator (the EXTVCC LDO) allows the INTVCC voltage to be derived from the lower-voltage EXTVCC pin. In most applications, the EXTVCC pin is simply tied directly to the regulated output voltage of the DC/DC converter to enable operation in a high efficiency, bootstrapped configuration. In order to ensure that the power dissipation on the internal VIN LDO is limited to a safe level, the LT7101 incorporates a special regulator timeout feature into the soft-start pin. Start-Up and Shutdown (RUN, SS, OVLO Pins) When the RUN pin is below 0.7V, the LT7101 enters a low current shutdown state, reducing the DC supply current to 0.7A. When the RUN pin is above 0.7V and the VIN pin is above than the internal undervoltage threshold (VIN(UVLO)) of 4.55V, the INTVCC LDO regulators are enabled. However, switching is inhibited until the RUN pin is greater than VRUN(ON) = 1.21V. This allows the RUN pin to be used to implement a VIN undervoltage lockout function so that the power supply will not operate below a user-adjustable level. In addition, switching is also inhibited if the voltage on the OVLO pin exceeds VOV(R) = 1.21V. This feature can be used to implement an input overvoltage lockout function to prevent power supply operation during an overvoltage condition on the input supply. When appropriate voltages are present on the VIN, RUN and OVLO pins, the LT7101 will begin switching and initiate a soft-start ramp of the output voltage. An internal soft-start ramp of 1.2ms will limit the ramp rate of the output voltage to prevent excessive input current during start-up. If a longer ramp time is desired, a capacitor can be placed from the SS pin to ground. The 10A current that is sourced from the SS pin will create a smooth voltage ramp on the capacitor. If this external ramp rate is slower than the internal 1.2ms soft-start, then the output voltage will be limited by the ramp rate on the SS pin instead. Once both the external and internal soft-start ramps have exceeded 1V, the output voltage will be in regulation. The internal and external soft-start functions are reset during initial start-up and after an undervoltage or overvoltage condition on the input supply. The soft-start pin is also used to implement a regulator timeout feature. This feature limits die temperature rise due to power dissipation in the internal VIN LDO regulator by disabling the top and bottom power MOSFETs after a timeout, if EXTVCC voltage is not present. This is useful, for example, if EXTVCC is tied to the output of the DC/DC converter, but the converter output gets shorted to ground. During start-up, a regulator timeout begins after both the internal and external soft-start ramps have exceeded 1V, and EXTVCC < 3V. If this condition persists for a period of time (approximately 1.4 times the normal soft-start time), then a regulator timeout fault occurs and all switching stops. After a long restart delay (approximately 46 times the normal soft-start time), a restart is initiated. If the regulator timeout feature is not needed, the SS pin should be tied to INTVCC through a 75k resistor. See Soft-Start and LDO Regulator Timeout in the Applications Section for more information. Output Voltage Programming (VPRG1, VPRG2, VFB Pins) The VPRG1 and VPRG2 pins provide a great deal of flexibility in programming the output voltage of the power supply. Floating both pins selects adjustable VOUT mode. In this mode, the output is programmed using external resistors on the VFB pin, and the VFB voltage is regulated to the 1V reference. If one of the pins is tied either to SGND or INTVCC, then fixed output voltage mode is selected. In this mode, precision internal resistor dividers are used to program the output voltage to one of eight fixed voltage levels. See Output Voltage Programming in the Applications Information Section. Inductor Current Replication (RIND Pin) The LT7101 contains a unique circuit that replicates the inductor current immediately after the top switch turnon and combines this with the sensed switch currents Rev. 0 For more information www.analog.com 13 LT7101 OPERATION to fully reconstruct the inductor current signal internally. This technique allows for direct control and monitoring of the average output current as well as clean operation at very short top switch on-times. In order to replicate the inductor current, the LT7101 needs to know the approximate value of the inductor. This is achieved by placing a resistor on the RIND pin that is equal to 1/(3.3*L). The LT7101 uses the current in the RIND resistor in conjunction with the voltage on the VIN and SW pins to generate a replicated inductor current signal. In addition, the RIND pin current is also used in conjunction with the voltages on VIN and SW to set the DC gain of the average current amplifier. This is done to maintain optimum current loop performance over all operating conditions. Note that if fixed output voltage mode is selected using the VPRG1 and VPRG2 pins, then the RIND pin can be left floating. In this case, the LT7101 will assume a particular inductor value based on output voltage and switching frequency. See Inductor Value and RIND Resistor Selection in the Applications Information section. Light Load Operation: Forced Continuous, Burst and Pulse-Skipping Modes (PLLIN/MODE Pin) The LT7101 can be set to enter high efficiency Burst Mode operation, constant frequency pulse-skipping mode or forced continuous mode at low load currents. To select Burst Mode operation, tie the PLLIN/MODE pin to ground. To select forced continuous operation, tie the PLLIN/ MODE pin to INTVCC. To select pulse-skipping mode, tie the PLLIN/MODE pin to INTVCC through a 100k resistor. When the LT7101 is set for Burst Mode operation, the minimum output current is set to approximately 100mA even though the voltage on the ITH pin might indicate a lower value. If the average inductor current is higher than the load current, the error amplifier will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.4V, the internal sleep signal goes high (enabling sleep mode) and both MOSFETs are turned off. The ITH pin is then disconnected from the output of the error amplifier and parked at 0.43V. In sleep mode, much of the internal circuitry is turned off, reducing the total quiescent current that the LT7101 14 draws to 9A.When EXTVCC is present, the majority of this quiescent current (8A) is drawn from the EXTVCC supply and only 1A is drawn from the VIN supply. This dramatically reduces the sleep mode VIN supply current in bootstrapped applications where EXTVCC is tied to VOUT and VIN >> VOUT. In sleep mode, the load current is supplied by the output capacitor. As the output voltage VOUT decreases, the error amplifier output begins to rise. When the VOUT voltage drops enough, the ITH pin is reconnected to the output of the error amplifier, the sleep signal goes low, and normal operation is resumed by turning on the top MOSFET on the next cycle of the internal oscillator. When the LT7101 is set for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator turns off the bottom MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the converter operates with discontinuous inductor current (DCM). In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. This maintains continuous inductor current operation (CCM) down to no load, and the average inductor current is always determined by the voltage on the ITH pin. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry. In forced continuous mode, the output ripple is independent of load current. When the PLLIN/MODE pin is connected for pulse-skipping mode, the LT7101 operates in PWM pulse-skipping mode at light loads. In this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the PWM comparator may remain tripped for several cycles and force the top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Rev. 0 For more information www.analog.com LT7101 OPERATION When operating with discontinuous inductor current (DCM) in either burst or pulse-skipping mode, the LT7101 smoothly transitions from average current to peak current control. This feature eases compensation of the voltage loop in light load DCM operation by removing the pole associated with the average current loop. The typical capture range of the phase-locked loop is from approximately 160kHz to 2.3MHz, with a guarantee over all manufacturing variations to be between 200kHz and 2MHz. In other words, the LT7101's PLL is guaranteed to lock to an external clock source whose frequency is between 200kHz and 2MHz. To avoid spurious changes in the operating mode, the LT7101 incorporates a 20s delay before changing from one mode to another. This is particularly helpful since the PLLIN/MODE pin can be used to select an initial operating mode, and subsequently be used to receive an external clock for synchronization. The 20s delay avoids changes in mode while the synchronizing signal is recognized. When synchronized, the LT7101 operates in forced continuous mode. After the PLL has locked to an external clock, if the external clock is stopped, the LT7101 will immediately detect this condition and prevent the PFD from adjusting the loop, so that the internal oscillator continues operating at the external clock frequency. After approximately 9s, the LT7101 will detect a loss of SYNC, and the oscillator operating frequency returns to the level set by the FREQ pin. This feature prevents the oscillator frequency from dipping momentarily when the external clock is stopped, and enables smooth transitions into and out of synchronization. Frequency Selection and Phase-Locked Loop (FREQ, PLLIN/MODE Pins) The switching frequency of the LT7101 can be selected using the FREQ pin, which can be tied to SGND, tied to INTVCC, or programmed through an external resistor. Tying FREQ to SGND selects 300kHz while tying FREQ to INTVCC selects 1MHz. Placing a resistor between FREQ and SGND sends the FREQ pin voltage into the input of the voltage controlled oscillator (VCO), allowing the frequency to be programmed between 200kHz and 2MHz. A phase-locked loop (PLL) is available on the LT7101 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. The LT7101's phase detector (PFD) and low pass filter adjust the voltage of the VCO input to align the turn-on of the top MOSFET to the rising edge of the synchronizing signal. When an external clock is detected, the PFD low pass filter is quickly prebiased to the operating frequency set by the FREQ pin before the PLL is allowed to take over the VCO. If prebiased near the external clock frequency, the PLL loop only needs to make slight changes to the VCO input in order to synchronize the rising edge of the external clock's to the top MOSFET turn-on. The ability to prebias the loop filter allows the PLL to lock in rapidly without deviating far from the desired frequency. The typical input clock thresholds on the PLLIN/MODE pin are 1.5V rising and 1.1V falling, and this input is TTL compatible. The CLKOUT pin supplies a reference clock that is helpful for synchronizing other switching circuits to the LT7101 switching frequency. The output high level of this signal is equal to INTVCC (3.5V typical), and the rising edge of the CLKOUT signal is 180 out of phase with respect to the top MOSFET turn-on. This makes it easy to synchronize two LT7101 converters and operate them out of phase to minimize input current, or to use two LT7101's together for a higher current, 2-Phase converter. See 2-Phase Operation in the Applications Information section. Setting and Monitoring Output Current (ICTRL, IMON Pins) Because the LT7101 utilizes average current mode control, in which the ITH voltage is proportional to average output current, the setting and monitoring of the average output current is straight-forward. The average output current limit is set using the ICTRL pin, whose voltage directly clamps the ITH voltage to a maximum level. Tie this pin to a voltage between 0.4V and 1.3V to program the average output current to a value Rev. 0 For more information www.analog.com 15 LT7101 OPERATION By maintaining a fast and optimized current loop over all operating conditions, the LT7101 responds to changes in the ICTRL pin voltage with the greatest possible speed. This is orders of magnitude faster than most competing solutions, where a slow, average current loop is placed outside of the voltage regulation loop. By placing the average current loop inside of the voltage regulation loop, the LT7101 allows for current programming on a nearly cycle-by-cycle basis. The average output current can be monitored at the IMON pin. The reconstructed inductor current signal (VSNS) is run through a low pass filter (fc = 10kHz), buffered, and then delivered to the IMON pin. The voltage on the IMON normally varies between 0.4V and 1.3V, corresponding to an average output current between 0A and 1.11A. The IMON voltage may momentarily be less than 0.4V or greater than 1.3V, but eventually is limited to these levels by the average current loop. During SLEEP, this pin is held at 0.4V. Short-Circuit Protection and Minimum On-Time The architecture of the LT7101 provides inherent protection against short-circuit conditions, without the need for folding back either the output current or the oscillator frequency. This is made possible because the PWM comparator is continuously receiving inductor current information from the average current amplifier. This results in automatic cycle skipping under short-circuit conditions if the minimum on-time of the top switch is too long to maintain control of the inductor current at the full switching frequency. Because a given switching cycle is skipped only as needed to satisfy the high speed average current loop, this creates a brick-wall style current limit without any foldback or hiccups in the operation down to VOUT = 0V. Figure2 illustrates the typical operation of this brickwall current limit. 16 5 4 OUTPUT VOLTAGE (V) between 0A and 1.11A. An internal 20A pull-up on this pin allows a single resistor to SGND to be used to set the voltage. This pin can be floated to set the average output current to 1.11A and the peak current limit to 1.64A. 3 2 1 0 0 0.5 1 LOAD CURRENT (A) 1.5 7101 F02 Figure2. Typical Current Limit Operation While the average current loop is extremely fast, a failsafe peak current limit (IPK) comparator has also been incorporated to ensure that the inductor current cannot exceed a safe level even momentarily. The peak current limit is internally set to 0.53A above the average current limit, and tracks with the average current limit set by the voltage on the ICTRL pin. In practice, this peak current limit comparator is only needed when there is an abnormal voltage on the average current amplifier output filter and a short-circuit is simultaneously applied. In this case, the peak current limit comparator may be needed for a few cycles while the average current amplifier filter settles. When operating at a high step-down ratio from VIN to VOUT, care should be taken to choose a switching frequency that is low enough to avoid operation at minimum on-time. However, in the event that a high step-down ratio requires an on-time that is less than the minimum, the LT7101 architecture offers inherent protection against output overvoltage. Once again, the PWM comparator will automatically cause the skipping of a cycle as needed to maintain regulation of the output voltage. While this avoids output overvoltage, operation in this mode is undesirable as it increases inductor current ripple. In addition to this inherent protection, a separate output overvoltage comparator monitors the VFB voltage and prevents top MOSFET turn-on if an overvoltage condition is present (VFB exceeds VFB(OV)). Rev. 0 For more information www.analog.com LT7101 OPERATION Boost Supply and Dropout Operation By making use of an internal charge pump, the LT7101 is capable of operating at 100% duty cycle, providing the lowest possible dropout voltage and zero switching noise while in dropout. This charge pump delivers the small current required to maintain the static gate voltage on the top MOSFET switch when operating in dropout. When not operating in dropout, the gate drive voltage required for switching the top MOSFET switch is supplied by the charge pump formed by the BOOST capacitor (CBST), the bottom MOSFET switch, and an internal switch from INTVCC to BOOST. As dropout is approached, the on-time of the bottom MOSFET switch is lengthened as needed to maintain an adequate supply to the floating gate driver between BOOST and SW. Power Good (PGOOD Pin) The PGOOD pin is connected to the open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the internal feedback voltage (VFBI) is not within 10% of the 1V reference voltage. The PGOOD pin is also pulled low when the RUN pin is low (shutdown). When VFBI is within the 10% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 16V. There is a 24s delay (TPG) before the PGOOD pin goes low in response to the VFBI voltage going outside of the 10% window. Overtemperature and Overvoltage Protection In addition to the OVLO pin, which provides a useradjustable protection against VIN overvoltage, the LT7101 contains an internal VIN overvoltage shutdown feature. If the VIN pin voltage exceeds 118.5V rising (112V falling), then the top and bottom MOSFETs are held off and all switching stops. Likewise, if the internal die temperature exceeds 171C rising (155C falling), then the LT7101 disables switching until the temperature drops. Note that the internal overvoltage and overtemperature protection features are activated outside of the absolute maximum range of operation, and therefore should not be relied upon operationally. These features are only intended as a secondary failsafe to improve overall system reliability and safety. Rev. 0 For more information www.analog.com 17 LT7101 APPLICATIONS INFORMATION A general LT7101 application circuit is shown on the first page of this data sheet. External component selection is largely driven by the load requirement and begins with the selection of the operating frequency and light load operating mode. Next, the inductor L is chosen, which also determines the value of resistor RIND. After the inductor is chosen, the input capacitor CIN, the output capacitor COUT, the internal regulator capacitor CVCC, and the boost capacitor CBST, can be selected. Next, either a fixed output voltage or feedback resistors are selected to set the desired output voltage. Finally, the remaining optional external components can be selected for functions such as VIN undervoltage/overvoltage lock-out, external softstart, LDO regulator timeout, external loop compensation, average output current monitor and limit, and PGOOD. Setting the Operating Frequency Selection of the operating frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge and transition losses, but requires larger inductance values and/or capacitance to maintain low output ripple voltage. MAX RECOMMENDED FREQUENCY (MHz) 2.2 An additional constraint on operating frequency is the minimum controllable on-time of the LT7101. While the architecture of the LT7101 inherently maintains output voltage regulation even if the minimum on-time is exceeded, cycle-skipping will result in increased inductor current ripple. To avoid this, chose a switching frequency such that: f< V OUT V IN(MAX ) * t ON(MIN) When operating at VOUT>6V, additional constraints on the switching frequency may also apply. See Operating at VOUT>6V section for more information. The switching frequency is set using the FREQ and/or PLLIN/MODE pins as shown in Table1. Table1. Frequency Setting 2.0 1.8 ILOAD = 0.5A 1.6 ILOAD = 1A 1.4 1.2 1.0 0.8 FREQ PIN PLLIN/MODE PIN FREQUENCY(F) SGND DC Voltage 300kHz INTVCC DC Voltage 1MHz R = (f/40 + 7.5k) to SGND DC Voltage 200kHz to 2MHz Any of the Above External Clock Phase-Locked to External Clock (200kHz to 2MHz) VOUT = 5V FIGURE 13 CIRCUIT 0 20 40 60 INPUT VOLTAGE (V) 80 100 7101 F03 Figure3. Maximum Recommended Frequency vs Input Voltage For most LT7101 applications, a good balance between size and efficiency is achieved with a switching frequency between 300kHz and 750kHz. Operating at higher switching frequencies up to 2MHz is readily possible, but switching losses generally limit the input voltage to lower levels. 18 This is illustrated in Figure3, which shows the maximum recommended switching frequency versus input voltage at 0.5A and 1A loads for the application circuit of Figure14. These lines correspond to a power loss of 2.5W in the LT7101, which will result in a junction temperature rise of approximately 85C without air flow. See Efficiency Considerations and Thermal Considerations sections for more information on calculating the power loss and temperature rise. Tying the FREQ pin to SGND selects 300kHz while tying FREQ to INTVCC selects 1MHz. Since the FREQ pin sources 40A, placing a resistor between FREQ and SGND allows the frequency to be programmed anywhere between 200kHz and 2MHz. Choose a FREQ pin resistor such that: R FREQ = f 40 + 7.5k Rev. 0 For more information www.analog.com LT7101 APPLICATIONS INFORMATION A phase-locked loop (PLL) is also available on the LT7101 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. Once synchronized, the turn-on of the top MOSFET is aligned to the rising edge of the synchronizing signal. See PhaseLocked Loop and Frequency Synchronization section fordetails. Setting the Light-Load Operating Mode The LT7101 can be set to enter high efficiency Burst Mode operation, constant frequency pulse-skipping mode or forced continuous conduction mode at light load currents. To select Burst Mode operation, tie the PLLIN/MODE pin to ground. To select forced continuous operation, tie the PLLIN/MODE pin to INTVCC. To select pulse-skipping mode, tie the PLLIN/MODE pin to INTVCC through a 100k resistor. When synchronized, the LT7101 operates in forced continuous mode. Table2 summarizes the use of the PLLIN/MODE pin to select light-load operating mode. Table2. Mode Selection PLLIN/MODE PIN LIGHT-LOAD OPERATING MODE SGND Burst Mode Operation INTVCC Forced Continuous Mode R = 100k to INTVCC Pulse-Skipping Mode External Clock Forced Continuous Mode In general, the requirements of each application will dictate the appropriate choice for light-load operating mode. In Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator turns off the bottom MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the converter operates in discontinuous operation. In addition, when the average output current falls below approximately 100mA, the inductor current will begin bursting at frequencies lower than the switching frequency, and entering a low current SLEEP mode when not switching. As a result, Burst Mode operation has the highest possible efficiency at light loads. In forced continuous mode, the inductor current is allowed to reverse at light loads and switches at the same frequency regardless of load. In this mode, the efficiency at light loads is considerably lower than in Burst Mode operation. However, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry. in forced continuous mode, the output ripple is independent or load current. In pulse-skipping mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the PWM comparator may remain tripped for several cycles and force the top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Consequently, pulse-skipping mode represents a compromise between light load efficiency, output ripple and EMI. In some applications, it may be desirable to change lightload operating mode based on the conditions present in the system. For example, if a system is inactive, one might select high efficiency Burst Mode operation by keeping the PLLIN/MODE pin set to 0V. When the system wakes, one might send an external clock to PLLIN/MODE to switch to forced continuous mode. Such on-the-fly mode changes can allow an individual application to benefit from the advantages of each light-load operating mode. Inductor Value Selection For a given input and output voltage, the inductor value and operating frequency determine the inductor ripple current. More specifically, the inductor ripple current decreases with higher inductor value or higher operating frequency according to the following equation: V V IL = OUT 1- OUT f *L VIN For proper operation, always use an inductor value that is greater than: LMIN > 520nH * VOUT Rev. 0 For more information www.analog.com 19 LT7101 APPLICATIONS INFORMATION Note that in applications with VOUT>6V, additional constraints on the inductance value may also apply. See Operating at VOUT>6V section for more information. A trade-off between component size, efficiency and operating frequency can be seen from this equation. Accepting larger values of IL allows the use of lower value inductors, but results in greater core loss in the inductor, greater ESR loss in the output capacitor, and larger output ripple. Generally, highest efficiency operation is obtained at low operating frequency with small ripple current. A reasonable starting point for setting the ripple current is approximately 0.35AP-P. Note that the largest ripple current occurs at the highest VIN. To guarantee the ripple current does not exceed a specified maximum, the inductance should be chosen according to: V OUT V OUT L= 1- f * IL(MAX ) V IN(MAX ) The LT7101 contains a fast, average current limit loop that limits the DC output current to a value determined by the voltage on the ICTRL pin. (See Average Output Current Limit and Monitor section for details.) However, some applications may experience inductor current transients that are limited by the peak current limit comparator, which tracks nominally 0.53A above the average current limit set point. To avoid saturation, choose an inductor with a saturation current ISAT such that: V - 0.4 ISAT > ICTRL + 0.68A 0.77 This enables the use of an inductor with a current rating that fits the needs of a given application. If the average output current limit is set to the default value of 1.11A, then an inductor with ISAT > 1.9A is required. However, if the average current limit is set to 0.6A (VICTRL=0.89V), then an inductor with ISAT > 1.4A may be used. Note that if there is a varying voltage on the ICTRL pin, always use the highest value present on ICTRL when calculating the required inductor saturation current. See Average Output Current Limit and Monitor section for details on setting the average current limit. 20 If fixed VOUT operation is selected using the VPRG1 and VPRG2 pins, the RIND pin can be left floating, but only if the inductance value is chosen according to Table3. Since the RIND pin resistor indicates the inductance value being used, the LT7101 will automatically assume an inductance value as shown in Table3 when this pin is left floating. These inductance values will provide an inductor ripple current that is approximately 30% to 40% of the full load current. If the nominal value of the inductance used differs by more than 10% from the values specified in Table3, a resistor must be placed on the RIND pin to indicate this value. Table3. Required Inductor Values with RIND Pin Floating REQUIRED INDUCTANCE VALUE (RIND = FLOAT) FIXED VOUT f = 300kHz f = 1MHz f = ADJ 1.2V 10H 3.3H L = 3.1/f 1.8V 15H 4.7H L = 4.6/f 2.5V 22H 6.8H L = 6.7/f 3.3V 33H 10H L = 9.9/f 3.6V 33H 10H L = 9.9/f 5V 47H 15H L = 14.6/f 12V 100H 33H L = 31.5/f 15V 100H 33H L = 31.5/f Inductor Core Selection Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value but is very dependent on the inductance selected. As the inductance increases, core loss decreases. Unfortunately, increased inductance requires more turns of wire leading to increased copperloss. Ferrite designs exhibit very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core materials saturate hard, meaning the inductance collapses abruptly when the peak design current is exceeded. This collapse will result in an abrupt increase in inductor ripple current, so it is important to ensure the core will not saturate. Rev. 0 For more information www.analog.com LT7101 APPLICATIONS INFORMATION RIND Resistor Selection The resistor on the RIND pin is used to indicate to the LT7101 what inductance value is being used. This is required for the internal reconstruction of the inductor current waveform and to set the DC gain of the current loop. Once the inductor value is selected, the RIND pin resistor is chosen according to: R IND = 1 3.3 * L If fixed VOUT operation is selected using the VPRG1 and VPRG2 pins, the RIND pin can be left floating, but only if the inductance value is chosen according to Table3. Do not leave the RIND pin floating when adjustable VOUT mode is selected. If the RIND pin is left floating and adjustable VOUT mode selected (VPRG1 and VPRG2 are both floating), the LT7101 will detect this as a fault condition and will not operate. The allowable current range on the RIND pin is between 8A and 220A, which means that: 2.5 f * L 67 In practice, the above constraint does not normally affect the choice of inductor value. CIN Selection The input capacitance, CIN, is needed to filter the trapezoidal current at the drain of the top power MOSFET. CIN should be sized to do this without causing a large variation in input voltage. In addition, the input capacitor needs to have a very low ESR and must be rated to handle the worst-case RMS input current of: used for CIN. In many applications, an X7R capacitor of 4.7F or greater is a suitable choice. Always consult the manufacturer if there is any question. The input capacitor, CIN, should be placed as close as possible to the VIN pins, with a low inductance connection to the PGND (paddle) of the IC. In addition to a larger bulk capacitor, a smaller case-size (0603 or 0805) ceramic decoupling capacitor can be placed closer to the VIN pins to reduce EMI. Using an LC Input Filter CBULK Note that capacitor manufacturers' ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LT7101, ceramic capacitors can also be CF CD VIN LT7101 SW ZIN RD OPTIONAL 7101 F04 Figure4. Input Filter with Optional Damping Network For high voltage applications, it can be costly to use bulk capacitance that is rated to handle the required RMS input current. Moreover, when using a simple capacitor to filter the AC input current, it is difficult to determine exactly where this AC current is flowing when a power supply is placed into a larger system. To avoid these issues, an LC filter can be used on the power supply input as shown in Figure4. This keeps the higher AC currents contained in a relatively small and inexpensive capacitor (CF) whose RMS current rating is known to be adequate. Choose an LC filter such that: 1 2 L F C F I IRMS = OUT(MAX ) 2 ZOUT LF VIN < f 5 where f is the switching frequency. This will attenuate the RMS input current by a factor of approximately 5X, greatly alleviating the RMS input requirements of the larger bulk capacitor CBULK. The filter inductor LF should have a saturation current of at least: V I ISAT(LF ) 1.3 * OUT OUT(MAX ) V IN(MIN) Rev. 0 For more information www.analog.com 21 LT7101 APPLICATIONS INFORMATION In order to keep the ripple voltage at the filter output to a reasonable level, choose a value of LF and CF that also satisfies: R V < 2.9 * RIPPLE + ESR IOUT(MAX ) CF 2 LF Using Ceramic Input and Output Capacitors where VRIPPLE is the desired ripple voltage at the output of the input filter and RESR is the ESR of capacitor CF. A reasonable target for VRIPPLE is 3% of nominal VIN. When using an LC input filter, the output impedance of the LC filter (ZOUT) must never be greater in magnitude than the input impedance looking into the power stage of the DC/DC converter (ZIN). This is necessary to avoid ringing and possible voltage loop instability. In many applications, this condition is naturally satisfied because the ESR of the bulk input capacitance CBULK is high enough to lower the Q of the LC input filter. In some situations, a series damping network must be added as shown in Figure4. In order to provide critical damping, choose CD and RD according to: CD 4 * CF RD = LF CF COUT Selection The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (VOUT) is approximated by: 1 V OUT IL ESR + 8 * f * C OUT where f is the operating frequency, COUT is the output capacitance and IL is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. If internal voltage loop compensation is selected, than a minimum amount of bulk output capacitance is required to 22 ensure stability. Loop stability can be checked by viewing the load transient response. See Internal/External Loop Compensation in the Applications Information section. Higher value, lower cost ceramic capacitors are now available in small case sizes. Their high voltage rating and low ESR make them ideal for switching regulator applications. However, due to the self-resonant and high-Q characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input, and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the VIN input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. For a more detailed discussion, refer to Application Note 88. When choosing the input and output ceramic capacitors select the X5R or X7R dielectric formulations. These dielectrics provide the best temperature and voltage characteristics for a given value and size. In addition, be careful to consider the voltage coefficient of ceramic capacitors when choosing the value and case size. Most ceramic capacitors lose 50% or more of their rated value when used near their rated voltage. INTVCC Regulators The LT7101 features two separate internal low dropout linear regulators (LDO) that supply power at the INTVCC pin from either the VIN pin or the EXTVCC pin depending on the EXTVCC pin voltage available. INTVCC powers the internal MOSFET gates and most of the internal circuitry. The VIN LDO and the EXTVCC LDO each regulate INTVCC to 3.5V. The INTVCC pin must be bypassed to ground with a minimum of 1F ceramic capacitor, placed as close as possible to the INTVCC pin. In order to minimize noise and ripple on the INTVCC supply, always use a capacitor CVCC on Rev. 0 For more information www.analog.com LT7101 APPLICATIONS INFORMATION INTVCC that is at least 10x greater than the capacitor CBST from BOOST to SW: CVCC > 10 * CBST Be careful to account for the voltage coefficient of ceramic capacitors when choosing the value and case size. Many ceramic capacitors lose 50% or more of their rated value when used near their rated voltage. For high VIN applications it is advantageous to tie EXTVCC to VOUT (bootstrapping), as this will improve efficiency and reduce power dissipation in the VIN LDO. This can be done with any VOUT voltage between 3.3V and 40V. Alternatively, the EXTVCC pin can be tied to any DC voltage between 3.3V and 40V that is capable of delivering the required INTVCC bias current, which varies with switching frequency and operating mode. At full-load operation, which is the worst case, the INTVCC bias current is given approximately by: V IINTVCC = 3.5mA +1nC 4+ IN * f 31 4. EXTVCC connected to an output-derived boost or charge-pump network. For 2.5V and other low voltage buck regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 3.05V. Most applications will simply tie EXTVCC to VOUT for high efficiency bootstrapping. In this configuration, with Burst Mode operation selected, the no-load VIN current in regulation can be calculated using: IVIN = 1A + V OUT V V * OUT + OUT + 8A 0.8 * V IN RD 6M where RD is the total resistance of the feedback resistive divider from VOUT to GND. In fixed output voltage mode, where VOUT is programmed using VPRG1 and VPRG2, use RD = VOUT/1.25A. For adjustable VOUT mode (Figure5), use RD = R1 +R2. Topside MOSFET Driver Supply (CBST) When EXTVCC is not present, the LDO timeout feature limits the junction temperature rise due to the VIN LDO power dissipation. See Soft-Start and LDO Regulator Timeout section for more information. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the VIN LDO resulting in an efficiency penalty at high input voltages. 2. EXTVCC connected directly to the output voltage VOUT. This is the normal connection for a 3.3V to 40V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available in the 3.3V to 40V range, it may be used to power EXTVCC providing it can supply the required INTVCC current. Operating with EXTVCC > VIN is allowed. The boost capacitor, CBST, on the Functional Diagram is used to create a voltage rail above the applied input voltage, VIN. Specifically, the boost capacitor is charged through an internal MOSFET switch to a voltage equal to approximately INTVCC each time the bottom power MOSFET is turned on. The charge on this capacitor is then used to supply the required current during the remainder of the switching cycle. When the top MOSFET is turned on, the BOOST pin voltage will be equal to approximately VIN + 3.5V. For most applications a 0.1F, X7R ceramic capacitor will provide adequate performance. The LT7101 also contains an internal charge pump that supplies a small amount of current to the BOOST pin to allow for continuous operation at 100% duty cycle. This charge pump is adequate to support internal biasing needs and to keep the top MOSFET fully enhanced. Note that the total external leakage on the BOOST pin (including the CBST capacitor leakage) must be less than 4A to ensure continuous operation at 100% duty cycle. Rev. 0 For more information www.analog.com 23 LT7101 APPLICATIONS INFORMATION Output Voltage Programming The VPRG1 and VPRG2 pins provide a great deal of flexibility in programming the output voltage of the power supply. Floating both pins selects adjustable VOUT mode. In this mode, the output is programmed using external resistors on the VFB pin as shown in Figure5. The regulated output voltage is determined by: R1 V OUT = 1V 1+ R2 To avoid excessively large values of R1 in high output voltage applications (VOUT 15V), a combination of external and internal resistors can be used to set the output voltage. Figure6 shows the LT7101 with the VFB pin configured for a 15V fixed output with an external divider to generate a higher output voltage. The internal 12M resistance appears in parallel with R2, and the value of R2 must be adjusted accordingly. R2 should be chosen to be less than 400k to keep the output voltage variation less than 1% due to the tolerance of the LT7101's internal resistor. VOUT VOUT R1 LT7101 LT7101 R1 VFB CFF 11.2M VFB 15V R2 1V R2 800k INTVCC 7101 F05 VPRG1 Figure5. Setting the Output Voltage VPRG2 Place resistors R1 and R2 very close to the VFB pin to minimize PCB trace length and noise. Great care should be taken to route the VFB trace away from noise sources, such as the inductor or the SW trace. To improve frequency response, a feedforward capacitor (CFF) may be used. If either VPRG1 or VPRG2 is tied to SGND or INTVCC, then fixed output voltage mode is selected. In this mode, precision internal resistor dividers are used to program the output voltage to one of eight fixed voltage levels as shown in Table4. Table4. Output Voltage Programming VPRG1 VPRG2 VOUT INTVCC INTVCC 1.2V OPEN INTVCC 1.8V SGND SGND 2.5V SGND OPEN 3.3V SGND INTVCC 3.6V OPEN SGND 5V INTVCC OPEN 12V INTVCC SGND 15V OPEN OPEN Adjustable 1V to VIN 7101 F06 Figure6. Setting the Output Voltage with External and Internal Resistors RUN Pin and Overvoltage/Undervoltage Lockout The LT7101 has a low power shutdown mode controlled by the RUN pin. Pulling the RUN pin below 0.7V puts the LT7101 into a low quiescent current shutdown mode (IQ = 0.7A). When the RUN pin is greater than VRUN(ON) = 1.21V, switching is enabled. Figure7 shows examples of configurations for driving the RUN pin from logic. Note that the RUN pin can only be directly controlled as shown in Figure7 for applications with VOUT6V. See Operating at VOUT>6V section for more information. VIN 4.7M SUPPLY 1k LT7101 RUN 1k LT7101 RUN 7101 F07 Figure7. RUN Pin Interface to Logic 24 Rev. 0 For more information www.analog.com LT7101 APPLICATIONS INFORMATION The RUN and OVLO pins can alternatively be configured as precise undervoltage (UVLO) and overvoltage (OVLO) lockouts on the VIN supply with a resistor divider from VIN to ground. A simple resistor divider can be used as shown in Figure8 to meet specific VIN voltage requirements. For applications with VOUT>6V that require direct RUN pin control, an open-drain pull-down must be used as shown in Figure8. See Operating at VOUT>6V section for more information. VIN Similarly, for applications that do not require a precise UVLO, the RUN pin can be tied to VIN. In this configuration, the UVLO threshold is limited to the internal VIN UVLO thresholds as shown in the Electrical Characteristics table. The resistor values for the OVLO can be computed using the previous equations with R3 = 0. Be aware that the OVLO pin cannot be allowed to exceed its absolute maximum rating of 6V. To keep the voltage on the OVLO pin from exceeding 6V, the following relation should be satisfied: R3 RUN LT7101 R4 If this equation cannot be satisfied in the application, connect a 4.7V Zener diode between the OVLO pin and ground to clamp the OVLO pin voltage as shown in Figure8. OVLO OPTIONAL R5 4.7V 7101 F08 OPTIONAL Figure8. Adjustable UV and OV Lockout The current that flows through the R3-R4-R5 divider will directly add to the shutdown, sleep, and active current of the LT7101, and care should be taken to minimize the impact of this current on the overall efficiency of the application circuit. Resistor values in the M range may be required to keep the impact on quiescent shutdown and sleep currents low. To pick resistor values, the sum total of R3 + R4 + R5 (RTOTAL) should be chosen first based on the allowable DC current that can be drawn fromVIN. The individual values of R3, R4 and R5 can then be calculated from the following equations: R5 = R TOTAL * R4 = R TOTAL * 1.21V RISING V IN OVLO THRESHOLD 1.21V RISING V IN UVLO THRESHOLD R5 V IN(MAX ) * < 6V R3 + R4 + R5 - R5 R3 = R TOTAL - R5 - R4 For applications that do not need a precise external OVLO, the OVLO pin should be tied directly to ground. The RUN pin in this type of application can be used as an external UVLO using the previous equations with R5 = 0. Note that in applications with VOUT > 6V, additional constraints on the use of the RUN pin also apply. See Operating at VOUT>6V section for more information. Soft-Start and LDO Regulator Timeout An internal soft-start ramp of 1.2ms will limit the ramp rate of the output voltage to prevent excessive input current during start-up. If a longer ramp time is desired, a capacitor can be placed from the SS pin to ground. The value of the soft-start capacitor needed to provide a desired soft-start time (tSS) can be calculated by: CSS = tSS * 10A Note that the value of CSS must be greater than 12nF to provide a soft-start time that is greater than the internal default of tSS(INT) = 1.2ms. The LT7101 also includes an LDO regulator timeout feature that is essential for limiting die temperature rise due to power dissipation in the VIN LDO. This is useful in high VIN applications, where EXTVCC is tied to VOUT, and VOUT gets shorted to ground. When this occurs, the VIN LDO will take over the INTVCC current, resulting in potentially high power dissipation (>1W) in the VIN LDO pass device. If this condition persists, an LDO timeout occurs, disabling the switching of the top and bottom MOSFETs. Once switching is disabled, the INTVCC bias Rev. 0 For more information www.analog.com 25 LT7101 APPLICATIONS INFORMATION current is reduced to approximately 4mA, thereby lowering the power dissipation in the LDO. After a long restart delay, a soft-start is again initiated. The LDO regulator timeout and restart time are dependent on the length of the soft-start time selected, tSS, which is either the default of 1.2ms or set externally. After the soft-start is complete, a timeout will occur if EXTVCC < 3V for a time given by: tTIMEOUT = 1.4 * tSS At this point, switching will stop, and a restart delay timer will be activated. A restart will occur after a delay given by: tRESTART = 46 * tSS As long as this condition persists (EXTVCC < 3V), the LT7101 will continue operating in a hiccup restart mode. This yields an effective duty cycle of power dissipation in the VIN LDO of approximately 2%, which prevents any significant rise in die temperature. Note, however, that the LDO regulator timeout feature precludes operation in constant output current mode in applications where EXTVCC is tied to VOUT, and VOUT < 3V. If the LDO regulator timeout feature is not needed, the SS pin can be tied to INTVCC through a 75k resistor. This will prevent the LDO timeout from occurring, allowing continuous operation even with EXTVCC = 0V. The addition of this resistor also affects the soft-start time when an external capacitor is used (the internal 1.2ms softstart is not affected). With SS tied to INTVCC through 75k, the value of the soft-start capacitor needed to provide a desired soft-start time (tSS) can be calculated by: CSS(75k) = tSS * 51A If the LDO regulator timeout feature is defeated, care must be taken to avoid exceeding the maximum junction temperature. See Thermal Considerations for more information. Phase-Locked Loop and Frequency Synchronization The LT7101 contains a phase-locked loop (PLL) to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. Once synchronized, the turn-on of the top MOSFET is aligned to the rising edge of the synchronizing signal. 26 The typical capture range of the PLL is from 160kHz to 2.3MHz, with a guarantee over all manufacturing variations to be between 200kHz and 2MHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.5V rising and 1.1V falling, and this input is TTL compatible. Rapid phase-locking can be achieved by using the FREQ pin to set a free-running frequency near the desired synchronization frequency. Before synchronization, the VCO's filter voltage is prebiased to a level that corresponds to the frequency set by the FREQ pin. Consequently, the PLL only needs to make minor adjustments to achieve phase-lock and synchronization. Although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the PLL locks. After the PLL has locked to an external clock, if the external clock is stopped, the LT7101 will immediately detect this condition and momentarily prevent the PLL from adjusting the loop, so that the internal oscillator continues operating at the external clock frequency. After approximately 9s, the LT7101 will detect a loss of SYNC, and the oscillator frequency will return to the level set by the FREQ pin. This feature enables smooth transitions into and out of synchronization. The CLKOUT pin supplies a reference clock that is helpful for synchronizing other switching circuits to the LT7101 switching frequency. The output high level of this signal is equal to INTVCC (3.5V typical), and the rising edge of the CLKOUT signal is 180 out of phase with respect to the top MOSFET turn-on. This makes it easy to synchronize two LT7101 converters and operate them out of phase to minimize input current, or to use two LT7101's together for a higher current, 2-Phase converter. See 2-Phase Operation Section. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LT7101 is capable of turning on the top MOSFET. It is determined by internal timing delays. Low duty cycle applications may approach this minimum on-time limit and care should be taken to avoid this by operating at a sufficiently low switching frequency. See Setting the Operating Frequency section. Rev. 0 For more information www.analog.com LT7101 APPLICATIONS INFORMATION The minimum on-time for the LT7101 is approximately 40ns. If the duty cycle drops below the minimum on-time limit in this situation, cycle skipping can occur with correspondingly larger current and voltage ripple. Operating at VOUT>6V The LT7101 contains circuitry to automatically charge the boost supply for the topside MOSFET driver by activating the bottom MOSFET for short periods of time when necessary. This feature ensures the boost supply is always charged and ready under all operating conditions. When starting up or operating near dropout (VINVOUT) and with VOUT>6V, however, care must be taken to avoid the accumulation of negative inductor current that can arise from the automatic boost charging circuitry. There are two optional configurations allowable for applications with VOUT>6V. Option 1: 100% Duty Cycle Allowed. Use this option when operation at or near 100% duty cycle is required or if RUN pin control is not needed. For this option, the RUN pin must be tied to the VIN pin directly and operation at higher switching frequencies is prohibited. The switching frequency set point must be limited to a maximum value of As shown in Figure9, this constraint on minimum operating input voltage establishes a maximum allowable duty cycle that varies with switching frequency. Note that the minimum operating input voltage can be set to any voltage higher than the value for VIN,MIN given above. 100 90 MAXIMUM DUTY CYCLE (%) If the duty cycle does fall below what can be accommodated by the minimum on-time, the LT7101 will begin to skip cycles, regardless of the mode of operation (burst pulse-skipping or forced continuous modes). The output voltage will continue to be regulated, but the ripple voltage and current will increase. 80 70 60 50 40 30 0.2 1 FREQUENCY (MHz) 2 7101 F09 Figure9. Maximum Allowable Duty Cycle vs Frequency for VOUT>6V and Option 2 Configuration When selecting the resistors for the RUN pin divider to limit the minimum operating VIN voltage, use the RUN pin falling threshold minimum value of 1.06V. This ensures that the LT7101 will not operate below the minimum operating input voltage requirement given in Option 2 above. Referring to Figure8, calculate the RUN pin divider resistors as: R4 = R TOTAL * 1.06V VIN,MIN f 550kHz R3 = R TOTAL - R4 - R5 and the inductance value must be a minimum of The rising VIN voltage at which the LT7101 will begin switching is determined by the rising RUN pin threshold of 1.21V (1.26V maximum). The typical rising VIN turn-on voltage is therefore: L4.5H*(VOUT-3)-10H Option 2: High Switching Frequency Allowed. Use this option when either high switching frequency or RUN pin control is needed. In this case, operation near drop-out is prohibited and a RUN pin divider is required to set the minimum operating input voltage to a value of: VIN,MIN VOUT 1- f * 260ns VIN(ON,TYP)=1.14*VIN,MIN Note that for direct RUN pin control in all applications with VOUT>6V, an open-drain pull-down must be used in conjunction with a RUN pin divider as shown in Figure8. Since Option 2 allows for higher switching frequency and smaller size inductors, this option is preferred for Rev. 0 For more information www.analog.com 27 LT7101 APPLICATIONS INFORMATION applications with VOUT 16V or where space is limited, provided that high duty cycle operation is not required. Option1 is a better choice for applications with 6V<VOUT<16V or whenever high duty cycle operation is required, provided that RUN pin control is not needed. Internal/External Loop Compensation The LT7101 provides the option to use a fixed internal loop compensation network to reduce both the required external component count and design time. The internal loop compensation network can be selected by connecting the ITH pin to the INTVCC pin. Internal compensation can be used at any switching frequency from 200kHz to 2MHz. The LT7101 automatically adjusts the internal compensation based on switching frequency to maintain an optimum transient response. When using internal compensation, a reasonable starting point for the minimum amount of output capacitance necessary for stability can be found as the greater of either 4.7F or COUT defined by the equation: C OUT 40 f * V OUT where COUT is the capacitance value at voltage VOUT, noting that most ceramic capacitors lose 50% or more of their rated value when used at their rated voltage. Alternatively, the user may choose specific external loop compensation components to optimize the main control loop transient response as desired. External loop compensation is chosen by simply connecting the desired network to the ITH pin. Typical compensation component values are shown in Figure10. For a 500kHz application, for example, an R-C (RCOMP and CCOMP in Figure10) network of 2.2nF and 10k provides a good starting point. The bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. A 10pF bypass capacitor (CBYP in Figure10) on the ITH 28 pin can be used to filter out high frequency coupling from stray board capacitance. In addition, a feedforward capacitor, CFF, can be added to improve the high frequency response, as previously shown in Figure5. Capacitor CFF provides phase lead by creating a high frequency zero with R1 which improves the phase margin. ITH LT7101 SGND RCOMP 10k RCOMP 2.2nF CBYP 7101 F10 Figure10. Compensation Components Checking the Transient Response The regulator loop response can be checked by observing the response of the system to a load step. When configured for external compensation, the availability of the ITH pin not only allows optimization of the control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time, and settling behavior at this test point reflect the system's closed loop response. Assuming a predominantly second order system, the phase margin and/or damping factor can be estimated by observing the percentage of overshoot seen at this pin with a high impedance, low capacitance probe. The ITH external components shown in Figure10 will provide an adequate starting point for most applications. The series R-C filter sets the pole-zero loop compensation. The values can be modified to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The specific output capacitors must be selected because their various types and values determine the loop feedback factor, gain, and phase. An output current pulse of 20% to 100% of full load current, with a rise time of 1s to 10s, will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Rev. 0 For more information www.analog.com LT7101 APPLICATIONS INFORMATION When observing the response of VOUT to a load step, the initial output voltage step may not be within the bandwidth of the feedback loop. As a result, the standard second order overshoot/DC ratio cannot be used to estimate phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Analog Devices Application Note 76. In some applications, severe transients can be caused by switching in loads with large (>1F) supply bypass capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this output droop if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot SwapTM controller is designed specifically for this purpose and usually incorporates current limit, short-circuit protection and soft-start functions. Average Output Current Limit and Monitor The LT7101 contains a fast and accurate average current limit that can be externally controlled and monitored. This fast current loop is useful in applications such as the charging of batteries and capacitors or current programming in LEDs and laser diodes. The average output current limit is set using the ICTRL pin. The voltage on the ICTRL pin sets the average output current limit accordingto: V - 0.4 ILIM(AVG) = ICTRL 0.811 An internal 20A pull-up on this pin allows a single resistor to SGND to be used to set the voltage. To program a particular fixed average output current limit ILIM(AVG), chose a resistor according to: R ICTRL = 0.811*ILIM(AVG) + 0.4 20A Since the LT7101 uses average current mode control with a high speed inner current loop, there are no stability concerns when operating in constant current mode. In addition, the LT7101 automatically optimizes the current loop based on switching frequency and operating condition. The unity-gain bandwidth of the average current loop is maintained at approximately 1/3 of the switching frequency. This enables the LT7101 to respond to changes in the ITH pin voltage on a nearly cycle-by-cycle basis. This is orders of magnitude faster than competing solutions, where a slow, average current loop is placed outside of the voltage regulation loop. When operating in constant current mode with a low voltage on ICTRL, the inductor current will become discontinuous. In this situation, the LT7101 average current loop maintains good output current programming accuracy down to no load. The average output current can be monitored at the IMON pin. This pin generates a voltage that represents a filtered version (fC = 10kHz) of the internally sensed inductor current. The DC voltage on IMON normally varies between 0.4V and 1.3V, corresponding to an average output current between 0A and 1.11A according to: VIMON = 0.811 * IOUT(AVG) + 0.4 This allows for the average current limit to be set anywhere between 0A and 1.11A by adjusting the ICTRL voltage from 0.4V to 1.3V. If the ICTRL voltage is less than 0.4V, it will be internally limited to 0.4V, so that the average output current cannot be set to a negative value. Likewise, the ICTRL voltage is internally limited to 1.3V if the ICTRL pin is floated or tied to a voltage greater than 1.3V. The IMON voltage may momentarily be less than 0.4V or greater than 1.3V, but eventually is limited to these levels by the average current loop. During SLEEP, this pin is held at 0.4V. To ensure stability of the internal IMON buffer, place a 2k or higher resistor in series with any capacitive load that is greater than 100pF. Rev. 0 For more information www.analog.com 29 LT7101 APPLICATIONS INFORMATION 2-Phase Operation The LT7101 supports parallel operation in order to produce a higher output current. 2-Phase operation is easily implemented as shown in Figure11. In this figure, the upper LT7101 operates as the master, and handles voltage regulation. The lower (slave) LT7101 operates as a current source, the value of which is determined by the demand of the average current loop of the master. The slave is synchronized 180 out of phase with respect to the master, dramatically reducing input current ripple. Tying the SS pins together insures that the both parts start up and shut down together. Tying the VFB pin of the slave to INTVCC while floating VPRG1 and VPRG2 activates slave mode. This disables the 20A pull-up current on the ICTRL pin and causes the ITH voltage of the slave to track with the ICTRL pin voltage. When operating in slave mode, a resistor on the RIND pin is always required to indicate the inductor value being used. Place a 10pF cap from ITH to GND on the slave to eliminate any high frequency noise. L1 VIN VIN VOUT SW VFB LT7101 EXTVCC (MASTER) INTVCC CIN1 COUT 1F SS CLKOUT ITH CC RC CBYP SS PLLIN/MODE ICTRL SW VIN VPRG1 EXTV CC LT7101 VPRG2 (SLAVE) INTVCC RIND VFB ITH CIN2 RIND L2 1F 10pF 7101 F11 Figure11. Connections for 2-Phase Operation Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would 30 produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% - (L1 + L2 + L3 +...) where L1, L2, etc. are the individual loss terms as a percentage of input power. Although all dissipative elements in the circuit produce losses, three main sources account for the majority of the losses in the LT7101: 1) I2R loss, 2) INTVCC regulator current, 3) transition losses and other system losses. 1. I2R loss is calculated from the DC resistance of the internal switches, RSW, and external inductor, RL. In continuous current mode, the average output current will flow through inductor L but is chopped between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both the top and bottom MOSFET's RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP) * (DC) +(RDS(ON)BOT) * (1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R loss: I2R Loss = IOUT2 * (RSW + RL) 2. The internal LDO supplies the power to the INTVCC rail. The total power loss here is the sum of the gate drive losses and quiescent current losses from the control circuitry. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the DC control bias current. In continuous current mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and bottom power MOSFETs and f is the switching frequency. For estimation purposes, (QT + QB) on the LT7101 is approximately 4nC, although it varies with VIN voltage. To calculate the total power loss from the LDO load, simply add the gate charge current and quiescent current and multiply byvoltage: V PLDO = 3.5mA +1nC 4+ IN * f * VX 31 Rev. 0 For more information www.analog.com LT7101 APPLICATIONS INFORMATION where VX = VIN if the VIN LDO is active or VX = EXTVCC if the EXTVCC LDO is active. Supplying INTVCC from an output-derived power source through EXTVCC will scale the VIN current required for the gate drive and control circuits by a factor of (duty cycle)/(efficiency). For example, in a 48V to 5V application, 10mA of INTVCC current results in approximately 1.2mA of VIN current. This reduces the mid-current loss from 10% or more to less than 2%. 3. Transition losses apply only to the top MOSFET, and can become significant when operating at high input voltages (typically 40V or greater) and high frequency. Transition losses can be estimated from: Transition Loss = (47pF) * (VIN + 13)2 * (IOUT + 1.3) * f Other hidden losses such as copper trace resistances, and internal battery resistances can account for additional efficiency degradations in the overall power system. Other losses, including diode conduction losses during dead time and inductor core losses, generally account for less than 2% total additional loss. Fault Conditions: Short-Circuit Protection The architecture of the LT7101 provides inherent protection against short-circuit conditions, without the need for folding back either the output current or the oscillator frequency. A given switching cycle is skipped only as needed to satisfy the high-speed average current loop, resulting in a brick-wall style current limit without any foldback or hiccups in the operation down to VOUT = 0V. Note, however, that hiccup restart will occur due to the LDO timeout feature unless EXTVCC > 3V, or this feature is disabled by tying the SS pin to INTVCC through a 75k resistor. While the average current loop is extremely fast, a failsafe peak current limit (IPK) comparator has also been incorporated to ensure that the inductor cannot exceed a safe level, even momentarily. In practice, the peak current limit comparator is only needed when there is an abnormal voltage on the average current amplifier output filter and a short-circuit is applied. In this case, the peak current limit comparator may be needed for a few cycles while the average current amplifier filter settles. Fault Conditions: Overtemperature Protection At higher temperatures, or in cases where the internal power dissipation causes excessive self-heating on chip, the overtemperature shutdown circuitry will shut down the LT7101. When the junction temperature exceeds approximately 171C, the overtemperature circuitry disables all switching to eliminate internal power dissipation. Once the junction temperature drops back to approximately 155C, the LT7101 turns back on and re-initiates a start-up. Long term overstress (TJ > 150C) should be avoided as it can degrade the performance or shorten the life of the part. Thermal Considerations The LT7101 requires the exposed package backplane metal (PGND) to be well soldered to the PC board to provide both electrical and thermal contact. This gives the QFN package exceptional thermal properties, compared to other packages of similar size. In many applications, the LT7101 does not generate much heat due to its high efficiency and low thermal resistance package backplane. However, in applications in which the LT7101 is running at a high ambient temperature and high input voltage or high switching frequency, the generated heat may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 171C, both power switches will be turned off until temperature decreases by approximately 16C. Thermal analysis should always be performed by the user to ensure the LT7101 does not exceed the maximum junction temperature. The temperature rise is given by: TRISE = PD * JA where PD is the power dissipated in the chip and JA is the thermal resistance from the junction of the die to the ambient environment. Consider the example in which an LT7101 is operating with IOUT = 1A, VIN = 50V, f = 500kHz, VOUT = EXTVCC = 5V, and an ambient temperature of 70C. From the Typical Performance Characteristics section the RDS(ON) of the top switch at this temperature is found to be nominally 760m while that of the bottom switch is Rev. 0 For more information www.analog.com 31 LT7101 APPLICATIONS INFORMATION nominally 410m yielding an equivalent power MOSFET resistance RSW of: RSW = (760m)(0.1) + (410m)(0.9) = 445m From the previous section, the I2R losses are (12)(0.445) = 445mW. INTVCC power dissipation is: 50 PLDO = 3.5mA +1nC 4+ * 500k * 5 = 32mW 31 The transition losses are approximately: (47pF) * 632 * (1 + 1.3) * 500kHz = 215mW so the total power dissipation is approximately 0.69W. The QFN 5mm x 6mm package junction-to-ambient thermal resistance, JA, is approximately 38C/W. Therefore, the junction temperature of the regulator operating in a 70C ambient temperature is approximately: TJ = 0.69W * 38C/W + 70C = 96C which is below the maximum junction temperature of150C. Design Example As a design example, consider the LT7101 in an application with the following specifications: VIN = 36V to 72V, VOUT = 12V, IOUT(MAX) = 1A, IOUT(MIN) = 20mA, and switching is enabled between 30V and 90V on VIN. First, because efficiency is important at both high and low load currents, Burst Mode operation at 500kHz is chosen. VIN 36V TO 72V The RFREQ resistor for 500kHz switching frequency is calculated using RFREQ = f/40 + 7.5k = 20k. In addition, the PLLIN/MODE pin is tied to ground to select Burst Mode operation. Next, since the output voltage is available as a preprogrammed value (VPRG1 = INTVCC and VPRG2 = OPEN), the RIND pin is left floating, and the inductor value chosen according to Table3 as 63H. Suitable inductors with a nominal value of 68H and ISAT 1.8A are available from multiple manufacturers, so a value of L = 68H is chosen. Next, COUT = 10F is selected based on the minimum needed for internal voltage loop compensation and output ripple. CIN is sized to handle a ripple current IRMS = IOUT/2 = 0.5A. A low ESR, 100V, 4.7F ceramic capacitor is chosen. The INTVCC decoupling capacitor is chosen as 1F and the BOOST capacitor is chosen as 0.1F. EXTVCC is tied to VOUT to minimize loss in the INTVCC LDO. The undervoltage and overvoltage lockout requirements on VIN can be satisfied with a resistor divider from VIN to the RUN and OVLO pins (refer to Figure8). Choose R3+R4+R5 = 2.5M to minimize the loading on VIN. Calculate R3, R4 and R5 as follows: R5 = R4 = 90V 1.21V * 2.5M = 33.6k - R5 = 67.2k 30V R3 = 2.5M - R5 - R4 = 2.4M VIN BOOST 0.1F LT7101 2.2M RUN 4.7F 1.21V * 2.5M 62k OVLO 30.9k SW 68H VOUT 12V 1A VFB EXTVCC FREQ PLLIN/MODE 10F INTVCC 20k VPRG1 ITH SGND PGND 1F 7101 F12 Figure12. 36V to 72V Input to 12V Output, 1A Regulator 32 Rev. 0 For more information www.analog.com LT7101 APPLICATIONS INFORMATION Since specific resistor values in the M range are generally less available, it may be necessary to scale R3, R4, and R5 to a standard value of R3. For this example, choose R3 = 2.2M and scale R4 and R5 by 2.2M/2.4M. Then, R4 = 61.6k and R5 = 30.8k. Choose standard values of R3 = 2.2M, R4 = 62k, and R5 = 30.9k. Note that the falling thresholds for the UVLO and OVLO will be 8% and 5% lower than the rising thresholds, or 27.6V and 85.5V respectively. Since this application has VOUT>6V and RUN pin control is desired, Option 2 configuration is selected. The minimum allowed operating input voltage is given by: VIN,MIN 12 1- 0.13 = 13.8V This requirement is easily satisfied by the RUN pin divider, which limits operation to input voltage greater than 27.6V. Internal compensation is selected by tying the ITH pin to INTVCC. The ICTRL pin is left floating to select a current limit of 1.11A, and the SS pin is left floating to select the internal soft-start ramp of 1.2ms. Figure12 shows a complete schematic for this design example. Low EMI PCB Layout The LT7101 is designed specifically to minimize EMI/EMC emissions by reducing the parasitic inductance associated with the internal power switches. For optimal performance, the LT7101 requires two VIN bypass capacitors. As shown in Figure13, place a smaller 0.1F capacitor (CIN1, 0805 case) as close as possible to the LT7101, and a 4.7F or larger capacitor (CIN2, 1210 case) just beyond CIN1. For the lowest possible EMI/EMC emissions, an input filter is required. See Figure17 for an example and the LT7101 demo board guide for additional details as well as PCB design files. When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LT7101 (Refer to Figure13): 1.Place the input capacitors, inductor and output capacitors on the same side of the circuit board, and make their connections on that layer where possible. Place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. 2. Connect capacitor CIN1 to VIN and PGND as close to the pins as possible. These capacitors provide the AC current to the internal power MOSFETs. The (-) plate of CIN1 should be closely connected to PGND and the (-) plate of COUT. 3. When using adjustable VOUT mode, the resistor divider (R1 and R2) must be connected between the (+) plate of COUT and a ground line terminated near SGND. Place these resistors near the IC, keeping the VFB trace short and away from either SW or BOOST. 4. Keep sensitive components (attached to RUN, OVLO, RIND, ITH, VFB, FREQ, IMON and ICTRL) away from the SW and BOOST pins. Make the SW and BOOST nodes as small as possible. 5. Use either one ground plane or segregate the signal and power grounds into two planes connected through a single, low resistance trace to a common reference point, typically at the exposed pad. 6. Flood all unused areas on all layers with copper tied to the exposed pad in order to reduce the temperature rise of the LT7101. Rev. 0 For more information www.analog.com 33 LT7101 APPLICATIONS INFORMATION VIN VIN BOOST R3 RUN CIN2 CIN1 CBST LT7101 L1 SW R4 VOUT EXTVCC OVLO R1 VFB R5 PLLIN/MODE FREQ RFREQ COUT INTVCC R2 VPRG1 ITH PGND SGND CVCC VOUT COUT VIN CIN2 CIN1 R3 GND L1 CBST R4 R5 CVCC R2 R1 RFREQ 7101 F13 VIAS TO GROUND PLANE VIAS TO OUTPUT SUPPLY (VOUT) VIAS TO INTVCC OUTLINE OF GROUND PLANE Figure13. Example PCB Layout VIN 5V TO 100V 4.7F 100V X7R VIN RUN BOOST 0.1F LT7101 SW VPRG1 VFB OVLO EXTVCC ITH PLLIN/MODE fsw = 300kHz L: WURTH 7447714470 SGND VOUT 5V 1A 47F 6.3V X5R VPRG2 FREQ 47H INTVCC PGND 1F 7101 F14 Figure14. High Efficiency 5V to 100V Input to 5V/1A Output Step-Down Regulator 34 Rev. 0 For more information www.analog.com LT7101 TYPICAL APPLICATIONS VIN 12V TO 100V VIN 4.7F 100V X7R BOOST 0.1F LT7101 RUN 100H SW VFB EXTVCC VPRG2 VPRG1 PLLIN/MODE FREQ INTVCC SGND fsw = 300kHz L: WURTH 7447714101 22F 25V X5R ITH OVLO VOUT 12V 1A PGND 1F 7101 F15 Figure15. High Efficiency 12V to 100V Input to 12V/1A Output Step-Down Regulator VIN 4.4V TO 100V VIN 4.7F 100V X7R BOOST 0.1F LT7101 RUN 33H SW VPRG2 VFB OVLO EXTVCC 100F 6.3V X5R VPRG1 ITH PLLIN/MODE FREQ INTVCC SGND fsw = 300kHz L: WURTH 7447714330 VOUT 3.3V 1A PGND 1F 7101 F16 Figure16. High Efficiency 4.4V to 100V Input to 3.3V/1A Output Step-Down Regulator VIN 5V TO 100V BEAD FB1 4.7F 100V X7R BEAD FB2 0.22F 100V X7R 0.1F 100V X7R 4.7F 100V X7R + C1 10F 125V VIN BOOST SW VFB RUN 4.7F 100V X7R RIND PLLIN/MODE ITH FREQ 17.8k VOUT 5V 1A 47F 6.3V X6S EXTVCC VPRG1 OVLO VPRG2 fSW = 400kHz C1: SUNCON 125HVH10M L2: COILCRAFT XAL6060-333ME FB1, FB2: MURATA BLM31PG121SN1 0.1F 33H, L2 LT7101 SGND 8.87k INTVCC PGND 1F 7101 F17 Figure17. Low EMI 5V to 100V Input to 5V/1A Output Step-Down Regulator Rev. 0 For more information www.analog.com 35 LT7101 TYPICAL APPLICATIONS 1.1A, 6-Cell SLA Battery Charger with Charge Termination VIN 18V TO 72V VIN 2.2F 100V X7R RUN BOOST 20k 47H 402k 0.1% VFB VPRG1 IMON VPRG2 INTVCC RIND ITH FREQ PLLIN/MODE SGND VBAT 13.5V TO 14.3V 1.1A SW EXTVCC OVLO 6.49k 0.1F LT7101 IN- V+ 100k 115k 1F PGND 10k R1 115k 100k 0.1% LTC1440 IN+ REF HYST V- 10F 25V X7R 1.74M OUT 40.2k 0.1% GND 7101 TA03 fsw = 500kHz L: COILCRAFT XFL6060-473ME 36 R1 = 125k (ITERM + 0.61) 0.96 - ITERM 1.1A CHARGING CURRENT 14.3V TOPPING CHARGE VOLTAGE WITH 0.15A TERMINATION 13.4V FLOAT VOLTAGE Rev. 0 For more information www.analog.com LT7101 PACKAGE DESCRIPTION UHE Package Variation: UHE36(26) 36-Lead Plastic QFN (5mm x 6mm) (Reference LTC DWG # 05-08-1983 Rev O) 0.70 0.05 5.50 0.05 2.60 0.05 4.10 0.05 3.00 REF PACKAGE OUTLINE 3.60 0.05 0.25 0.05 0.50 BSC 5.10 0.05 6.50 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 1.50 REF 5.00 0.10 0.00 - 0.05 0.200 REF R = 0.10 TYP 29 30 32 33 34 35 36 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1.25 REF 28 1 27 3.60 0.10 24 6.00 0.10 1.75 REF 2 3 4 5 6 23 22 2.60 0.10 21 20 10 19 0.8 REF (UHE36(26)) QFN 0714 REV O 0.75 0.05 18 0.25 0.05 11 R = 0.125 TYP 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 37 LT7101 TYPICAL APPLICATION 4.4V to 32V Input to 3.3V/1A Output, 2MHz Automotive Supply with Overvoltage Lockout and 100V Input Tolerance BEAD FB1 4.7F 100V X7R 50 BEAD FB2 4.7F 100V X7R + 0.22F 100V X7R VIN BOOST 0.1F LT7101 SW VFB RUN 4.7F 100V X7R x3 EXTVCC 1.74M 0.1F 100V X7R 60.4k OVLO PLLIN/MODE VPRG2 RIND VPRG1 ITH FREQ 57.6k SGND VERTICAL POLARIZATION 40 4.7H 2MHz CLK OR GND VOUT 3.3V 1A 10F 6.3V X5R AMPLITUDE (dBV/m) VIN 4.4V TO 32V (100V MAX) Radiated EMI Performance (CISPR25) Radiated Emission Test with Class 5 Peak Limits 30 20 10 CLASS 5 PEAK LIMIT LT7101 64.9k INTVCC 0 PGND 1F 7101 TA04a 0 100 200 300 14VIN TO 3.3VOUT AT 1A fSW = 2MHz 400 500 600 FREQUENCY (MHz) 700 800 900 1000 7101 TA04b fSW = 2MHz OVERVOLTAGE LOCKOUT AT 36V L: COILCRAFT XFL4020-472ME FB1, FB2: MURATA BLM31PG601SN1 C1: SUNCON 125HVH10M RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC7103 105V, 2.3A, Low EMI Synchronous Step-Down Regulator VIN: 4.4V to 105V, 1VVOUTVIN, IQ = 2A, ISD = 0.7A, Programmable Output Current with Current Monitor, 5mmx6mm QFN-36 LTC7801 150V, Low IQ, Synchronous Step-Down DC/DC Controller 4V VIN 140V, 150V ABS Max, 0.8V VOUT 60V, IQ = 40A, PLL Fixed Frequency 320kHz to 2.25MHz LTC7138 High Efficiency, 140V, 400mA Step-Down Regulator VIN: 4V to 140V, 0.8VVOUTVIN, IQ = 12A, ISD = 1.4A, MSE Package LTC7810 150V Low IQ, Dual Synchronous Step-Down DC/DC Controller VIN: 4.5V to 140V, 1VVOUT60V, IQ = 16A, ISD = 1.5A, 7mm x 7mm LXE-48 (eLQFP) Package LTC3630A 76V, 500mA Synchronous Step-Down DC/DC Regulator VIN: 4V to 76V, 0.8VVOUTVIN, IQ = 12A, ISD = 5A, 3mm x 5mm DFN16, MSOP-16E Packages LTC7800 60V, Low IQ, High Frequency Synchronous Step-Down DC/DC Controller 4V VIN 60V, 0.8V VOUT 24V, IQ = 50A, PLL Fixed Frequency 320kHz to 2.25MHz LTC7862 140V N-Channel Switching Surge Stopper 4V VIN 140V, 0.8V VOUT 60V, IQ = 40A, PLL Fixed Frequency, TSSOP and QFN Packages LTC3892/ LTC3892-1 60V, Low IQ, Dual 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle VIN: 4V to 60V, 0.8VVOUT0.99 *VIN, IQ = 29A, ISD < 14A, 5mm x 5mm QFN-32, TSSOP-28E Packages LTC3895 150V Low IQ, Synchronous Step-Down DC/DC Controller PLL Fixed Frequency 50kHz to 900kHz, 4V VIN 140V, 0.8V VOUT 60V, IQ = 40A LTC4366-1/ LTC4366-2 High Voltage Surge Stopper VIN: 9V to > 500V, IQ = 50A, ISD < 14A, 2mm x 3mm DFN-8, TSOT-8 Packages LTC3649 60V, 4A Synchronous Step-Down Regulator with Rail-to-Rail Programmable Output VIN: 3.1V to 60V, 0VVOUTVIN-0.5V, Programmable Output Current with Current Monitor, 4mm x 5mm QFN and TSSOP Packages 38 Rev. 0 04/19 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2019