S0401-01
VIN
EN
Cdly
GND
RST
GND
COMP
VSENSE
PGND
Vout
Vsupply
SS
SYNC
SW
BOOT
Rslew
RST_TH
RT
VReg
TPS55332
GND
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
2.2-MHz, 60-V OUTPUT STEP UP DC/DC CONVERTER
Check for Samples: TPS55332-Q1
1FEATURES DESCRIPTION
2• Withstands Transients up to 60 V, Boost Input
Operating Range of 1.5 V to 40 V (VIN) The TPS55332 is a monolithic high-voltage switching
regulator with integrated 3-A, 60-V power MOSFET.
• Peak Internal Switch Current: 5.7 A (typ) The device can be configured as a switch mode
• 2.5 V ± 1.5% Feedback Voltage Reference step-up power supply with voltage supervisor. Once
• 80 kHz to 2.2 MHz Switching Frequency the internal circuits have stabilized with a minimum
• High Voltage Tolerant Enable Input for On/Off input supply of 3.6 V, the system can then have an
input voltage range from 1.5 V to 40 V, to maintain a
State fixed boost output voltage. For optimum performance,
• Soft Start on Enable Cycle VIN/Vout ratios should be set such that the minimum
• Slew Rate Control on Internal Power Switch required duty cycle pulse > 150 ns. The supervisor
circuit monitors the regulated output and indicates
• External Clock Input for Synchronization when this output voltage has fallen below the set
• External Compensation for Wide Bandwidth value. The TPS55332 has a switching frequency
Error Amplifier range from 80 kHz to 2.2 MHz, allowing the use of
• Programmable Power on Reset Delay low profile inductors and low value input and output
capacitors. The external loop compensation gives the
• Reset Function Filter Time for Fast Negative user the flexibility to optimize the converter response
Transients for the appropriate operating conditions. Using the
• Programmable Undervoltage Output enable pin (EN), the shutdown supply current is
Monitoring, Issuance of Reset if Output Falls reduced to 1 mA. The device has built-in protection
Below Set Threshold features such soft start on enable cycle,
• Thermal Shutdown to Protect Device During pulse-by-pulse current limit, and thermal sensing and
shutdown due to excessive power dissipation.
Excessive Power Dissipation
• ILIM Threshold Protection (Current Limit) SIMPLIFIED SCHEMATIC
• Operating Junction Temperature Range: –40°C
to 150°C
• Thermally Enhanced 20-Pin HTSSOP
PowerPAD™ Package
APPLICATIONS
• Lighting
• Battery Powered Applications
• Qualified for Automotive Applications
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
DEVICE NUMBER CURRENT OUTPUT ORDERABLE NUMBER
TPS55332 0.5 A TPS55332QPWPRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
Unregulated input voltages (VIN, EN)(2) ( SW) (2) (3) –0.3 to 60 V
VIUnregulated input voltages (BOOT) –0.3 to 8 V
VReg Regulated voltage –0.3 to 60 V
Logic level signals (RT, RST, SYNC, VSENSE, RST_TH) (2) –0.3 to 5.5 V
Logic level signals (SS, Cdly) (2) –0.3 to 8 V
Logic level signals (COMP)(2) –0.3 to 7 V
TJOperating virtual junction temperature range –40 to 150 °C
TSStorage temperature range –55 to 165 °C
ESD Electrostatic discharge HBM (4) 2 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Absolute negative voltage on these pins not to go below –0.6 V.
(4) The human body model is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VIUnregulated buck supply input voltage (VIN, EN) 3.6 40 V
VReg Output voltage range 2.5 50 V
Bootstrap capacitor (BOOT) 3.6 8 V
Switched outputs (SW) 3.6 52 V
Logic level inputs (RST, VSENSE, RST_TH, Rslew, SYNC, RT) 0 5.25 V
Logic level inputs (SS, Cdly, COMP) 0 6.5 V
qJA Thermal resistance, junction to ambient(1) 35 °C/W
qJC Thermal resistance, junction to case(2) 10 °C/W
TJOperating junction, temperature range(3) –40 150 °C
(1) This assumes a JEDEC JESD 51-5 standard board with thermal vias and high-K profile – See PowerPAD section and application note
from Texas Instruments (SLMA002) for more information.
(2) This assumes junction to exposed PAD.
(3) This assumes TA= TJ– power dissipation × qJA (junction to ambient).
2Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
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SLVS939A –JUNE 2009–REVISED JUNE 2010
DC ELECTRICAL CHARACTERISTICS
VIN = 7 V to 40 V, EN = High, TJ= –40°C to 150°C (unless otherwise noted)
TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
Info VIN Supply voltage on VIN line Normal mode – buck mode after start up 1.5 40 V
PT Iq-Normal Bias current, normal mode 4.2 8 mA
PT ISD Shutdown EN = 0 V, VIN = 12 V, TA= 25°C 2 4 mA
SWITCH MODE SUPPLY; VReg/Vout
Info VReg Regulator output VSENSE = 2.5 V in boost mode (1) Vin×1.05 50 V
CT VSENSE Feedback voltage VIN = 12 V 2.463 2.5 2.538 V
PT RDS(on) Internal switch resistance Measured across VSWD and GND 500 mΩ
Info ICL Switch current limit VIN = 7 V to 28 V 5.7 A
tON-Min 50 100 150
Info Duty cycle pulse width Bench mode = 500 kHz ns
tOFF-Min 50 100 150
PT fsw Switch mode frequency Set using external resistor on RT pin 80 2200 kHz
PT fsw Internal oscillator frequency –10% 10%
ENABLE (EN)
PT VIL Low input threshold 0.7 V
PT VIH High input threshold 1.7 V
PT ILeakage Leakage into EN terminal EN = 24 V 35 mA
RESET DELAY (Cdly)
PT IOExternal capacitor charge current EN = high 1.4 2 2.6 mA
PT VThreshold Switching threshold Output voltage in regulation 1.8 2 2.4 V
RESET OUTPUT (RST)
Info trdly POR delay timer Based on Cdly capacitor, Cdly = 4.7 nF 3.6 7 ms
PT RST_TH Reset threshold for VReg Check RST output 0.768 0.832 V
PT t RSTdly Filter time Once VRST_TH or OV_TH Is detected, 10 20 35 ms
delay before RST Is asserted low
SYNCHRONIZATION (SYNC)
PT VSYNC Low-level input voltage, VIL 0.7 V
PT High-level input voltage, VIH 1.7 V
PT ILeakage Leakage current SYNC = 5 V 65 95 mA
PT SYNC Input clock VIN = 12 V, fsw < fext < 2 × fsw 80 2200 kHz
Info SYNCtrans External clock to internal clock No external clock, VIN = 12 V 32 ms
Info SYNCtrans Internal clock to external clock External clock = 500 kHz, VIN = 12 V 2.5 ms
CT SYNCCLK Minimum duty cycle 30%
CT SYNCCLK Maximum duty cycle 70%
Rslew
CT IRslew Slew current Rslew = 50 kΩ, Calculated not measured 20 mA
CT IRslew Slew current Rslew = 50 kΩ, Calculated not measured 100 mA
Soft Start (SS)
PT Iss Soft start current 40 50 60 mA
(1) Voltage ratio of input to output in boost mode is 1:10 (max) and up to 50 V output max.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s) :TPS55332-Q1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
NC
SYNC
GND
EN
RT
Rslew
RST
Cdly
GND
BOOT
VIN
SW
PGND
VReg
COMP
VSENSE
RST_TH
GND
SS
PWP Package
(Top View)
P0021-03
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 7 V to 40 V, EN = High, TJ= –40°C to 150°C (unless otherwise noted)
TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
Thermal shutdown junction 200
CT TSD 175 °C
temperature
CT THYS Hysteresis 30 °C
PT: Production tested
CT: Characterization tested only, not production tested
Info: User Information only, not production tested
DEVICE INFORMATION
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
NC 1 NC Connect to ground
NC 2 NC Connect to ground
SYNC 3 I External synchronization clock input, 62-kΩ(typ) pull-down resistor
GND 4 I Connect to ground
EN 5 I Enable input, high voltage tolerant
RT 6 O Resistor to program internal oscillator frequency
Rslew 7 O Internal switch programmable slew rate control
RST 8 O Reset output open drain (active low)
Cdly 9 O Reset delay timer (programmed by external capacitor)
GND 10 O Analog ground, DVSS and SUB
SS 11 O Programmable soft-start. (external capacitor)
GND 12 I Connect to ground
RST_TH 13 I Input for RESET circuitry to detect undervoltage on output (adjustable threshold)
VSENSE 14 I Feedback input for voltage mode control
COMP 15 O Error amplifier output
VReg 16 I Internal low side FET to load output during start up or limit over shoot
PGND 17 O Power ground connection
SW 18 I/O Switched drain output/input
VIN 19 I Unregulated input voltage
BOOT 20 O Bootstrap capacitor pump
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Product Folder Link(s) :TPS55332-Q1
–
–
+
+
VIN
EN
Cdly
GND
RST
GND
COMP
VSENSE
PGND
Vout
Vsupply
Modulator
Error
amp
0.8 V ref
2.5 V ref
ref
SS
0.8V
SYNC
Vreg
SW
BOOT
Rslew
RST_TH
RT
VReg
R9
R8
R7
R3
R4
C1
C2
C5
CO
C4
L
D1
D2
C3
D3
R6
R5
2.5V
R1
R2
GND
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Bandgap
Ref
Internal
Vreg
Internal
Supply
Selectable
Oscillator Thermal
Sensor
Gate Drive With
Over-Current Limit
for Internal Switch
Voltage
Comp
Reset With
Delay Timer
B0354-01
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
TYPICAL APPLICATION SCHEMATIC (Boost Converter)
NOTE: An integrated forward biased diode is between VReg and VIN. VReg is tied to Vout and used to bias VIN when Vout >
Vsupply. However, the minimum Vsupply operating voltage at power-up (when Vout < Vsupply) is 3.6 V + 2 diode
drops. After power-up (when Vout > Vsupply) the minimum Vsuppy = 1.5 V + 2 diode drops. VReg < 5.8 V and VIN <
3.6 V. Converter non-operational.
NOTE: VIN is the voltage at VIN before VReg > Vsupply.
Figure 1. TPS55332 Functional Block Diagram
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IL− LoadCurrent − A
30
40
50
60
70
80
90
100
0.0 0.1 0.2 0.3 0.4 0.5
η− Efficiency − %
G001A
Vout=25.5V
C =10 F
f
L H
T =25 C
O
sw
A
m
°
=2MHz
=22m
VIN =8V
VIN =13.5V
VIN =18V
IL− LoadCurrent − A
20
30
40
50
60
70
80
90
100
0.0 0.1 0.2 0.3 0.4 0.5
η− Efficiency − %
G002A
Vout=25.5V
C =
L =22
T = C
O
sw
A
10 F
f =180kHz
H
25
m
m
°
VIN =13.5V
VIN =18V
TA − Free-Air Temperature − °C
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
−40 −20 0 20 40 60 80 100 120
VSENSE Ref Voltage − V
G003
7V
48V
24V
TA − Free-Air Temperature − °C
0
1
2
3
4
5
6
7
8
9
−40 −20 0 20 40 60 80 100 120
VIN Leakage Current − µA
G004
12V
24V
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
TYPICAL CHARACTERISTICS
EFFICIENCY (%) EFFICIENCY (%)
vs vs
LOAD CURRENT (A) LOAD CURRENT (A)
Figure 2. Figure 3.
VSENSE Ref VOLTAGE (V) VIN LEAKAGE CURRENT (mA)
vs vs
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 4. Figure 5.
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TA − Free-Air Temperature − °C
3.5
3.7
3.9
4.1
4.3
4.5
4.7
4.9
5.1
5.3
5.5
−40 −20 0 20 40 60 80 100 120
Iq − Normal Current Consumption − mA
G006
7V
24V 12V
TA − Free-Air Temperature − °C
0.15
0.20
0.25
0.30
0.35
0.40
−40 −20 0 20 40 60 80 100 120
Rds of Power FET − Ω
G005
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
TYPICAL CHARACTERISTICS (continued)
Rds OF POWER FET (Ω) NORMAL CURRENT CONSUMPTION (mA)
vs vs
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 6. Figure 7.
OVERVIEW
The TPS55332 operates as a step up (boost) converter; the feedback concept is voltage mode control using the
VSENSE terminal, with cycle-by-cycle current limit.
The voltage supervisory function for power-on-rest during system power-on is monitoring the output voltage, and
once this has exceeded the threshold set by RST_TH, a delay of 1.0 ms/nF (based on the capacitor value on the
Cdly terminal) is invoked before the RST line is released high. Conversely, on power down, once the output
voltage falls below the same set threshold (ignoring hysteresis), RST is pulled low only after a de-glitch filter of
approximately 20 ms (typ) expires. This is implemented to prevent RST from being triggered due to fast transient
noise on the output supply.
Soft start is activated on every enable cycle and limits the power stored in the inductor by duty cycle control. Soft
start duration is set by an external capacitor on the SS terminal.
If thermal shutdown is invoked due to excessive power dissipation, the internal switch is disabled and the
regulated output voltage starts to decrease. Depending on the load line, the regulated voltage can decay and the
RST_TH threshold may assert RST output low after the output voltage drops below the set threshold.
DETAILED DESCRIPTION
The TPS55332 is a step up (boost) dc/dc converter using voltage-control mode scheme. The following sections
include descriptions of the individual pin functions.
Input Voltage (VIN)
The VIN pin is the input power source for the TPS55332. This pin must be externally protected against voltage
level transients greater than 60 V and reverse battery. In boost mode the input current drawn from this pin is
pulsed, with fast rise and fall times. Therefore, this input line requires a filter capacitor to minimize noise.
Additionally, for EMI considerations, an input filter inductor may also be required.
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R8
Vout = Vref 1 + (Volts)
R7
æ ö
ç ÷
è ø
( )
Vout Vref R8 R7
R8
tol = tol + tol + tol
R8+R7
æ ö ´
ç ÷
è ø
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
Output Voltage (Vout)
The output voltage, Vout, is generated by the converter supplied from the battery voltage VIN and external
components (L, C). The output is sensed through an external resistor divider and compared with an internal
reference voltage.
The value of the adjustable output voltage in boost mode is selectable between VIN × 1.05 to 50 V if the
minimum ON time (ton) and minimum OFF times are NOT violated by choosing the external resistors, according
to the following relationship:
(1)
Where:
R7 and R8 are feedback resistors
Vref = 2.5 V (typ)
The internal reference voltage Vref has a ±1.5% tolerance. The overall output voltage tolerance is dependent on
the external feedback resistors. To determine the overall output voltage tolerance, use the following relationship:
(2)
Typically, an output capacitor within the range of 10 mF to 400 mF is used. This terminal has a filter capacitor with
low ESR characteristics in order to minimize output ripple voltage.
Regulated Supply Voltage (VReg)
There is an integrated forward biased diode between VReg and VIN. VReg is tied to Vout and used to bias VIN
when Vout > Vsupply.
Over-Current Protection (SW)
Over-current protection is implemented by sensing the current through the NMOS switch FET. The sensed
current is then compared to a current reference level representing the over-current threshold limit. If the sensed
current exceeds the over-current threshold limit, the over-current indicator is set true. The system ignores the
over-current indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn-on
noise glitches.
Once the over-current indicator is set true, over-current protection is triggered. The MOSFET is turned off for the
rest of the cycle after a propagation delay. The over-current protection scheme is called cycle-by-cycle current
limiting. If the sensed current continues to increase during cycle-by-cycle current limiting, the temperature of the
device starts to rise, and the TSD kicks in and shuts down switching until the device cools down.
Oscillator Frequency (RT)
The oscillator frequency is selectable by means of a resistor placed at the RT pin. The switching frequency (ƒsw)
can be set in the range of 80 kHz to 2.2 MHz. In addition, the switching frequency can be imposed externally by
a clock signal (ƒext) at the SYNC pin with ƒsw < ƒext < 2 × ƒsw. In this case the external clock overrides the
switching frequency determined by the RT pin, and the internal oscillator is clocked by the external
synchronization clock input.
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RT Resistor − kΩ
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
0 200 400 600 800 1000 1200
fsw − Switching Frequency − kHz
G007
TA = 25°C
8V
14V
24V 40V
dly
1 ms
tdelay = trdly C = C, Where C = capacitor on C pin
nF
æ ö
´ ´
ç ÷
è ø
TPS55332-Q1
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SLVS939A –JUNE 2009–REVISED JUNE 2010
Enable / Shutdown (EN)
The Enable pin provides electrical on/off control of the regulator. Once the Enable pin voltage exceeds the
threshold voltage, the regulator starts operation and the internal soft start begins to ramp. If the Enable pin
voltage is pulled below the threshold voltage, the regulator stops switching and the internal soft start resets.
Connecting the pin to ground or to any voltage less than 0.7 V disables the regulator and activates shutdown
mode. The quiescent current of the TPS55332 in shutdown mode is typically < 2 mA. This pin has to have an
external pull up or pull down to change the state of the device.
Reset Delay (Cdly)
The Reset delay pin sets the desired delay time for asserting the RST pin high after the supply has exceeded the
programmed Vreg_RST voltage. The delay may be programmed in the range of 2.2 ms to 200 ms using
capacitors in the range of 2.2 nF to 200 nF. The delay time is calculated using Equation 3:
(3)
Reset Pin (RST)
The RST pin is an open-drain output. The power-on reset output is asserted low until the output voltage exceeds
the programmed Vreg_RST voltage threshold and the reset delay timer has expired. Additionally, whenever the
Enable pin is low or open, RST is immediately asserted low regardless of the output voltage. There is a reset
de-glitch timer to prevent a reset being invoked due to short negative transients on the output line. If a thermal
shut down occurs due to excessive thermal conditions this pin is asserted low, where switching is commanded
off and the output drops below the rest threshold set on the RST_TH terminal.
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VIN
VReg
Cdly
RST
Css
Set by RST_TH
Terminal
20 s
(Typ-Deglitch Time)
m
Power On Condition/Reset Line Power Down Condition/Reset Line
0.92 V´Reg
VIN
VReg
Cdly
RST
tdelay
Css
T0435-01
CSS
1< 10 T
GBW
´
( )
SS -6
C 3.5
Time Tc = (sec)
40 10
´
´
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
Boost Capacitor (BOOT)
This capacitor provides gate drive voltage for the Internal MOSFET switch. X7R or X5R grade dielectrics are
recommended due to their stable values over temperature.
Soft Start (SS)
To limit the start-up inrush current, an internal soft start circuit is used to ramp up the reference voltage from 0 V
to its final value. The switch duty cycle starts with narrow pulses and increases gradually as the voltage on the
Css capacitor ramps up. The output current on this pin charges the capacitor up to 6.6 V (typ).
The boost soft start is dependent on the gain bandwidth (GBW) of the loop. Therefore, in this configuration the
Css equation only holds when:
(4)
GBW is dependent on the compensation technique used. TYPE1 is the slowest.
Where:
Tcss is the time it takes for Vcss to reach ~3.5 V
GBW = ƒc of the converter
(5)
Where:
C = Capacitor Css on the SS pin
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Product Folder Link(s) :TPS55332-Q1
Rslew − kΩ
0
10
20
30
40
50
60
70
5 7 9 11 13 15 17 19 21
tr − Rise T ime − ns
G008
TA = 25°C
VIN = 14V
VIN = 24V
VIN = 5V
VIN = 8V
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
Synchronization (SYNC)
The SYNC pin inputs an external clock signal that synchronizes the switching frequency. The synchronization
input over-rides the internally fixed oscillator signal. The synchronization signal has to be valid for approximately
2 clock cycles (pulses) before the transition is made for synchronization with the external frequency input. If the
external clock input is does NOT transition low or high for 32 ms (typ), the system defaults to the internal clock
set by the Rosc pin.
Regulation Voltage (VSENSE)
This pin is used to program the regulated output voltage based on a resistor feedback network monitoring the
Vout voltage. The selected ratio of R7 and R8 sets the output voltage.
Reset Threshold (RST_TH)
This pin is programmable to set the under-voltage monitoring of the regulated output voltage. The resistor
combination of R5 and R6 is used to program the threshold for detection of under-voltage.
Reset Threshold = RST_TH = Vref (1 + (R6/R5)), (6)
Recommended range: 70% to 92% of the regulation voltage
The internal reference Vref is set at 0.8 V ±1.5%
Slew Rate Control (Rslew)
This pin controls the switching slew rate of the internal power NMOS. The slew rate is set by an external resistor
with a slew rate range shown for rise and fall times. The range of rise time tr= 20 ns to 60 ns and fall time
tf= 60 ns to 250 ns, with Rslew range of 5 kΩto 20 kΩ(see Figure 8 and Figure 9).
Figure 8. FET Rise Time (tr)
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Rslew − kΩ
0
50
100
150
200
250
300
5 7 9 11 13 15 17 19 21
tf − Fall T ime − ns
G009
TA = 25°C
VIN = 5V
VIN = 8V
VIN = 14V
VIN = 24V
R8
C4
L
V =V
O reg
V =2.5V
ref
VSENSE
COMP
CO
CO-ESR
R7
Error
Amp
S0402-01
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
Figure 9. FET Fall Time (tf)
Thermal Shutdown
The TPS55332 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the MOSFET is turned off. The device is restarted under
control of the slow start circuit automatically when the junction temperature drops below the thermal shutdown
hysteresis trip point.
Loop Control Frequency Compensation
Figure 10. Type 1 Compensation
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Load IN
sat
IV
I > + × 15μs
D × efficiency L
æ ö
ç ÷
è ø
( )2O
CCM CCM
O
max
sw
V
0.8 D 1 D I
L = (Henries)
2 × ƒ
æ ö
´ ´ - ´ ç ÷
è ø
IN
CCM
O
V
D = 1
V
æ ö
-ç ÷
è ø
S
2 L
O(max) 1 R T
dcm-min
sw 0
I
C (Farads)
ƒΔV
é ù
´
´ -
ê ú
´
ê ú
ë û
³´
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
The boost converter operating in continuous conduction mode (CCM) has a right-half-plane (RHP) zero with the
transfer function. The RHP zero causes the converter to respond to a circuit disturbance in the opposite direction
to that needed to support the output load transition (positive feedback). This complicates loop compensation and
limits the converter bandwidth, and requires an increase in the output filter capacitor.
The converter can be designed to operate in discontinuous conduction mode (DCM) with a smaller inductance
value for the inductor over the full range of the operating conditions. This may be difficult to achieve and other
issues like instability may occur if the converter enters CCM.
The inductor saturation current Isat must satisfy the following:
(7)
Where:
D=VIN/VO
The converter designed for CCM with external loop compensation factors the maximum output load current, the
ESR of the output filter capacitor, the inductance used for the inductor, the input voltage range, and the output
voltage required.
DCM Operation
The control to output transfer function for the boost in DCM has a single pole. The energy in the inductor is
completely discharged during every switching cycle (inductor current is reduced to zero). The small inductor
value for DCM compared to CCM operation shifts the RHP zero frequency close to the switching frequency, see
Equation 11. In this mode, the RHP is not a factor for compensation of the feedback loop, additionally the
frequency of the pole associated with the inductor is also increased to a higher frequency.
The maximum inductance to keep the boost converter running in DCM over the full operating range is given by
Equation 8:
(8)
Where:
(9)
VO= Output voltage
IO= Maximum output current
VIN = Minimum input voltage
Three elements of the output capacitor contribute to the impedance (output voltage ripple), ESR, ESL, and
capacitance.
During discontinuous conduction mode operation, the minimum capacitance needed to limit the voltage ripple
due to the capacitance of the capacitor is given by Equation 10:
(10)
Where:
R = min load resistance,
Ts= clock period,
ƒsw = switching frequency,
ΔV0= output voltage ripple desired
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s) :TPS55332-Q1
O
O
ΔV
ESR (Ohms)
ΔI
£
LC RΗP-zero
= 0.1 ƒ¦ ´
RΗP-zero
LC
ƒM>
¦
C RΗP-zero
= 0.33 ƒ¦ ´
IN
LC
O
V
1
= (Hz)
V
2 LCo
¦ ´
p
2
IN
RHP-zero
O
V
R
= (Hz)
2 L V
æ ö
¦ ´ ç ÷
è ø
p
ESR
R
= (Hz)
2 Co ESR
¦´p
4
p
1
= (Hz)
2 C R8
¦p
O(max) IN
(ccm min)
O O sw
IV1
C 1 (Farads)
V V
æ ö
³ -
ç ÷
Dè ø f
L O IN-max
I = 0.4 I (Amperes) for VD ´
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
The ESR of the output capacitor needed to limit the output ripple voltage is given by Equation 11:
(11)
CCM Operation
In continuous conduction mode of operation the RHP zero complicates the loop compensation. This limits the
bandwidth of the converter and may require a larger value output filter capacitor to compensate for loop
response. The benefit of this mode is a lower switch and inductor current compared to DCM. This results in
reduced power dissipation and size of the power switch, input capacitor, and output capacitor. The output filter
capacitor value may need to be increased such that
ƒLC ≤0.1 ƒRHP
The following requirements for compensating the loop have to be satisfied for the control-to-output gain of a CCM
boost operation.
(12)
(13)
Where:
M = 10 – for tantalum capacitors
M = 15 – for ceramic capacitors
(14)
(15)
Where:
L = Inductor value,
Co = Output capacitor,
VIN = Input voltage, and
VO= Output voltage
(16)
(17)
The feed-forward compensation network type 1 is calculated using the pole frequency in Equation 18:
(18)
The minimum output capacitor required for a desired output ripple voltage is given by Equation 19:
(19)
The minimum inductor value needed to ensure CCM from maximum to 25% of maximum load is determined by
choosing the value of the inductor to have a ripple current of approximately 40% of the maximum output load
current at maximum input voltage of the system.
(20)
To maintain ccm operation with at least a 10% of maximum load current (IO-DLM ≥0.1 × IO-max) The inductor is
given by Equation 21:
14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS55332-Q1
( )
IN ccm ccm
O-Dccm sw
V
L = D 1 - D (Henries)
2 I ´ ´
´ ´ f
CRMS O
D
I = I
1 D
´
-
O
O(max) O
max
ΔV
ESR (Ohms)
IΔI
+
1 D 2
£
-
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
(21)
Where:
Dccm = 0.5,
VIN = Typical operating voltage
Choosing an inductor value less than the one determined by Equation 21 may cause the converter to go into
DCM operation during low output currents. This may not be a problem if the loop compensation allows for good
phase margin.
The ripple current flowing through the output capacitor ESR causes power dissipation in the capacitor.
Equation 17 gives the RMS value of the ripple current flowing through the output capacitance.
(22)
Where:
D = Duty cycle
For continuous inductor current mode operation, the ESR needed to limit the ripple voltage ΔVOto volts
peak-peak is:
(23)
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s) :TPS55332-Q1
-40dB/dec
+20dB/dec
+20dB/dec
Gain – dB
Phase
Freq-Hz
Freq-Hz
fZfCfP
fLC fRHP-ZERO
0°
-90°
-180°
-270°
Black; double pole system
Blue; RHP – Zero system
Reflected RHP – Zeroimpact
Reflected Phase boost contribution
Red: feed forward compensation (1-zero, 1-pole system)
Phaseboostcontribution
bycompensationcircuit
fLC
fRHP-ZERO =M
fC Z
=2 f´
G010
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
Loop Compensation for Stability Criteria
The Bode-Plot above is an illustration of stability criteria and is used to ensure converter performance based on
the type of loop compensation implemented.
16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS55332-Q1
GND
GND
GND
VIN = 6 to 25V
Enable
1
JP1
1.25MR1
2k
R3
0.47uF
C9
GND 100k
R4
1nF
C1
100uH
21
L1
10k
R7
267k
R5
V_REG
V_REG
VIN
GND
30BQ100
D3
GND
V_REG
30BQ100
D1
VIN
GND
GND
GND
10.7k
R6
30BQ100
D2
1nF
C5
GND
0.1uFC8
0.1uF
C4
2.2nF
C7
1
2
J1
1
2
J2
VOUT= 26V
IOUT= 300mA
GND
GND
GND
GND
GND
4.99kR2
GND
GND
10uF
C2
10uF
C6
10uF
C3
fsw = 80KHz
Rslew
7
GND
4
NC
1
SS 11
VSENSE 14
PGND 17
BOOT 20
RST
8
Cdly
9
GND
10
EN
5
NC
2
SYNC
3
RST_TH 13
GND 12
VReg 16
VIN 19
SW 18
RT
6COMP 15
PAD
21
U1 TPS55332PWP
GND
GND
S001
ripple ESR
O O
V = I × ESR (Volts)
cap
OIN
(min ripple)
ripple sw
IV1
C = 1
Vo Vo
æ ö
-
ç ÷
è ø f
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
APPLICATION INFORMATION
Design Guide – Step By Step Design Procedure
The following table lists the requirements of a switching regulator design.
PARAMETER VALUE
Input voltage, VIN 6 V to 25 V, with typical operating voltage = 14 V
Output voltage, V 26 V ± 2%
Maximum output current, IO0.3 A
Transient response 0A to 0.25A 5%
Switching frequency, ƒsw 80 kHz
Reset threshold 84% of output voltage
Vo_ripple 520 mV peak to peak at capacitance
Vo_transient 92% of output voltage
The design considers the converter to operate in CCM for most of the operating range and in DCM during less
than 40% of the maximum output load rating.
Output Capacitor (Co)
Selection of the output capacitor in CCM using Equation 19 gives a capacitor value of 5.5 mF. Select 10 mF as
standard value.
Output ripple voltage is a product of output capacitor ESR and ripple current on the output capacitor Co.
The minimum output capacitor required for a desired output ripple voltage is given by:
(24)
(25)
The minimum capacitance needed for the output voltage ripple specification, using Equation 19,C↓(min ↓ripple)
= 5.55 mF.
Using Equation 20, the transient response should be taken into consideration when selecting the output
capacitor. The minimum capacitance required for a duration dt with a load transient Itran to allow a maximum
output voltage droop of Vo_droop is:
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s) :TPS55332-Q1
tran dt tran
(min tran)
droop droop c
I I 1
C = = (Farads)
Vo Vo 4
´
´f
diode d O
P = V I (1 D) (Watts)
¦´ ´ -
( )
( )
I-min O
O
I-RMS O
I min I min
V V
(V )
I = I (Amperes)
V V
- -
-
´ ´
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
(26)
Where,
dt is approximated to 1 / 4 × ƒc ( ƒc = 10-kHz bandwidth)
This gives a capacitance of 6.25 mF. Allowing for tolerances and temperature variations, use a 10-mF standard
value output capacitor.
Output Inductor Selection (Lo) for CCM
Using Equation 21, the minimum lead current for ccm operation is 40% of maximum output current, IO-DCM = 120
mA. The inductor value is estimated to be L = 100 mH.
Output Diode
The TPS55332 requires an external output diode which conducts when the power switch is turned off. This
provides the path for the inductor current to the output capacitor. The important factors in selecting the rectifier
are: fast switching, reverse breakdown voltage, current rating, and forward-voltage drop. The breakdown voltage
should be greater than the maximum output voltage; the current rating must be two times the maximum switch
output current. The forward drop of the diode should be low (schottky rectifier is preferred). The schottky diode is
selected based on the appropriate power rating, which factors in the dc conduction losses; this is determined by
Equation 27:
(27)
Where,
Vƒd = forward conducting voltage of Schottky diode
Input Capacitor CI
The TPS55332 requires an input ceramic de-coupling capacitor type X5R or X7R and bulk capacitance to
minimize input ripple voltage. The dc voltage rating of this input capacitance must be greater than the maximum
input voltage. The capacitor must have an input ripple current rating higher than the maximum input ripple current
of the converter for the application; this is determined by Equation 28.
The input capacitors for power regulators are chosen to have a reasonable capacitance to volume ratio and be
fairly stable over the temperature range.
(28)
Output Voltage and Feedback Resistor Selection
In the design example 10 kΩwas selected for R7, using Equation 1, R8 is calculated as 100.58 kΩ. The nearest
standard value is 100 kΩ. Higher resistor values help improve converter efficiency at low output currents but may
introduce noise immunity problems.
Reset Threshold Resistor Selection
Using Equation 6, select resistor R5 as 10 kΩthen calculate R6. This gives a resistor value of 263 kΩ; use a
standard value of 267 kΩ. This sets the reset threshold at 0.86 × 26V.
Soft Start Capacitor
The soft start capacitor determines the minimum time to reach the desired output voltage during a power up
cycle. This is useful when a load requires a controlled voltage slew rate and helps to limit the current draw from
the input voltage supply line. Equation 4 and Equation 5 have to be satisfied in addition to the other conditions
stated in the soft start section of this document. In this design a 47-nF capacitor is required to meet these
criteria.
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Product Folder Link(s) :TPS55332-Q1
Gain – dB
-20dB/dec
-40dB/dec
f – Frequency – Hz
f = 15.9Hz
P
f = 1.161kHz
LC
f = 2.466kHz
Cf = 7.339kHz
RHP
G011
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
Loop Compensation Calculation
To make sure the right hand plane zero does not impact converter design in CCM operation based on VIN = 6 V,
L = 100 mH, and Co = 10 mf, calculated values using Equation 16, the frequency is set at:
ƒRHP = 7.339 kHz
The double pole associated with the L and Co components is given by Equation 15:
ƒLC = 1.161 kHz
Using Equation 14:
ƒC= 2.466 kHz
The zero due to the ESR of the capacitor is beyond the right hand plane zero frequency and can be calculated
based on Equation 17 and Equation 23.
So to avoid any instability issues and from the frequency values calculated above the amplifier gain requires a
gain roll off much earlier than the double pole of the L and Co components.
So the pole must be set at a much lower frequency to obtain a reasonable phase margin.
Using Equation 18 and choosing a frequency close to 2.9 Hz for the pole frequency, the capacitor value C8 for
this application is:
C8 = 0.54 mF
If C8 = 1 mF standard value, then ƒP= 15.9 Hz.
Loop Compensation Response
Since the pole due to the integrating capacitor C4 is dominant in the compensation loop, the frequency of the
pole due to the inductor has no consequence in this situation.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s) :TPS55332-Q1
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
Output Inductor Selection (Lo) for DCM
The maximum inductor value is calculated using Equation 16 and gives a value of 15.4 mH, so 15 mH is the
selected standard value. This allows the converter to be in DCM mode over the full operating range.
To operate in this mode with the calculated inductor value, the right hand plane zero frequency has moved to
45.6 kHz and the cut off frequency is 15.2 kHz.
The double pole due to the L and Co values is 2.9 kHz.
To compensate with either type II or type III loop compensation, the Bode Plot stability criteria must be satisfied.
Power Dissipation
The power dissipation losses are applicable for continuous conduction mode operation (CCM).
PCON = Io2× RdsON × (1 – Vi/Vo) (conduction losses) (29)
PSW = ½ × Vo × Io/(1 – D) × (tr + tf) × ƒSW (switching losses) (30)
PGate = Vdrive × Qg × ƒsw (gate drive losses), where Qg = 1 × 10-9 (nC) (31)
PIC = Vi × Iq-normal (supply losses) (32)
PTotal = PCON + PSW + PGate + PIC (watts) (33)
Where:
Vo = Output voltage
Vi = Input voltage
Io = Output current
tr = FET switching rise time (tr max = 40 ns)
tf = FET switching fall time
Vdrive = FET gate drive voltage (typically Vdrive = 6 V and Vdrive max = 8 V)
ƒsw = Switching frequency
D = Duty cycle
For given operating ambient temperature, TAmb:
TJ= TAmb + Rth × PTotal (34)
For a given max junction temperature of TJ-Max = 150°C:
TAmb-Max = TJ-Max – Rth × PTotal (35)
Where:
PTotal = Total power dissipation (watts)
TAmb = Ambient temperature in °C
TJ= Junction temperature in °C
TAmb-Max = Maximum ambient temperature in °C
TJ-Max = Maximum junction temperature in °C
Rth = Thermal resistance of package in (°C/W)
Other factors NOT included in the information above which affect the overall efficiency and power losses are
inductor ac and dc losses, and trace resistance and losses associated with the copper trace routing connection.
Layout
The recommended guidelines for PCB layout of the TPS55332 device are described in the following sections.
Inductor
Use a low EMI inductor with a ferrite type shielded core. Other types of inductors may be used, however they
must have low EMI characteristics and be located away from the low power traces and components in the circuit.
Input Filter Capacitors
Input ceramic filter capacitors should be located in close proximity of the VIN terminal. Surface mount capacitors
are recommended to minimize lead length and reduce noise coupling. Also low ESR and max input ripple current
requirements must be satisfied.
20 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS55332-Q1
NC
NC
SYNC
GND
EN
RT
Rslew
RST
Cdly
SS
GND
RST_TH
VSENSE
COMP
VReg
PGND
SW
VIN
BOOT
Inductor
Topside Ground Area
Topside Supply Area
Thermal Via
Signal Via
Input Capacitor
Ground
Plane
Output
Capacitor
Compensation
Network Resistor
Divider
Signal via to
Ground Plane
Supervisor
Network
Place enough thermal
vias to enhance thermal
performance
GND
M0148-01
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
Feedback
Route the feedback trace such that there is minimum interaction with any noise sources associated with the
switching components. Recommended practice is to ensure the inductor is placed away from the feedback trace
to prevent EMI noise sourcing.
Traces and Ground Plane
All power (high current) traces should be as thick and short as possible. The inductor and output capacitors
should be as close to each other as possible. This reduces EMI radiated by the power traces due to high
switching currents.
In a two sided PCB it is recommended to have ground planes on both sides of the PCB to help reduce noise and
ground loop errors. The ground connection for the input and output capacitors and IC ground should be
connected to this ground plane.
In a multi-layer PCB, the ground plane is used to separate the power plane (high switching currents and
components are placed) from the signal plane (where the feedback trace and components are placed) for
improved performance.
Also arrange the components such that the switching current loops curl in the same direction. Place the high
current components such that during conduction the current path is in the same direction. This prevents magnetic
field reversal caused by the traces between the two half cycles, helping to reduce radiated EMI.
The power ground terminal for the power FET must also be terminated to the ground plane in the shortest trace
possible.
PCB Layout Example
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s) :TPS55332-Q1
TA − Ambient Temperature − °C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
−40 −20 0 20 40 60 80 100 120 140
PD − Power Dissipation − W
G012
TPS55332-Q1
SLVS939A –JUNE 2009–REVISED JUNE 2010
www.ti.com
Power Dissipation
NOTE: Power de-rating based on JEDEC JESD 51-5 standard board with thermal vias and high-k profile.
22 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS55332-Q1
TPS55332-Q1
www.ti.com
SLVS939A –JUNE 2009–REVISED JUNE 2010
REVISION HISTORY
Changes from Original (June 2009) to Revision A Page
• Changed title from 0.5-A, 60-V STEP UP DC/DC CONVERTER to 2.2-MHz, 60-V OUTPUT STEP UP DC/DC
CONVERTER ....................................................................................................................................................................... 1
• Added Peak Internal Switch Current: 5.7 A (typ) to Features .............................................................................................. 1
• Deleted Asynchronous Switch Mode Regulator with External Components (L and C), Output up to 0.5 A (max) in
Boost Mode from Features ................................................................................................................................................... 1
• Added fsw < fext < 2 × fsw to SYNC input clock test conditions .............................................................................................. 3
• Changed SYNC input clock max value from 1100 kHz to 2200 kHz .................................................................................... 3
• Added Vout = 25.5V to test conditions ................................................................................................................................. 6
• Added Vout = 25.5V to test conditions ................................................................................................................................. 6
• Changed Output Voltage (Vout) description ......................................................................................................................... 8
• Changed internal reference Vref from 2.5 V to 0.8 V ......................................................................................................... 11
• Added inductor saturation current Isat description ............................................................................................................... 13
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s) :TPS55332-Q1
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS55332QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2010
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS55332QPWPRQ1 HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS55332QPWPRQ1 HTSSOP PWP 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
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Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
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DSP dsp.ti.com Energy and Lighting www.ti.com/energy
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Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
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