A3922KLPTR-T - ALLEGRO MICROSYSTEMS

The A3922 is an N-channel power MOSFET driver capable of

controlling MOSFETs connected in a full-bridge (H-bridge)

arrangement and is specifically designed for automotive

applications with high-power inductive loads, such as brush

DC motors solenoids and actuators.

A unique charge pump regulator provides a programmable gate

drive voltage for battery voltages down to 7 V and allows the

A3922 to operate with a reduced gate drive, down to 5.5 V.

A bootstrap capacitor is used to provide the above-battery

supply voltage required for N-channel MOSFETs.

The full bridge can be controlled by independent logic level

inputs or through the SPI-compatible serial interface. The

external power MOSFETs are protected from shoot-through

by programmable dead time.

Integrated diagnostics provide indication of multiple internal

faults, system faults, and power bridge faults, and can be

configured to protect the power MOSFETs under most short-

circuit conditions. For safety-critical systems, the integrated

diagnostic operation can be verified under control of the serial

interface.

In addition to providing full access to the bridge control, the

serial interface is also used to alter programmable settings such

as dead time, VDS threshold, and fault blank time. Detailed

diagnostic information can be read through the serial interface.

The A3922 is supplied in a 28-pin eTSSOP (suffix ‘LP’). This

package is available in lead (Pb) free versions, with 100%

matte-tin leadframe plating (suffix –T).

A3922-DS, Rev. 2

MCO-0000646

• Full-bridge MOSFET driver

• Bootstrap gate drive for N-channel MOSFET bridge

• Cross-conduction protection with adjustable dead time

• Charge pump for low supply voltage operation

• Programmable gate drive voltage

• 5.5 to 50 V supply voltage operating range

• Integrated current sense amplifier

• SPI compatible serial interface

• Bridge control by direct logic inputs or serial interface

• TTL-compatible logic inputs

• Open-load detection

• Extensive programmable diagnostics

• Diagnostic verification

• Safety-assist features

Automotive Full-Bridge MOSFET Driver

PACKAGE:

Typical Application – Functional Block Diagram

Not to scale

A3922

ECU A3922

SPI

VBAT

GND

FEATURES AND BENEFITS DESCRIPTION

April 10, 2019

28-Pin eTSSOP (suffix LP)

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

SELECTION GUIDE

Part Number Packing Package

A3922KLPTR-T 4000 pieces per reel 9.7 mm × 4.4 mm, 1.2 mm nominal height

28-lead eTSSOP with exposed thermal pad

*Contact Allegro™ for additional packing options.

Table of Contents

Features and Benefits 1

Specifications 3

Absolute Maximum Ratings 3

Thermal Characteristics 3

Pinout Diagram and Terminal List Table 4

Functional Block Diagram 5

Electrical Characteristics Table 6

Overcurrent Fault Timing Diagrams 12

VDS Fault Timing Diagrams 13

Logic Truth Tables 14

Functional Description 15

Input and Output Terminal Functions 15

Power Supplies 16

Gate Drives 16

Logic Control Inputs 18

Output Disable 19

Sleep Mode 19

Current Sense Amplifier 20

Diagnostic Monitors 20

Status and Diagnostic Registers 20

Chip-Level Protection 20

Operational Monitors 21

Power Bridge and Load Faults 23

Fault Action 27

Fault Masks 28

Diagnostic and System Verification 28

On-Line Verification 29

Off-Line Verification 30

Serial Interface 33

Serial Registers Definition 33

Configuration Registers 34

Verification Registers 35

Diagnostic Registers 35

Control Register 35

Status Register 36

Serial Register Reference 37

Config 0, 1 37

Config 2, 3 38

Config 4, 5 39

Verify Command 0, 1 41

Verify Result 0, 1 42

Mask 0, 1 43

Diag 0, 1, 2 44

Control 45

Status 46

Applications Information 47

Power Bridge PWM Control 47

Current Sense Amplifier Configuration 48

Dead Time Selection 49

Bootstrap Capacitor Selection 49

Bootstrap Charging 49

VREG Capacitor Selection 50

Supply Decoupling 50

Braking 50

Input / Output Structures 51

Package Drawing 52

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

ABSOLUTE MAXIMUM RATINGS [1][2]

Characteristic Symbol Notes Rating Unit

Load Supply Voltage VBB –0.3 to 50 V

Pumped Regulator Terminal VREG VREG –0.3 to 16 V

Charge Pump Capacitor Low Terminal VCP1 CP1 –0.3 to 16 V

Charge Pump Capacitor High Terminal VCP2 CP2 VCP1 – 0.3 to VREG + 0.3 V

Battery Compliant Logic Input

Terminals VIB HA, HBn, LAn, LB, RESETn, ENABLE –0.3 to 50 V

Logic Input Terminals VISTRn, SCK, SDI –0.3 to 6 V

Logic Output Terminals VOSDO –0.3 to 6 V

Sense Amplifier Input VCSI CSP, CSM –4 to 6.5 V

Sense Amplifier Output VCSO CSO –0.3 to VDD + 0.3 V

Bridge Drain Monitor Terminals VBRG VBRG –5 to 55 V

Bootstrap Supply Terminals VCX CA, CB –0.3 to VREG + 50 V

High-Side Gate Drive Output

Terminals VGHX GHA, GHB VCX – 16 to VCX + 0.3 V

Motor Phase Terminals VSX SA, SB VCX – 16 to VCX + 0.3 V

Low-Side Gate Drive Output Terminals VGLX GLA, GLB VREG – 16 to 16 V

Bridge Low-Side Source Terminal VLSS LSS VREG – 16 to 18 V

Operating Ambient Temperature TALimited by power dissipation –40 to 150 °C

Maximum Junction Temperature TJ(max) 165 °C

Transient Junction Temperature TJt

Overtemperature event not exceeding 10 seconds,

lifetime duration not exceeding 10 hours,

guaranteed by design characterization.

180 °C

Storage Temperature Tstg –55 to 150 °C

1 With respect to GND. Ratings apply when no other circuit operating constraints are present.

2 Lowercase “x” in pin names and symbols indicates a variable sequence character.

SPECIFICATIONS

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see Power Derating section

Characteristic Symbol Test Conditions [3] Value Unit

Package Thermal Resistance

RθJA

4-layer PCB based on JEDEC standard 28 °C/W

2-layer PCB with 3.8 in2 copper each side 38 °C/W

RθJP 2 °C/W

3 Additional thermal information available on the Allegro website.

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Package LP, 28-Pin eTSSOP Pinout Diagram

10 19

11 18

12 17

13 16

14 15

PAD

CP2

VBB

VBRG

ENABLE

RESETn

LAn

HBn

GND

SDI

STRn

SDO

SCK

CP1

VREG

GHA

GHB

GLA

LSS

GLB

CSP

CSM

CSO

PINOUT DIAGRAM AND TERMINAL LIST TABLE

Terminal

Name

Terminal

Number

Terminal

Description

VBB 2 Main power supply

ENABLE 4 Output enable

VREG 27 Gate drive supply output

CP1 28 Pump capacitor

CP2 1 Pump capacitor

GND 10 Digital ground

RESETn 5 Standby mode control

SDI 11 Serial data input

SCK 14 Serial clock input

STRn 12 Serial strobe (chip select) input

SDO 13 Serial data output

CSP 17 Current sense amp + input

CSM 16 Current sense amp – input

CSO 15 Current sense amp output

HA 6 Phase A HS control

Terminal

Name

Terminal

Number

Terminal

Description

HBn 8 Phase B HS control

LAn 7 Phase A LS control

LB 9 Phase B LS control

VBRG 3 High-side drain voltage sense

CA 26 Phase A bootstrap capacitor

GHA 25 Phase A high-side gate drive

SA 24 Phase A motor connection

GLA 20 Phase A low-side gate drive

CB 23 Phase B bootstrap capacitor

GHB 22 Phase B high-side gate drive

SB 21 Phase B motor connection

GLB 18 Phase B low-side gate drive

LSS 19 Low-side source

PAD – Thermal pad; connect to GND

Terminal List Table

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

CP1 CP2

VBAT

VBB

VREG

CREG

CBOOTA

CBOOTB

RGHA RGHB

RGLA RGLB

Logic Supply

Regulator

Charge

Pump

Regulator

Charge

Pump

Drive

Bootstrap

Monitor VDS

Monitor

VDS

Monitor

Drive

Sense

Amp

Control

Logic

ENABLE

LAn

HBn

RESETn

STRn

SCK

SDI

SDO

Timers

Diagnostics &

Protection

Diagnostic

Veriﬁcation

GND

CSO

CSM

CSP

GLB

GHB

LSS

GLA

GHA

VBRG

Phase A

As above for

Phase B

VDL

VREG

DAC

VOOS

DAC

*V = V& V

DACOLTON OCT

Serial

Interface

Functional Block Diagram

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

SUPPLY AND REFERENCE

VBB Functional Operating Range VBB

Operating; outputs active 6 – 50 V

Operating; outputs disabled 5.5 – 50 V

No unsafe states 0 – 50 V

VBB Quiescent Current IBBQ

RESETn = high, VBB = 12 V, all gate drive

outputs low – 10 24 mA

IBBS RESETn ≤ 300 mV, sleep mode – – 30 µA

Internal Logic Supply Regulator Voltage VDL 3.1 3.3 3.5 V

VREG Output Voltage, VRG = 0 VREG

VBB ≥ 9 V, IVREG = 0 to 27 mA 7.5 8 8.5 V

7.5 V ≤ VBB < 9 V, IVREG = 0 to 20 mA 7.5 8 8.5 V

6 V ≤ VBB < 7.5 V, IVREG = 0 to 15 mA 7.5 8 8.5 V

5.5 V ≤ VBB < 6 V, IVREG ≤ 10 mA 7.5 8 8.5 V

VREG Output Voltage, VRG = 1 VREG

VBB ≥ 9 V, IVREG = 0 to 27 mA 9 13 13.8 V

7.5 V ≤ VBB < 9 V, IVREG = 0 to 20 mA 9 13 13.8 V

6 V ≤ VBB < 7.5 V, IVREG = 0 to 10 mA 7.9 – – V

5.5 V ≤ VBB < 6 V, IVREG ≤ 6 mA 7.9 9.5 – V

Bootstrap Diode Forward Voltage VfBOOT

ID = 10 mA 0.4 0.7 1 V

ID = 100 mA 1.5 2.2 2.8 V

Bootstrap Diode Resistance rD

rD(100 mA) = (VfBOOT(150 mA) – VfBOOT(50 mA)) /

100 mA 611 25 Ω

Bootstrap Diode Current Limit IDBOOT 250 500 750 mA

Top-Off Charge Pump Current Limit ITOCPM – 100 – µA

High-Side Gate Drive Static Load

Resistance RGSH 250 – – kΩ

System Clock Period tOSC 42.5 50 57.5 ns

Continued on the next page…

ELECTRICAL CHARACTERISTICS: Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise specied

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

GATE OUTPUT DRIVE

Turn-On Time trCLOAD = 10 nF, 20% to 80% – 190 – ns

Turn-Off Time tfCLOAD = 10 nF, 80% to 20% – 120 – ns

Pull-Up On-Resistance RDS(on)UP

TJ = 25°C, IGH = –150 mA [1] 5 8 11 Ω

TJ = 150°C, IGH= –150 mA [1] 10 15 20 Ω

Pull-Down On-Resistance RDS(on)DN

TJ = 25°C, IGL= 150 mA 1.5 2.4 4 Ω

TJ = 150°C, IGL= 150 mA 2.9 4 6 Ω

GHx Output Voltage High VGHH Bootstrap capacitor fully charged VCX – 0.2 – – V

GHx Output Voltage Low VGHL –10 µA1 < IGH < 10 µA – – VSX + 0.3 V

GLx Output Voltage High VGLH VREG – 0.2 – – V

GLx Output Voltage Low VGLL –10 µA1 < IGL < 10 µA – – VLSS + 0.3 V

Gate-Source Voltage – MOSFET On VGSon No faults present VROFF – VREG V

GHx Passive Pull-Down RGHPD VGHx – VSx < 0.3 V – 950 – kΩ

GLx Passive Pull-Down RGLPD VGLx – VLSS < 0.3 V – 950 – kΩ

Turn-Off Propagation Delay tP(off)

Input change to unloaded gate output change

(Figure 3), DT[5:0] = 0 60 90 140 ns

Turn-On Propagation Delay tP(on)

Input Change to unloaded Gate output change

(Figure 3), DT[5:0] = 0 50 80 130 ns

Propagation Delay Matching

(Phase-to-Phase) ΔtPP Same state change, DT[5:0] = 0 – 5 15 ns

Propagation Delay Matching

(On-to-Off) ΔtOO Single phase, DT[5:0] = 0 – 15 30 ns

Propagation Delay Matching

(GHx-to-GLx) ΔtHL Same state change, DT[5:0] = 0 – – 20 ns

Dead Time (Turn-Off to Turn-On Delay) tDEAD Default power-up state (Figure 3) 1.25 1.6 2.15 µs

ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise specied

Continued on the next page…

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

LOGIC INPUTS AND OUTPUTS

Input Low Voltage VIL All logic inputs – – 0.8 V

Input High Voltage VIH All logic inputs 2 – – V

Input Hysteresis VIhys All logic inputs 250 550 – mV

Input Pull-Down

HA, LB, SDI, SCK, ENABLE

RPD 0 V < VIN < 5 V – 50 – kΩ

IPD 5 V < VIN < 50 V, HA, LB, ENABLE – 100 – µA

Input Pull-Down RESETn RPDR 0 V < VIN < 5 V – 50 – kΩ

IPDR 5 V < VIN < 50 V – 100 – µA

Input Pull-Up Current to VDL RPU HBn, LAn, STRn, Input = 0 V – 100 – µA

Output Low Voltage VOL IOL = 1 mA – 0.2 0.4 V

Output High Voltage VOH IOL = –1 mA [1] 2.4 – – V

Output Leakage [1] IOSDO, 0 V < VSDO < 3 V, STRn = 1 –1 – 1 µA

LOGIC I/O – DYNAMIC PARAMETERS

Reset Pulse Width tRST 0.5 – 4.5 µs

Clock High Time tSCKH A in Figure 2 50 – – ns

Clock Low Time tSCKL B in Figure 2 50 – – ns

Strobe Lead Time tSTLD C in Figure 2 30 – – ns

Strobe Lag Time tSTLG D in Figure 2 30 – – ns

Strobe High Time tSTRH E in Figure 2 300 – – ns

Data Out Enable Time tSDOE F in Figure 2 – – 40 ns

Data Out Disable Time tSDOD G in Figure 2 – – 30 ns

Data Out Valid Time from Clock Falling tSDOV H in Figure 2 – – 40 ns

Data Out Hold Time from Clock Falling tSDOH I in Figure 2 5 – – ns

Data In Setup Time to Clock Rising tSDIS J in Figure 2 15 – – ns

Data in Hold Time from Clock Rising tSDIH K in Figure 2 10 – – ns

Wake Up from Sleep tEN CREG = 2.2 µF – – 2 ms

ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise specied

Continued on the next page…

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise specied

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

CURRENT SENSE AMPLIFIERS

Input Offset Voltage [3] VIOS –4 ±1 +4 mV

Input Offset Voltage Drift ΔVIOS – ±4 – µV/°C

Input Bias Current [1] IBIAS 0 V < VCSP < VDL, 0 V < VCSM < VDL –160 – –60 µA

Input Offset Current [1] IOS VID = 0 V, VCM in range –20 – +20 µA

Input Common-Mode Range (DC) VCM VID = 0 V –1 – 2 V

Gain AVDefault power-up value – 35 – V/V

Gain Error EAVCM in range –5 ±2 5 %

Output Offset VOOS Default power-up value – 2.5 – V

Output Offset Error [3] EVO

VCM in range, Gain = 10 V/V, VOOS > 1 V –5 – 5 %

VCM in range, Gain = 10 V/V, VOOS ≤ 1 V –75 – 75 mV

Small Signal –3 dB Bandwidth at

Gain = 25 BWVIN = 10 mVpp 500 – – kHz

Output Settling Time (to within 40 mV) tSET

VCSO = 1 Vpp square wave Gain = 25 V/V,

COUT = 200 pF – 1 1.8 µs

Output Dynamic Range VCSOUT –100 µA [1] < ICSO < 100 µA 0.3 – 4.8 V

Output Voltage Clamp VCSC ICSO = –2 mA 4.9 5.1 5.5 V

Output Current Sink [1] ICSsink VID = 0 V, VCSO = 1.5 V, Gain = 25 V/V 200 – – µA

Output Current Sink (Boosted) [1][4] ICSsinkb

VOOS = 1.5 V, VID = –50 mV, Gain = 25 V/V,

VCSO = 1.5 V 1 – – mA

Output Current Source [1] ICSsource

VID = 200 mV, VCSO = 1.5 V, Gain = 25 V/V,

Offset = 0 V – – –1 mA

DC Common-Mode Rejection Ratio CMRR VCM step from 0 to 200 mV, Gain = 25 V/V 60 – – dB

AC Common-Mode Rejection Ratio CMRR

VCM = 200 mVpp, 100 kHz, Gain = 25 V/V – 62 – dB

VCM = 200 mVpp, 1 MHz, Gain = 25 V/V – 43 – dB

Common-Mode Recovery Time

(to within 100 mV) tCMrec

VCM step from –4 V to +1 V, Gain = 25 V/V,

COUT = 200 pF – 1 – µs

Output Slew Rate 10% to 90% SR VID step from 0 V to 175 mV, Gain = 25 V/V,

COUT = 200 pF – 10 – V/µs

Input Overload Recovery

(to within 40 mV) tIDrec

VID step from 250 mV to 0 V, Gain = 25 V/V,

COUT = 200 pF – 1 – µs

Continued on the next page…

CSP

CSM

CSP

V= (V + V )/2

CM CSP CSM

CSO

OOS

AGND

CSO

V= [(V –V ) ×A] + V

CSO CSP CSM VOOS

OOS

set by

SAO[3:0] in

Conﬁg 5

A set by

SAG[2:0] in

Conﬁg 5

A3922

Figure 1: Sense Amp Voltage Denitions

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise specied

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

DIAGNOSTICS AND PROTECTION

VREG Undervoltage, VRG = 0 VRON VREG rising 6.3 6.5 6.8 V

VROFF VREG falling 5.2 5.4 5.6 V

VREG Undervoltage, VRG = 1 VRON VREG rising 7.5 7.95 8.2 V

VROFF VREG falling 6.7 7 7.2 V

VREG Overvoltage Warning VROV VREG rising 14.3 14.9 15.4 V

VREG Overvoltage Hysteresis VROVHys 500 700 – mV

VBB Overvoltage Warning VBBOV VBB rising 32 – 36 V

VBB Overvoltage Hysteresis VBBOVHys 1 – – V

VBB Undervoltage VBBUV VBB falling – 4.0 – V

VBB Undervoltage Hysteresis VBBUVHys – 500 – mV

VBB POR Voltage VBBR VBB – 3.5 – V

Bootstrap Undervoltage VBCUV VBOOT rising, VBOOT = VCx – VSx 70 – 79 %VREG

Bootstrap Undervoltage Hysteresis VBCUVHys – 14 – %VREG

Gate Drive Undervoltage Warning HS VGSHUV VGSH VBOOT – 1.2 VBOOT – 1 VBOOT – 0.8 V

Gate Drive Undervoltage Warning LS VGSLUV VGSL VREG – 1.2 VREG – 1 VREG – 0.8 V

Logic Terminal Overvoltage Warning VLOV

VL rising on HA, HBn, LAn, LB, RESETn,

ENABLE 6.5 – 9 V

ENABLE Input Timeout tETO 90 100 110 ms

VBRG Input Voltage VBRG When VDS monitor is active 5.5 VBB 50 V

VBRG Input Current IVBRG VDSTH = default, VBB = 12V, 0V < VBRG < VBB – – 500 µA

IVBRGQ Sleep mode, VBB < 35 V – – 5 µA

VBRG Disconnect Threshold VBRO VBB – VBRG; default value, VBB ≥ 6 V 1.5 2 2.5 V

VBRG Disconnect Hysteresis VBROHys – 250 – mV

High-Side VDS Threshold VDSTH

Default power-up value – 1.2 – V

VBRG ≥ 7 V – – 3.15 V

5.5 V ≤ VBRG < 7 V – – 1.5 V

High-Side VDS Threshold Offset [2] VDSTHO High-side on, 200 mV ≤ VDSTH ≤ 3.15 V –200 ±100 +200 mV

Low-Side VDS Threshold VDSTL

Default power-up value – 1.2 – V

VBB ≥ 5.5 V – – 3.15 V

Low-Side VDS Threshold Offset [2] VDSTLO Low-side on, 200 mV ≤ VDSTL ≤ 3.15 V –200 ±100 +200 mV

VDS Quality Time tVDQ Default power-up value 1.25 1.6 2.15 µs

Phase Comparator Threshold VPT Phase voltage, default power-up value – 50 – %VBRG

Continued on the next page…

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

DIAGNOSTICS AND PROTECTION (continued)

Overcurrent Voltage VOCT Default power-up value 2.7 3 3.3 V

Overcurrent Qualify Time tOCQ Default power-up value 6.75 7.5 8.25 µs

On-State Open-Load Threshold

Voltage VOLTON Default power-up value 200 225 250 mV

Off-State Open-Load Threshold Voltage VOLTOFF 0.6 1 1.4 V

Off-State Sink Current on SB IOLTS 6 10 14 mA

Off-State Source Current on SA IOLTT OLI = 0 – 100 – µA

Off-State Source Current on SA IOLTT OLI = 1 – 400 – µA

Open-Load Timeout tOLTO 90 100 110 ms

Temperature Warning Threshold TJWH Temperature increasing 125 135 145 °C

Temperature Warning Hysteresis TJWHhys – 15 – °C

Overtemperature Threshold TJF Temperature increasing 170 175 180 °C

Overtemperature Hysteresis TJHyst Recovery = TJF – TJHyst – 15 – °C

DIAGNOSTIC VERIFICATION

LSS Open Threshold VLSO 4.5 5 5.5 V

LSS Open Threshold Hysteresis VLSOHys – 500 – mV

LSS Verification Current ILU – –100 – µA

Phase Test Pull-Down Current [1] ISD – 200 – µA

Phase Test Pull-Up Current [1] ISU – -200 – µA

Sense Amplifier Input Open Threshold

(CSP, CSM) VSAD – 2.2 – V

Sense Amplifier Input Verification

Current [1] ISAD – –20 – µA

1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal.

2 VDS offset is the difference between the programmed threshold, VDSTH or VDSTL, and the actual trip voltage.

3 Ensured by design and characterization.

4 If the amplifier output voltage (VCSO) is more positive than the value demanded by the applied differential input (VID) and output offset (VOOS)

conditions, output current sink capability is boosted to enhance negative-going transient response.

ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise specied

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

STRn

SCK

SDI

SDO

CAB

XD15 XD14 X

D15’ D14’ D0’

Figure 2: Serial Interface Timing

X = don’t care; Z = high-impedance (tri-state)

LAN

GHA

GLA

tP(off)

tP(on)

tDEAD

tP(off) tP(off)

tP(off)

Synchronous Rectiﬁcation High-side PWM Low-side PWM

Figure 3a: Gate Drive Timing – Phase A Logic Control Inputs

HBN

GHB

GLB

tP(off)

tP(on)

tDEAD

tP(off) tP(off)

tP(off)

Synchronous Rectiﬁcation High-side PWM Low-side PWM

Figure 3b: Gate Drive Timing – Phase B Logic Control Inputs

OVERCURRENT FAULT TIMING DIAGRAMS

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

GHA

GLA

GHB

GLB

OC Monitor Blank Blank Blank Blank Blank

Active Active Active Active Active

tOCQ tOCQ tOCQ tOCQ tOCQ

Figure 4: Overcurrent Fault Monitor – Blank Mode Timing (OCQ = 1)

MOSFET turn on

No fault present

MOSFET turn on

Fault present

MOSFET on

Transient disturbance

No fault present

MOSFET on

Fault occurs

Gxx

VDS

Fault Bit

tVDQ tVDQ

Figure 5a: VDS Fault Monitor – Blank Mode Timing (VDQ = 1)

MOSFET turn on

No fault present

MOSFET turn on

Fault present

MOSFET on

Transient disturbance

No fault present

MOSFET on

Fault occurs

Gxx

VDS

Fault Bit

tVDQ tVDQ tVDQ tVDQ

Figure 5b: VDS Fault Monitor – Debounce Mode Timing (VDQ = 0)

VDS FAULT TIMING DIAGRAMS

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Table 1: Control Logic Table – Control by Logic Inputs

Phase A Phase B

HA LAn GHA GLA SA HBn LB GHB GLB SB

0 1 LO LO Z 1 0 LO LO Z

0 0 LO HI LO 1 1 LO HI LO

1 1 HI LO HI 0 0 HI LO HI

1 0 LO LO Z 0 1 LO LO Z

HI ≡ high-side FET active, LO ≡ low-side FET active.

Z ≡ high-impedance, both FETs o󰀨.

All control register bits set to 0, RESETn = 1, ENABLE = 1.

Table 2: Control Logic Table – Control by Serial Register

Phase A Phase B

AH AL GHA GLA SA BH BL GHB GLB SB

0 0 LO LO Z 0 0 LO LO Z

0 1 LO HI LO 0 1 LO HI LO

1 0 HI LO HI 1 0 HI LO HI

1 1 LO LO Z 1 1 LO LO Z

HI ≡ high-side FET active, LO ≡ low-side FET active.

Z ≡ high-impedance, both FETs o󰀨.

Logic 0 input on HA,LB. Logic 1 input on LAn, HBn, RESETn = 1, ENABLE = 1.

Table 3: Control Combination Logic Table – Control by Logic Inputs and Serial Register

Phase A Phase B

HA AH LAn AL GHA GLA SA HBn BH LB BL GHB GLB SB

0 0 1 0 LO LO Z 1 0 0 0 LO LO Z

0 0 X 1 LO HI LO 1 0 X 1 LO HI LO

0 0 0 X 1 0 1 X

X 1 1 0 HI LO HI X 1 0 0 HI LO HI

1 X 1 0 0 X 0 0

X 1 X 1

LO LO Z

X1X1

LO LO Z

X 1 0 X X 1 1 X

1 X X 1 0 X X 1

1 X 0 X 0 X 1 X

X ≡ don’t care, HI ≡ high-side FET active, LO ≡ low-side FET active, Z ≡ high-impedance, both FETs o󰀨.

RESETn = 1; ENBLE = 1.

LOGIC TRUTH TABLES

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

FUNCTIONAL DESCRIPTION

The A3922 is full-bridge (H-Bridge) MOSFET driver (pre-driver)

requiring a single unregulated supply of 6 to 50 V. It includes an

integrated linear regulator to supply the internal logic. All logic

inputs are TTL compatible and can be driven by 3.3 or 5 V logic.

The four high-current gate drives are capable of driving a wide

range of N-channel power MOSFETs, and are configured as a

full-bridge driver with two high-side drives and two low-side

drives. The A3922 provides all necessary circuits to ensure that

all external power MOSFETs are fully enhanced at supply volt-

ages down to 7 V. For extreme battery voltage drop conditions,

correct functional operation is guaranteed at supply voltages

down to 5.5 V, but with a reduced gate drive voltage.

Gate drives can be controlled directly through the logic input

terminals or through an SPI-compatible serial interface. The

sense of the logic inputs are arranged to allow each bridge to be

driven by a single PWM input if required. Each bridge can also

be driven by direct logic inputs or by two or four PWM signals,

depending on the required complexity. The logic inputs are bat-

tery voltage compliant, meaning they can be shorted to ground or

supply without damage up to the maximum battery voltage of

50 V.

Bridge efficiency can be enhanced by using the synchronous

rectification ability of the drives. When synchronous rectification

is used, cross-conduction (shoot-through) in the external bridge

is avoided by an adjustable dead time. A hard-wired logic lockout

ensures that high-side and low-side on any single phase cannot be

permanently active at the same time.

A low-power sleep mode allows the A3922, the power bridge,

and the load to remain connected to a vehicle battery supply

without the need for an additional supply switch.

The A3922 includes a number of diagnostic features to provide

indication of and/or protection against undervoltage, overvoltage,

overtemperature, and power bridge faults. Detailed diagnostic

information is available through the serial interface.

For systems requiring a higher level of safety integrity, the A3922

includes additional overvoltage monitors on the supplies and

the control inputs. In addition, the integrated diagnostics include

self-test and verification circuits to ensure verifiable diagnostic

operation. When used in conjunction with appropriate system

level control, these features can assist power drive systems using

the A3922 to meet stringent ASIL D safety requirements.

The serial interface also provides access to programmable dead

time, fault blanking time, programmable VDS threshold for short

detection, and programmable thresholds and currents for open-

load detection.

The A3922 includes a low-side current sense amplifier with

programmable gain and offset. The amplifier is specifically

designed for current sensing in the presence of high voltage

and current transients. The A3922 can also check the connec-

tions from the current sense amplifier to the sensing link using

integrated verification circuits.

Input and Output Terminal Functions

• VBB: Main power supply for internal regulators and charge

pump. The main power supply should be connected to VBB

through a reverse voltage protection circuit and should be

decoupled with ceramic capacitors connected close to the

supply and ground terminals.

• VBRG: Sense input to the top of the external MOSFET

bridge. Allows accurate measurement of the voltage at the

drain of the high-side MOSFETs in the bridge.

• CP1, CP2: Pump capacitor connection for charge pump.

Connect a minimum 220 nF, typically 470 nF, ceramic

capacitor between CP1 and CP2.

• VREG: programmable regulated voltage, 8 or 13 V, used to

supply the low-side gate drivers and to charge the bootstrap

capacitors. A sufficiently large storage capacitor must be

connected to this terminal to provide the transient charging

current.

• GND: Analog reference, digital, and power ground. Connect

to supply ground—see layout recommendations.

• CA, CB: High-side connections for the bootstrap capacitors

and positive supply for high-side gate drivers.

• GHA, GHB: High-side, gate-drive outputs for external

n-channel MOSFETs.

• SA, SB: Load phase connections. These terminals sense the

voltages switched across the load. They are also connected

to the negative side of the bootstrap capacitors and are the

negative supply connections for the floating high-side drivers.

• GLA, GLB: Low-side, gate-drive outputs for external

n-channel MOSFETs.

• LSS: Low-side return path for discharge of the capacitance on

the MOSFET gates, connected to the common sources of the

low-side external MOSFETs independently through a low-

impedance track.

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

• HA: Logic inputs with pull-down to control the high-side gate

drive on phase A. Battery voltage compliant terminal.

• HBn: Logic inputs with pull-up to control the high-side gate

drive on phase B. These are active-low inputs. Battery voltage

compliant terminal.

• LAn: Logic inputs with pull-up to control the low-side gate

drive on phase A. These are active-low inputs. Battery voltage

compliant terminal.

• LB: Logic inputs with pull-down to control the low-side gate

drive on phase B. Battery voltage compliant terminal.

• SDI: Serial data logic input with pull-down. 16-bit serial word

input MSB-first.

• SDO: Serial data output. High-impedance when STRn is high.

Outputs bit 15 of the Status register, the fault flag, as soon as

STRn goes low.

• SCK: Serial clock logic input with pull-down. Data is latched

in from SDI on the rising edge of SCK. There must be 16

rising edges per write and SCK must be held high when STRn

changes.

• STRn: Serial data strobe and serial access enable logic input

with pull-up. When STRn is high, any activity on SCK or SDI

is ignored and SDO is high-impedance, allowing multiple SDI

slaves to have common SDI, SCK, and SDO connections.

• CSP, CSM: Current sense amplifier inputs.

• CSO: Current sense amplifier outputs.

• RESETn: Resets faults when pulsed low. Forces low-power

shutdown (sleep) when held low. Can be pulled to VBB.

• ENABLE: Deactivates all gate drive outputs when pulled low

in direct mode or after a timeout in monitor mode. Provides

an independent output deactivation, directly to the gate drive

outputs, to allow a fast disconnect on the power bridge. Can be

pulled to VBB.

Power Supplies

A single power supply voltage is required. The main power sup-

ply (VBB) should be connected to VBB through a reverse voltage

protection circuit. A 100 nF ceramic decoupling capacitor must

be connected close to the supply and ground terminals.

An internal regulator provides the supply to the internal logic.

All logic is guaranteed to operate correctly to below the regulator

undervoltage levels, ensuring that the A3922 will continue to

operate safely until all logic is reset when a power-on-reset state

is present.

The A3922 will operate within specified parameters with VBB

from 5.5 to 50 V and will operate safely between 0 and 50 V

under all supply switching conditions. This provides a very rug-

ged solution for use in the harsh automotive environment.

PUMP REGULATOR

The gate drivers are powered by a programmable voltage internal

regulator which limits the supply to the drivers and therefore

the maximum gate voltage. At low supply voltage, the regulated

supply is maintained by a charge pump boost converter which

requires a pump capacitor, typically 470 nF, connected between

the CP1 and CP2 terminals.

The regulated voltage, VREG, can be programmed to 8 or 13 V

and is available on the VREG terminal. The voltage level is

selected by the value of the VRG bit: when VRG = 1, the voltage

is set to 13 V; when VRG = 0, the voltage is set to 8 V. A suf-

ficiently large storage capacitor (see Applications section) must

be connected to this terminal to provide the transient charging

current to the low-side drivers and the bootstrap capacitors.

Gate Drives

The A3922 is designed to drive external, low on-resistance,

power n-channel MOSFETs. It will supply the large transient

currents necessary to quickly charge and discharge the external

MOSFET gate capacitance in order to reduce dissipation in the

external MOSFET during switching. The charge current for

the low-side drives and the recharge current for the bootstrap

capacitors are provided by the capacitor on the VREG terminal.

The charge current for the high-side drives is provided by the

bootstrap capacitors connected between the Cx and Sx terminal,

one for each phase. The charge and discharge rate of the gate of

the MOSFET can be controlled using an external resistor in series

with the connection to the gate of the MOSFET.

BOOTSTRAP SUPPLY

When the high-side drivers are active, the reference voltage for

the driver will rise to close to the bridge supply voltage. The

supply to the driver will then have to be above the bridge supply

voltage to ensure that the driver remains active. This temporary

high-side supply is provided by bootstrap capacitors, one for each

high-side driver. These two bootstrap capacitors are connected

between the bootstrap supply terminals (CA and CB) and the

corresponding high-side reference terminal (SA and SB).

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

The bootstrap capacitors are independently charged to approxi-

mately VREG when the associated reference Sx terminal is low.

When the output swings high, the voltage on the bootstrap supply

terminal rises with the output to provide the boosted gate voltage

needed for the high-side n-channel power MOSFETs.

BOOTSTRAP CHARGE MANAGEMENT

The A3922 monitors the individual bootstrap capacitor charge

voltages to ensure sufficient high-side drive. It also includes an

optional bootstrap capacitor charge management system (boot-

strap manager) to ensure that the bootstrap capacitor remains suf-

ficiently charged under all conditions. The bootstrap manager is

enabled by default, but it may be disabled by setting the DBM bit

to 1. This may be required in systems where the output MOSFET

switching must only be allowed by the controlling processor.

Before a high-side drive can be turned on, the bootstrap capacitor

voltage must be higher than the turn-on voltage threshold (VBCUV

+ VBCUVHys). If this is not the case, then the A3922 will attempt

to charge the bootstrap capacitor by activating the complementary

low-side drive. Under normal circumstances, this will charge the

capacitor above the turn-on voltage in a few microseconds, and

the high-side drive will then be enabled. The bootstrap voltage

monitor remains active while the high-side drive is active;

furthermore, if the voltage drops below the turn-off voltage

threshold (VBCUV), a charge cycle is also initiated.

The bootstrap charge management circuit may actively charge the

bootstrap capacitor regularly when the PWM duty cycle is very

high, particularly when the PWM off-time is too short to permit

the bootstrap capacitor to become sufficiently charged.

In some safety systems, the gate driver is not permitted to turn

on a MOSFET without a direct command from the controller.

In this case, the bootstrap manager may be disabled by setting

the DBM bit to 1. If the bootstrap manager is disabled, then the

user must ensure that the bootstrap capacitor does not become

discharged below the bootstrap undervoltage threshold (VBCUV),

or a bootstrap fault will be indicated and the outputs disabled.

This can happen with very high PWM duty cycles when the

charge time for the bootstrap capacitor is insufficient to ensure

a sufficient recharge to match the MOSFET gate charge transfer

during turn on.

If, for any reason, the bootstrap capacitor cannot be sufficiently

charged, a bootstrap fault will occur—see Diagnostics section for

further details.

TOP-OFF CHARGE PUMP

An additional “top-off” charge pump is provided for each phase,

which will allow the high-side drive to maintain the gate voltage

on the external MOSFET indefinitely, ensuring so-called 100%

PWM if required. This is a low current trickle charge pump and is

only operated after a high side has been signaled to turn on. There

is a small amount of bias current drawn from the Cx terminal to

operate the floating high-side circuit (<40 µA), and the charge

pump simply provides enough drive to ensure the bootstrap

voltage—and hence the gate voltage—will not droop due to this

bias current.

In some applications, a safety resistor is added between the gate

and source of each MOSFET in the bridge. When a high-side

MOSFET is held in the on state, the current through the associ-

ated high-side gate-source resistor (RGSH) is provided by the

high-side driver and therefore appears as a static resistive load on

the top-off charge pump. The minimum value of RGSH for which

the top-off charge pump can provide current, without dropping

below the bootstrap undervoltage threshold, is defined in the

Electrical Characteristics table.

In all cases, the charge required for initial turn-on of the high-side

gate is always supplied by the bootstrap capacitor. If the bootstrap

capacitor becomes discharged, the top-off charge pump alone will

not provide sufficient current to allow the MOSFET to turn on.

HIGH-SIDE GATE DRIVE

High-side gate-drive outputs for external n-channel MOSFETs

are provided on pins GHA and GHB. External resistors between

the gate drive output and the gate connection to the MOSFET

(as close as possible to the MOSFET) can be used to control the

slew rate seen at the gate, thereby controlling the di/dt and dv/dt

of the voltage at the SA and SB terminals. GHx = 1 (or “high”)

means that the upper half of the driver is turned on, and its drain

will source current to the gate of the high-side MOSFET in the

external motor-driving bridge, turning it on. GHx = 0 (or “low”)

means that the lower half of the driver is turned on, and its drain

will sink current from the external MOSFET’s gate circuit to the

respective Sx terminal, turning it off.

The reference points for the high-side drives are the load phase

connections (SA and SB). These terminals sense the voltages at

the load connections. These terminals are also connected to the

negative side of the bootstrap capacitors and are the negative

supply reference connections for the floating high-side driv-

ers. The discharge current from the high-side MOSFET gate

capacitance flows through these connections, which should have

low-impedance traces to the MOSFET bridge.

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LOW-SIDE GATE DRIVE

The low-side, gate drive outputs on GLA and GLB are referenced

to the LSS terminal. These outputs are designed to drive external

n-channel power MOSFETs. External resistors between the gate

drive output and the gate connection to the MOSFET (as close

as possible to the MOSFET) can be used to control the slew rate

seen at the gate, thereby providing some control of the di/dt and

dv/dt of the voltage at the SA and SB terminals. GLx = 1 (or

“high”) means that the upper half of the driver is turned on, and

its drain will source current to the gate of the low-side MOSFET

in the external power bridge, turning it on. GLx = 0 (or “low”)

means that the lower half of the driver is turned on, and its drain

will sink current from the external MOSFET’s gate circuit to the

LSS terminal, turning it off.

The LSS terminal provides the return path for discharge of the

capacitance on the low-side MOSFET gates. This terminal is

connected independently to the common sources of the low-side

external MOSFETs through a low-impedance track.

GATE DRIVE PASSIVE PULL-DOWN.

Each gate drive output includes a discharge circuit to ensure that

any external MOSFET connected to the gate drive output is held

off when the power is removed. This discharge circuit appears

as 400 kΩ between the gate drive and the source connections

for each MOSFET. It is only active when the A3922 is not

driving the output to ensure that any charge accumulated on the

MOSFET gate has a discharge path even when the power is not

connected.

DEAD TIME

To prevent cross-conduction (shoot-through) in any phase of the

power MOSFET bridge, it is necessary to have a dead-time delay

between a high- or low-side turn-off and the next complementary

turn-on event. The potential for cross-conduction occurs when

any complementary high-side and low-side pair of MOSFETs

are switched at the same time (for example, at the PWM switch

point). In the A3922, the dead time for both phases is set by

the contents of the DT[5:0] bits in Config 0 register. These six

bits contain a positive integer that determines the dead time by

division from the system clock.

The dead time is defined as:

tDEAD = n × 50 ns

where n is a positive integer defined by DT[5:0] and tDEAD has a

minimum active value of 100 ns.

For example, when DT[6:0] contains [11 0000] (= 48 in decimal),

then tDEAD = 2.4 µs, typically.

The accuracy of tDEAD is determined by the accuracy of the

system clock as defined in the Electrical Characteristics table.

The range of tDEAD is 100 ns to 3.15 µs. A value of 1 or 2 in

DT[5:0] will set the minimum active dead time of 100 ns.

If the dead time is to be generated externally (for example, by

the PWM output of a microcontroller), then entering a value of

zero in DT[5:0] will disable the dead timer, and there will be no

minimum dead time generated by the A3922. However, the logic

that prevents permanent cross-conduction will still be active.

The internally generated dead time will only be present if the on

command for one MOSFET occurs within one dead time after the

off command for its complementary partner. In the case where

one side of a phase drive is permanently off (for example, when

using diode rectification with slow decay), then the dead time

will not occur. In this case, the gate drive will turn on within the

specified propagation delay after the corresponding phase input

goes high (see Figure 3).

Logic Control Inputs

Four logic level digital inputs provide direct control for the gate

drives, one for each drive. These TTL threshold logic inputs can

be driven from 3.3 or 5 V logic, and all have a typical hysteresis

of 500 mV to improve noise performance. Each input can be

shorted to the VBB supply, up to the absolute maximum supply

voltage, without damage to the input.

Input HA is active-high and controls the high-side drive for

phase A. LAn is active-low and controls the low-side drive

for phase A. Similarly, HBn (active-low) and LB (active-high)

control the high-side and low-side drives respectively for phase

B. The logical relationship between the inputs and the gate drive

outputs is defined in Table 1.

The logic sense of the inputs (active-high or active-low) are

arranged to permit the bridge to be controlled with 1, 2, or 4

inputs. The control inputs to each phase can be driven together

to control both high-side and low-side drives when synchronous

rectification is used. Driving each phase with a single input in

this way provides direction control with one input, and slow

decay synchronous rectification PWM with the other input.

Driving all four control inputs together provides fast decay with

synchronous rectification and can be used to control current in

both directions with a single PWM input.

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

The two phases can also operate independently providing two

half-bridge drives. In this case, the dead time, blank time, and

VDS threshold will be common to both half-bridge drives.

The gate drive outputs can also be controlled through the serial

interface by setting the appropriate bit in the control register. In

the control register, all bits are active-high. The logical relation-

ship between the register bit setting and the gate drive outputs is

defined in Table 2.

The logic inputs are combined (using logical OR) with the cor-

responding bits in the serial interface control register to determine

the state of the gate drive. The logical relationship between the

combination of logic input and register bit setting and the gate

drive outputs is defined in Table 3. In most applications, either

the logic inputs or the serial control will be used. When using

only the logic inputs to control the bridge, the serial register

should be left in the reset condition with all control bits set to 0.

When using only the serial interface to control the bridge, the

inputs should be tied such that the active-low inputs are con-

nected to DL and the active high inputs connected to GND. That

is, HA and LB should be tied to GND, and HBn and LAn should

be tied to DL. The internal pull-up and pull-down resistors on

these inputs ensure that they go to the inactive state should they

become disconnected from the control signal level. However,

connecting these inputs to a fixed level can allow detection of

control input faults that would not be detected using only the

internal pull-up or pull-down.

Internal lockout logic ensures that the high-side output drive and

low-side output drive cannot be active simultaneously. When the

control inputs request active high-side and low side at the same

time for a single phase, then both high-side and low-side gate

drives will be forced low.

Output Disable

The ENABLE input is connected directly to the gate drive output

command signal, bypassing all phase control logic. This input can

be used to provide a fast output disable (emergency cutoff) or to

provide non-synchronous fast decay PWM.

ENABLE can also be monitored by a watchdog timer by setting

the EWD bit to 1. In watchdog mode, the first change of state

on the ENABLE input will activate the gate drive outputs under

command from the corresponding phase control signals, and a

watchdog timer is started. The ENABLE input must then change

state before the end of the ENABLE timeout period (tETO). If the

ENABLE input does not change before the end of the timeout

period, then all gate drive outputs will be driven low, and the

ETO bit will be set in the Status register. Any following change

of state on the ENABLE input will reactivate the gate drive

outputs. The ETO bit remains in the Status register until cleared.

Sleep Mode

RESETn is an active-low input that commands the A3922 to

enter sleep mode. In sleep mode, the part is inactive and the

current consumption from the VBB supply is reduced to a low

level, defined by IBBS. When RESETn is held low for longer than

approximately 200 µs, the gate drive outputs are disabled and

the current consumption from the VBB supply decays. Holding

RESETn low for 1 ms will ensure the part is fully in sleep mode.

Taking RESETn high to wake from sleep mode clears all previ-

ously reported latched fault states and corresponding fault bits.

When waking up from sleep mode, the protection logic ensures

that the gate drive outputs are held off until the charge pump

reaches its correct operating condition. The charge pump stabi-

lizes in approximately 3 ms, under nominal conditions.

To allow the A3922 to start up without the need for an external

logic input, the RESETn terminal can be pulled to VBB with an

external pull-up resistor.

Note that, if the voltage on the RESETn terminal rises above the

logic terminal overvoltage warning threshold (VLOV), then the

VLO bit will be set in the Status register.

RESETn can also be used to clear any fault conditions without

entering sleep mode by taking it low for the reset pulse width

(tRST). Any latched fault conditions, such as short detection or

bootstrap capacitor undervoltage, which disable the outputs, will

be cleared. RESETn will not reset the fault bits in the status or

diagnostic registers.

Current Sense Amplifier

A programmable gain, differential sense amplifier is provided

to allow the use of low-value sense resistors or current shunt as

a low-side current sensing element. The input common-mode

range of the CSP and CSM inputs and programmable output

offset allows below ground current sensing typically required

for low-side current sense in PWM control of motors, or other

inductive loads, during switching transients. The output of the

sense amplifier is available at the CSO output and can be used

in peak or average current control systems. The output can drive

up to 4.8 V to permit maximum dynamic range with higher input

voltage A-to-D converters.

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

The gain of the sense amplifier is defined by the contents of the

SAG[2:0] variable as:

SAG Gain SAG Gain

0 10 4 30

1 15 5 35

2 20 6 40

3 25 7 50

The output offset, VOOS, of the sense amplifier is defined by the

contents of the SAO[3:0] variable as:

SAO VOOS SAO VOOS

0 0 8 750 mV

1 0 9 1 V

2 100 mV 10 1.25 V

3 100 mV 11 1.5 V

4 200 mV 12 1.75 V

5 300 mV 13 2 V

6 400 mV 14 2.25 V

7 500 mV 15 2.5 V

Diagnostic Monitors

Multiple diagnostic features provide three levels of fault monitor-

ing. These include critical protection for the A3922, monitors for

operational voltages and states, and detection of power bridge

and load fault conditions. All diagnostics, except for POR, serial

transfer error, and overtemperature, can be masked by setting the

appropriate bit in the mask registers.

The fault status is available from the status and diagnostic

registers accessed through the serial interface.

Status and Diagnostic Registers

The serial interface allows detailed diagnostic information to be

read from the diagnostic registers on the SDO output terminal at

any time.

A system Status register provides a summary of all faults in a

single read transaction. The Status register is always output on

SDO when any register is written.

The first bit (bit 15) of the Status register contains a common

fault flag (FF), which will be high if any of the fault bits in the

Status register have been set. This allows fault condition to be

detected using the serial interface by simply taking STRn low. As

soon as STRn goes low, the first bit (bit 15) in the Status register

can be read on SDO to determine if a fault has been detected at

any time since the last fault register reset. In all cases, the fault

bits in the diagnostic registers are latched and only cleared after a

fault register reset.

FF provides an indication that a fault has occurred since the last

fault reset and one or more fault bits have been set.

Chip-Level Protection

Chip-wide parameters critical for correct operation of the A3922

are monitored. These include maximum chip temperature,

minimum internal logic supply voltage, and the serial interface

transmission. These three monitors are necessary to ensure that

the A3922 is able to respond as specified.

Table 4: Diagnostic Functions

Name Diagnostic Level

POR Internal logic supply undervoltage causing power-

on reset Chip

OT Chip junction overtemperature Chip

SE Serial transmission error Chip

TW High chip junction temperature warning Monitor

VSO VBB supply overvoltage (load dump detection) Monitor

VSU VBB supply undervoltage Monitor

VLO Logic terminal overvoltage Monitor

ETO ENABLE watchdog timeout Monitor

VRO VREG output overvoltage Monitor

VRU VREG output undervoltage Monitor

AHU A high-side VGS undervoltage Monitor

ALU A low-side VGS undervoltage Monitor

BHU B high-side VGS undervoltage Monitor

BLU B low-side VGS undervoltage Monitor

OCA Overcurrent on phase A Bridge

OCB Overcurrent on phase B Bridge

OL Open load Bridge

VA Bootstrap undervoltage phase A Bridge

VB Bootstrap undervoltage phase B Bridge

AHO Phase A high-side VDS overvoltage Bridge

ALO Phase A low-side VDS overvoltage Bridge

BHO Phase B high-side VDS overvoltage Bridge

BLO Phase B low-side VDS overvoltage Bridge

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

CHIP FAULT STATE: INTERNAL LOGIC UNDERVOLTAGE

The A3922 has an independent internal logic regulator to supply

the internal logic. This is to ensure that external events, other than

loss of supply, do not prevent the A3922 from operating correctly.

The internal logic supply regulator will continue to operate with

a low supply voltage—for example, if the main supply voltage

drops to a very low value during a severe cold-crank event.

In extreme low supply circumstances, or during power-up or

power-down, an undervoltage detector ensures that the A3922

operates correctly. The logic supply undervoltage lockout cannot

be masked as it is essential to guarantee correct operation over

the full supply range.

When power is first applied to the A3922, the internal logic is

prevented from operating, and all gate drive outputs are held in

the off state until the internal regulator voltage (VDL) exceeds

the logic supply undervoltage lockout rising (turn-on) threshold,

derived from the VBB POR threshold (VBBR). At this point, all

serial registers will be reset to their power-on state, and all fault

states will be reset. The FF bit and the POR bit in the Status

taken place. The A3922 then goes into its fully operational state

and begins operating as specified.

Once the A3922 is operational, the internal logic supply continues

to be monitored. If, during the operational state, VDL drops below

logic supply undervoltage lockout falling (turn-off) threshold,

derived from VBBR, then the logical function of the A3922 cannot

be guaranteed, and the outputs will be immediately disabled. The

A3922 will enter a power-down state, and all internal activity,

other than the logic regulator voltage monitor, will be suspended.

If the logic supply undervoltage is a transient event, then the

A3922 will follow the power-up sequence above as the voltage

rises.

CHIP FAULT STATE: OVERTEMPERATURE

If the chip temperature rises above the overtemperature threshold

(TJF), the overtemperature bit (OT) will be set in the Status

drive outputs will be disabled automatically. If ESF = 0, then

no circuitry will be disabled, and action must be taken by the

user to limit the power dissipation in some way so as to prevent

overtemperature damage to the chip and unpredictable device

operation. When the temperature drops below TJF by more than

the hysteresis value (TJFHys), the fault state is cleared, and when

ESF = 1, the outputs re-enabled. The overtemperature bit remains

in the Status register until reset.

CHIP FAULT STATE: SERIAL ERROR

If there are more than 16 rising edges on SCK, or if STRn goes

high and there are fewer than 16 rising edges on SCK, or the

parity is not odd, then the write will be cancelled without writing

data to the registers, and the SE bit will be set to indicate a data

transfer error. If the transfer is a write, then the Status register

will not be reset. If the transfer is a diagnostic or verification

result read, then the addressed register will not be reset.

Operational Monitors

Parameters related to the safe operation of the A3922 in a system

are monitored. These include parameters associated with external

active and passive components, power supplies, and interaction

with external controllers.

Voltages relating to driving the external power MOSFETs are

monitored, specifically VREG, each bootstrap capacitor voltage,

and the VGS of each gate drive output. The main supply voltage

(VBB) is only monitored for overvoltage and undervoltage events.

The logic inputs are capable of being shorted to the main supply

voltage without damage, but any high voltage on these pins will

be detected. In addition, a watchdog timer can be applied to the

ENABLE input to verify continued operation of the external

controller.

MONITOR: VREG UNDERVOLTAGE AND OVERVOLTAGE

The internal charge pump regulator supplies the low-side gate

driver and the bootstrap charge current. It is critical to ensure that

the regulated voltage (VREG) at the VREG terminal is sufficiently

high before enabling any of the outputs.

If VREG goes below the VREG undervoltage threshold (VROFF),

the VREG undervoltage bit (VRU) will be set in the Diag 1

be disabled, and the motor will coast. When VREG rises above the

rising threshold (VRON), the gate drive outputs are re-enabled and

the fault state is reset. The VRU bit remains in the Diag 1 register

until cleared.

The VREG undervoltage monitor circuit is active during power

up, and all gate drives will be low until VREG is greater than

VRON. Note that this is sufficient to turn on standard threshold

external power MOSFETs at a battery voltage as low as 5.5 V, but

the on-resistance of the MOSFET may be higher than its speci-

fied maximum.

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

The VREG undervoltage monitor can be disabled by setting the

VRU bit in the mask register. Although not recommended, this

can allow the A3922 to operate below its minimum specified

supply voltage level with a severely impaired gate drive. The

specified electrical parameters will not be valid in this condition.

The output of the VREG regulator is also monitored to detect any

overvoltage applied to the VREG terminal.

If VREG goes above the VREG overvoltage threshold (VROV), the

VREG overvoltage bit (VRO) will be set in the Diag 1 register.

No action will be taken as the gate drive outputs are protected

from overvoltage by independent Zener clamps. When VREG falls

below VROV by more than the hysteresis voltage (VROVHys), the

fault state is reset, but VRO bit remains in the Diag 1 register

until cleared.

MONITOR: TEMPERATURE WARNING

If the chip temperature rises above the temperature warning

threshold (TJW), the hot warning bit (TW) will be set in the

Status register. No action will be taken by the A3922. When the

temperature drops below TJW by more than the hysteresis value

(TJWHys), the fault state is cleared ,and the TW bit remains in the

Status register until reset.

MONITOR: VBB SUPPLY UNDERVOLTAGE AND OVER-

VOLTAGE

The main supply to the A3922 on the VBB terminal (VBB) is

monitored to indicate if the supply voltage is above, or has

exceeded, its normal operating range (for example, during a load-

dump event). If VBB rises above the VBB overvoltage warning

threshold (VBBOV), then the VSO bit will be set in the Diag 2

falling VBB overvoltage warning threshold (VBBOV – VBBOVHys),

the fault state is reset, but the VSO bit remains in the Diag 2

The main supply on the VBB terminal is also monitored to

indicate if the supply voltage is below its normal operating range.

If VBB goes below the VBB undervoltage threshold (VBBUV),

then the VSU bit will be set in the Diag 2 register. All gate drive

outputs will go low, the motor drive will be disabled, and the

motor will coast. When VBB rises above the rising VBB under-

voltage threshold (VBBUV + VBBUVHys), the fault state will be

reset, and the gate drive outputs re-enabled. The VSU bit remains

in the Diag 2 register until cleared.

MONITOR: VGS UNDERVOLTAGE

To ensure that the gate drive output is operating correctly, each

gate drive output voltage is independently monitored, when

active, to ensure the drive voltage (VGS) is sufficient to fully

enhance the power MOSFET in the external bridge.

If VGS on any active gate drive output goes below the gate drive

undervoltage warning (VGSUV), the corresponding gate drive

undervoltage bit (AHU, ALU, BHU, or BLU) will be set in the

Diag 0 register. No other action will be taken. When VGS rises

above VGSUV

, the fault state is reset, but the fault bits remain in

the Diag 0 register until cleared.

MONITOR: LOGIC TERMINAL OVERVOLTAGE

Six of the logic terminals are capable of being shorted to the main

supply voltage, up to 50 V, without damage. These terminals are

HA, HBn, LAn, LB, RESETn, and ENABLE. The voltage on

these pins (VL) is monitored to provide an indication of an input

short-to-battery fault. If VL on any of the terminals rises above

the logic terminal overvoltage warning threshold (VLOV), then

the VLO bit will be set in the Status register. If the fault is on one

of the inputs, and the ESF bit is set, then all gate drive outputs

will be disabled. When VL on all terminals falls below the logic

terminal overvoltage warning threshold (VLOV), the fault state is

reset, and the outputs will be re-activated. The VLO bit remains

in the Status register until cleared.

MONITOR: ENABLE WATCHDOG TIMEOUT

The ENABLE input provides a direct connection to all gate drive

outputs and can be used as a safety override to immediately deac-

tivate the outputs. The ENABLE input is programmed to operate

as a direct logic control by default, but it can be monitored by a

watchdog timer by setting the EWD bit to 1. In the direct mode,

the input is not monitored other than for input overvoltage as

described in the Logic terminal overvoltage section above. In

watchdog mode, the first change of state on the ENABLE input

will activate the gate drive outputs under command from the cor-

responding phase control signals, and a watchdog timer is started.

The ENABLE input must then change state before the end of the

ENABLE timeout period (tETO). If the ENABLE input does not

change before the end of the timeout period, then all gate drive

outputs will be driven low, and the ETO bit will be set in the

Status register. Any following change of state on the ENABLE

input will re-activate the gate drive outputs. The ETO bit remains

in the Status register until cleared.

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Power Bridge and Load Faults

BRIDGE: OVERCURRENT DETECT

The output from the sense amplifier can be compared to an

overcurrent threshold voltage (VOCT) to provide indication of

overcurrent events. VOCT is generated by a 4-bit DAC with

a resolution of 300 mV and defined by the contents of the

OCT[3:0] variable and the contents of the SAO[3:0] variable.

VOCT is approximately defined as:

VOCT = [(n + 1) × 300 mV]

where n is a positive integer defined by OCT[3:0].

Any offset programmed on SAO[3:0] is applied to both the cur-

rent sense amplifier output (CSO) and the overcurrent threshold

(VOCT) and has no effect on the overcurrent threshold (IOCT).

The relationship between the threshold voltage and the threshold

current is approximately defined as:

OCT

(R ×A)

where VOCT is the overcurrent threshold voltage programmed

by OCT[3:0], (RS) is the sense resistor value in Ω, and A

V is the

sense amp gain defined by SAG[2:0].

The output from the overcurrent comparator is filtered by an

overcurrent qualifier circuit. This circuit uses a timer to verify

that the output from each comparator is indicating a valid

overcurrent event. The qualifier can operate in one of two ways—

debounce or blanking—selected by the OCQ bit.

In the default debounce mode, a timer is started each time a

comparator output indicates, on overcurrent detection, when the

corresponding low-side MOSFET is active. This timer is reset

when the comparator changes back to indicate normal operation.

If the debounce timer reaches the end of the timeout period, set

by tOCQ, then the overcurrent event is considered valid, and the

corresponding overcurrent bit (OCA or OCB) will be set in the

Diag 2 register.

In the optional blanking mode, a timer is started when a low-

side gate drive is turned on. The output from the comparator is

ignored (blanked) for the duration of the timeout period, set by

tOCQ. If a comparator output indicates an overcurrent event when

the blanking timer is not active, then the overcurrent event is

considered valid, and the corresponding overcurrent bit (OCA or

OCB) will be set in the Diag 2 register.

The duration of the overcurrent qualifying timer (tOCQ) is

determined by the contents of the TOC[3:0] variable. tOCQ is

approximately defined as:

tOCQ = n × 500 ns

where n is a positive integer defined by TOC[3:0].

When a valid overcurrent is detected, no action is taken. Only the

OCA or OCB bits are set and remain in the Diag 2 register until

cleared.

BRIDGE: OPEN-LOAD DETECT

Two open-load fault detection methods are provided: an on-state

current monitor and an off-state open-load detector. An on-state

is defined by the state of the gate drive outputs as one high-side

switched on and the low-side in the opposite phase switched on.

The resulting two combinations are the only ones where current

can be passed through the low-side sense resistor. An off-state

is defined by the state of the gate drive outputs as all MOSFETs

switched off. In this state, the load connections are high imped-

ance and can be used to detect the presence or otherwise of a

load.

ON-STATE OPEN-LOAD DETECTION

When AOL = 0, the on-state open-load detection will be com-

pletely inactive. The on-state open-load detection is only enabled

when AOL = 1 and either GHA and GLB are on together or GHB

and GLA are on together.

During the on-state, the A3922 compares the output from the

sense amplifier against the open-load threshold voltage (VOLTON).

VOLTON is generated by an internal 4-bit DAC with a resolution

of 25 mV and defined by the contents of the OLT[3:0] variable.

VOLTON is approximately defined as:

VOLTON = (n + 1) × 25 mV

where n is a positive integer defined by OLT[3:0].

Any offset programmed on SAO[3:0] is applied to both the cur-

rent sense amplifier output (CSO) and the VOLTON threshold and

has no effect on the open-load detect threshold current threshold,

IOLT. The relationship between the threshold voltage and the

threshold current is approximately defined as:

OLT

OLTON

(R ×A)

Automotive Full-Bridge MOSFET Driver

A3922

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

where VOLTON is the open-load threshold voltage programmed by

OLT[3:0], RS is the sense resistor value in Ω and A

V is the sense

amp gain defined by SAG[2:0].

If the output of the sense amplifier is less than VOLTON during

the on-state, then a timer is allowed to increment. If the output of

the amplifier is higher than VOLTON during the on-state, then the

timer is reset. If the timer reaches the open-load timeout value

tOLTO (typically 100 ms) then the open-load fault bit (OL) will be

set in the Diag 2 register indicating a valid open-load condition.

As soon as the output of the amplifier is higher than VOLTON

during the on-state, then the fault state is reset, but the OL bit

remains in the Diag 2 register until cleared.

If the sense amplifier is not used in an application, then the on-

state open-load detection can be completely disabled by setting

AOL to 0.

OFF-STATE OPEN-LOAD DETECTION

When DOO = 1, the off-state open-load detection will be com-

pletely disabled. The off-state open-load detection is only enabled

when DOO = 0 and all gate drive outputs are off. In the off-state,

a current sink (IOLTS) is applied to the SB terminal, and a current

source (IOLTT) is applied to the SA terminal.

IOLTS is typically 10 mA, which is low enough to allow the

A3922 to survive a short to VBB on the SB terminal during the

off-state without damage, and high enough to discharge any

output capacitance in an acceptable time.

The value of IOLTT is selected by the OLI bit. When OLI = 0,

IOLTT = 100 µA; when OLI = 1, IOLTT = 400 µA.

The sink current (IOLTS) pulls the SB terminal to ground once

any energy remaining in the load, when entering the off-state, has

dissipated. The source current (IOLTT) applies a test current to the

load. As the sink current is much larger than the source current,

the current through the load will be the source current. The

voltage at the SB terminal (VSB) should be close to zero, and the

voltage at the SA terminal (VSA) will allow the load resistance to

be measured. VSA is compared to a fixed threshold (VOLTOFF) of

typically 1 V. If VSA is less than VOLTOFF, then a load is assumed

to be present. If VSA is greater than VOLTOFF, then a timer is

started. If the timer reaches the open-load timeout value tOLTO

(typically 100 ms), then the open-load fault bit (OL) will be set in

the Diag 2 register, indicating a valid open-load condition.

When OLI = 0, the threshold for load resistance is 10 kΩ; when

OLI = 1, the threshold is 2.5 kΩ. So any load resistance greater

than 10 or 2.5 kΩ respectively is indicated as an open load.

If the bridge exits the off-state at any time before the timeout is

complete, then the timer is reset without indicating an open load.

If VSA becomes less than VOLTOFF, or if the bridge exits the

off-state after the open-load fault condition has been detected,

then the fault state is cleared, but the OL bit remains in the Diag 2

BRIDGE: BOOTSTRAP CAPACITOR UNDERVOLTAGE

FAULT