KU82596SX20 - Intel - Datasheet.Cloud

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82596DX AND 82596SX

HIGH-PERFORMANCE 32-BIT LOCAL

AREA NETWORK COPROCESSOR

YPerforms Complete CSMA/CD Medium

Access Control (MAC) FunctionsÐ

Independently of CPU

Ð IEEE 802.3 (EOC) Frame Delimiting

YSupports Industry Standard LANs

Ð IEEE TYPE 10BASE-T (TPE),

IEEE TYPE 10BASE5 (Ethernet*),

IEEE TYPE 10BASE2 (Cheapernet),

IEEE TYPE 1BASE5 (StarLAN),

and the Proposed Standard

TYPE 10BASE-F

Ð Proprietary CSMA/CD Networks Up

to 20 Mb/s

YOn-Chip Memory Management

Ð Automatic Buffer Chaining

Ð Buffer Reclamation after Receipt of

Bad Frames; Optional Save Bad

Frames

Ð 32-Bit Segmented or Linear (Flat)

Memory Addressing Formats

Y82586 Software Compatible

YOptimized CPU Interface

Ð 82596DX Bus Interface Optimized to

Intel’s 32-Bit i386TMDX

Ð 82596SX Bus Interface Optimized to

Intel’s 16-Bit i386TMSX

Ð Supports Big Endian and Little

Endian Byte Ordering

YHigh-Performance 16-/32-Bit Bus

Master Interface

Ð 66-MB/s Bus Bandwidth

Ð 33-MHz Clock, Two Clocks Per

Transfer

Ð Bus Throttle Timers

Ð Transfers Data at 100% of Serial

Bandwidth

Ð 128-Byte Receive FIFO, 64-Byte

Transmit FIFO

YNetwork Management and Diagnostics

Ð Monitor Mode

Ð 32-Bit Statistical Counters

YSelf-Test Diagnostics

YConfigurable Initialization Root for Data

Structures

YHigh-Speed, 5-V, CHMOS** IV

Technology

Y132-Pin Plastic Quad Flat Pack (PQFP)

and PGA Package

(See Packaging Specifications Order Number: 240800-001,

Package Type KU and A)

i386TM is a trademark of Intel Corporation

*Ethernet is a registered trademark of Xerox Corporation.

**CHMOS is a patented process of Intel Corporation.

290219–1

Figure 1. 82596DX/SX Block Diagram

82596DX/SX

82596DX and 82596SX High-Performance

32-Bit Local Area Network Coprocessor

CONTENTS PAGE

INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3

PIN DESCRIPTIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

82596 AND HOST CPU

INTERACTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

82596 BUS INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

82596 MEMORY ADDRESSING ÀÀÀÀÀÀÀÀÀÀ 14

82596 SYSTEM MEMORY

STRUCTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16

TRANSMIT AND RECEIVE MEMORY

STRUCTURES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

TRANSMITTING FRAMES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

RECEIVING FRAMES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

82596 NETWORK MANAGEMENT AND

DIAGNOSTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

NETWORK PLANNING AND

MAINTENANCE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

STATION DIAGNOSTICS AND SELF-

TEST ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

82586 SOFTWARE COMPATIBILITY ÀÀÀÀÀ 24

INITIALIZING THE 82596 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

SYSTEM CONFIGURATION POINTER

(SCP) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

Writing the Sysbus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

INTERMEDIATE SYSTEM

CONFIGURATION POINTER

(ISCP) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26

INITIALIZATION PROCESS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26

CONTROLLING THE 82596DX/SX ÀÀÀÀÀÀÀ 27

82596 CPU ACCESS INTERFACE

(PORTÝ)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27

MEMORY ADDRESSING FORMATS ÀÀÀÀÀ 28

LITTLE ENDIAN AND BIG ENDIAN

BYTE ORDERING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28

COMMAND UNIT (CU) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29

RECEIVE UNIT (RU) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

SYSTEM CONTROL BLOCK (SCB) ÀÀÀÀÀÀ 30

SCB OFFSET ADDRESSES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

CONTENTS PAGE

CBL Offset (Address) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

RFA Offset (Address) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

SCB STATISTICAL COUNTERS ÀÀÀÀÀÀÀÀÀÀ 34

Statistical Counter Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

ACTION COMMANDS AND

OPERATING MODES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35

NOP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35

Individual Address Setup ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36

Configure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

Multicast-Setup ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43

Transmit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44

Jamming Rules ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 46

TDR ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 47

Dump ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49

Diagnose ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 52

RECEIVE FRAME DESCRIPTOR ÀÀÀÀÀÀÀÀÀ 52

Simplified Memory Structure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53

Flexible Memory Structure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 54

Receive Buffer Descriptor (RBD) ÀÀÀÀÀÀÀ 55

PGA PACKAGE THERMAL

SPECIFICATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 60

ELECTRICAL AND TIMING

CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 60

Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 60

DC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 60

AC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61

82596DX Input/Output System

Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61

82596SX Input/Output System

Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 63

Transmit/Receive Clock

Parameters ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 66

82596DX/SX BUS OPERATION ÀÀÀÀÀÀÀÀÀÀ 68

System Interface A.C. Timing

Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 69

Input Waveforms ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 70

Serial A.C. Timing Characteristics ÀÀÀÀÀÀÀÀÀÀ 72

OUTLINE DIAGRAMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 74

REVISION SUMMARY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 77

82596DX/SX

INTRODUCTION

The 82596DX/SX is an intelligent, high-performance

32-bit Local Area Network coprocessor. The

82596DX/SX implements the CSMA/CD access

method and can be configured to support all exist-

ing IEEE 802.3 standardsÐTYPEs 10BASE-T,

10BASE5, 10BASE2, 1BASE5, and 10BROAD36. It

can also be used to implement the proposed stan-

dard TYPE 10BASE-F. The 82596DX/SX performs

high-level commands, command chaining, and inter-

processor communications via shared memory, thus

relieving the host CPU of many tasks associated

with network control. All time-critical functions are

performed independently of the CPU, this increases

network performance and efficiency. The

82596DX/SX bus interface is optimized for Intel’s

i386TM DX and i386TM SX microprocessors.

The 82596DX/SX implements all IEEE 802.3 Medi-

um Access Control and channel interface functions,

these include framing, preamble generation and

stripping, source address generation, destination ad-

dress checking, short-frame detection, and automat-

ic length-field handling. Data rates up to 20 Mb/s are

supported.

The 82596DX/SX provides a powerful host system

interface. It manages memory structures automati-

cally, with command chaining and bidirectional data

chaining. An on-chip DMA controller manages four

channels, this allows autonomous transfer of data

blocks (buffers and frames) and relieves the CPU of

byte transfer overhead. Buffers containing errored or

collided frames can be automatically recovered with-

out CPU intervention. The 82596DX/SX provides an

upgrade path for existing 82586 software drivers by

providing an 82586-software-compatible mode that

supports the current 82586 memory structure. The

82596DX/SX also has a Flexible memory structure

and a Simplified memory structure. The 82596DX/

SX can address up to 4 gigabytes of memory. The

82596DX/SX supports Little Endian and Big Endian

byte ordering.

The 82596DX/SX bus interface is optimized to In-

tel’s i386TM DX and i386 SX microprocessors, pro-

viding a bus transfer rate of up to 66 MB/s at

33 MHz. The bus interface employs bus throttle tim-

ers to regulate 82596DX/SX bus use. Two large, in-

dependent FIFOsÐ128 bytes for Receive and 64

bytes for TransmitÐtolerate long bus latencies and

provide programmable thresholds that allow the

user to optimize bus overhead for any worst-case

bus latency.

The 82596DX/SX provides a wide range of diagnos-

tics and network management functions, these in-

clude internal and external loopback, exception con-

dition tallies, channel activity indicators, optional

capture of all frames regardless of destination ad-

dress (promiscuous mode), optional capture of er-

rored or collided frames, and time domain reflectom-

etry for locating fault points on the network cable.

The statistical counters, in 32-bit segmented and lin-

ear modes, are 32-bits each and include CRC errors,

alignment errors, overrun errors, resource errors,

short frames, and received collisions. The

82596DX/SX also features a monitor mode for net-

work analysis. In this mode the 82596DX/SX can

capture status bytes, and update statistical coun-

ters, of frames monitored on the link without trans-

ferring the contents of the frames to memory. This

can be done concurrently while transmitting and re-

ceiving frames destined for that station.

The 82596DX/SX can be used in both baseband

and broadband networks. It can be configured for

maximum network efficiency (minimum contention

overhead) with networks of any length. Its highly

flexible CSMA/CD unit supports address field

lengths of zero through six bytes for IEEE 802.3/

Ethernet frame delimitation. It also supports 16- or

32-bit cyclic redundancy checks. The CRC can be

transferred directly to memory for receive, opera-

tions or dynamically inserted for transmit operations.

The CSMA/CD unit can also be configured for full

duplex operation for high throughput in point-to-point

connections.

The 82596 C-Step incorporates several new fea-

tures not found in previous steppings. The following

is a summary of the 82596 C-step’s new features.

#The 82596 C-step fixes Errata found in the A1

and B steppings.

#The 82596 C-step has improved AC timings over

both the A and B steppings.

#The 82596 C-step has a New Enhanced Big Endi-

an Mode where in Linear Addressing mode, true

32-bit Big Endian functionality is achieved. New

Enhanced Big Endian Mode is enabled by setting

bit 7 of the SYSBUS byte. This mode is software

compatible with the big endian mode of the B-

step with one exceptionÐno 32-bit addresses

need to be swapped by software in the C-step. In

this new mode, the 82596 C-step treats 32-bit ad-

dress pointers as true 32-bit entities and the SCB

absolute address and statistical counters are still

treated as two 16-bit big endian entities. Not set-

ting this mode will configure the 82596 C-step to

be 100% compatible to the A1-step bit endian

mode.

#The 82596 C-step is hardware and software com-

patible to both the A1 and B steppings allowing

for easy ‘‘drop-in’’ to current designs. Pinout and

control structures remain unchanged.

The 82596DX/SX is fabricated with Intel’s reliable,

5-V, CHMOS IV (Process 648.8) technology. It is

available in a 132-pin PQFP or PGA package.

82596DX/SX

290219–2

Figure 2a. 82596DX PQFP Pin Configuration

82596DX/SX

290219–34

Figure 2b. 82596SX PQFP Pin Configuration

82596DX/SX

290219–3

Figure 3a. 82596DX PGA Pin View Side

82596DX/SX

82596DX PGA Cross Reference by Pin Name

Address Data Control Serial N/C VCC VSS

Interface

Signal Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Pin No. Pin No. Pin No.

A2N9 D0J2 ADS M5 CDT A13 K3 B6 A6

A3M9 D1H3 BE0 M7 CRS A14 L1 B7 A7

A4M10 D2G2 BE1 P5 CTS C11 L2 B10 A8

A5P11 D3G3 BE2 M8 LPBK A12 L3 E2 A10

A6N11 D4G1 BE3 P9 RTS C10 N2 E13 C13

A7P12 D5D1 BREQ P4 RxC B11 P1 F2 E1

A8M11 D6C1 BS16 N1 RxD B12 G13 E14

A9N12 D7F3 CA P3 TxC C12 H2 F1

A10 M12 D8D2 CLK2 J3 TxD A11 H13 G14

A11 P13 D9C2 HLDA M6 J13 H1

A12 L12 D10 E3 HOLD P2 K2 H14

A13 N13 D11 D3 INT/INT N3 L13 J1

A14 M13 D12 B2 LE/BE B14 M1 J14

A15 P14 D13 B1 LOCK M4 N6 K1

A16 K12 D14 C3 PORT M2 N7 L14

A17 N14 D15 A1 READY M3 N8 N5

A18 J12 D16 B3 RESET B13 N10 P6

A19 K13 D17 C4 W/R N4 P7

A20 M14 D18 A2 P8

A21 H12 D19 C5 P10

A22 K14 D20 A3

A23 G12 D21 B4

A24 F14 D22 A4

A25 F12 D23 C6

A26 F13 D24 B5

A27 D14 D25 C7

A28 E12 D26 A5

A29 D13 D27 B8

A30 D12 D28 C8

A31 C14 D29 A9

D30 C9

D31 B9

82596DX/SX

290219–35

Figure 3b. 82596SX PGA Pin View Side

82596DX/SX

82596SX PGA Cross Reference by Pin Name

Address Data Control Serial N/C VCC VSS

Interface

Signal Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Pin No. Pin No. Pin No.

A2N9 D0J2 ADS M5 CDT A13 A2 B6 A6

A3M9 D1H3 BLE M7 CRS A14 A3 B7 A7

A4M10 D2G2 BHE P5 CTS C11 A4 B10 A8

A5P11 D3G3 BON P9 LPBK A12 A5 E2 A10

A6N11 D4G1 BREQ P4 RTS C10 A9 E13 C13

A7P12 D5D1 CA P3 RxC B11 B3 F2 E1

A8M11 D6C1 CLK2 J3 RxD B12 B4 G13 E14

A9N12 D7F3 HLDA M6 TxC C12 B5 H2 F1

A10 M12 D8D2 HOLD P2 TxD A11 B8 H13 G14

A11 P13 D9C2 INT/INT N3 B9 J13 H1

A12 L12 D10 E3 LE/BE B14 C4 K2 H14

A13 N13 D11 D3 LOCK M4 C5 L13 J1

A14 M13 D12 B2 PORT M2 C6 M1 J14

A15 P14 D13 B1 RDY M3 C7 N5 K1

A16 K12 D14 C3 RESET B13 C8 N6 L14

A17 N14 D15 A1 W/R N04 C9 N7 N1

A18 J12 K3 N8 P6

A19 K13 L1 N10 P7

A20 M14 L2 P8

A21 H12 L3 P10

A22 K14 N2

A23 G12 P1

A24 F14

A25 F12

A26 F13

A27 D14

A28 E12

A29 D13

A30 D12

A31 C14

82596DX/SX

PIN DESCRIPTIONS

Symbol PQFP Type Name and Function

Pin No.

CLK2 9 I CLOCK. The system clock input provides the fundamental timing for

the 82596. It is internally divided by two to generate the 82596 clock.

All external timing parameters are specified in reference to the rising

edge of CLK2. For clock levels see D.C. Characteristics.

D31–D0 14–53 I/O DATA BUS. The 32 Data Bus lines are bidirectional, tri-state lines that

provide the general purpose data path between the 82596 and

memory. With the 82596DX the bus can be either 16 or 32 bits wide;

this is determined by the BS16 signal which is static. The 82596

always drives all 32 data lines during Write operations, even with a

16-bit bus. D0– D31 are floated after a Reset or when the bus is not

acquired.

These lines are inputs during a CPU Port access; in this mode the CPU

writes the next address to the 82596 through the Data lines. During

PORT commands (Relocatable SCP, Self-Test, and Dump) the

address must be aligned to a 16 byte boundary. This frees the D3–D0

lines so they can be used to distinguish the commands. The following

is a summary of the decoding data.

D0 D1 D2 D3 D4– D31 Function

0000 0000 Reset

0100 ADDR Relocatable SCP

1000 ADDR Self-Test

1100 ADDR Dump Command

(D15– D0) 14– 32 I/O These 16 Data Bus lines are bidirectional, tri-state lines that provide

the entire data path for the 82596SX. In the 82596SX D16– D31 are

not connected (NC).

A31– A2 70– 108 O ADDRESS LINES. These 30 tri-stated Address lines output the

address bits required for memory operation. These lines are floated

after a Reset or when the bus is not acquired.

A1 112 O The 82596SX requires this additional address line to output the

address bits required for memory operation.

BE3– BE0 109– 114 O BYTE ENABLE. (82596DX only.) These tri-stated signals are used to

indicate which bytes are involved with the current memory access. The

number of Byte Enable signals asserted indicates the physical size of

the data being transferred (1, 2, 3, or 4 bytes).

#BE0 indicates D0– D7

#BE1 indicates D8– D15

#BE2 indicates D16– D23

#BE3 indicates D24– D31

These lines are floated after a Reset or when the bus is not acquired.

BHE, BLE 113– 114 O (82596SX only.) These signals are the Byte High Enable and Byte Low

Enable signals for the 82596SX.

BON 109 O BUS ON. (82596SX only.) This signal is driven high when the 82596 is

holding the bus. This signal is tri-stated when the bus is relinquished.

BON has the same timing as the Byte Enables.

82596DX/SX

PIN DESCRIPTIONS (Continued)

Symbol PQFP Type Name and Function

Pin No.

W/R 120 O WRITE/READ. This dual-function pin is used to distinguish Write and

Read cycles. This line is floated after a Reset or when the bus is not

acquired.

ADS 124 O ADDRESS STATUS. This tri-state pin is used by the 82596 to indicate

that a valid bus cycle has begun and that A31– A2, BE3– BE0, and

W/R are being driven. It is asserted during t1 bus states. This line is

floated after a Reset or when the bus is not acquired.

RDY 130 I READY. Active low. This signal is the acknowledgment from

addressed memory that the transfer cycle can be completed. When

high, it causes wait states to be inserted. It is ignored at the end of the

first clock of the bus cycle’s data cycle. This active-low signal does not

have an internal pull-up resistor. This signal must meet the setup and

hold times to operate correctly.

LOCK 126 O LOCK. This tri-state pin is used to distinguish locked and unlocked bus

cycles. LOCK generates a semaphore handshake to the CPU. LOCK

can be active for several memory cycles, it goes active during the first

locked memory cycle (t1) and goes inactive at the last locked cycle

(t2). This line is floated after a Reset or when the bus is not acquired.

LOCK can be disabled via the sysbus byte in software.

BS16 129 I BUS SIZE. This signal allows the 82596DX to work with either 16- or

32-bit bytes. This signal is static and should be tied high for 32-bit

operation or low for 16-bit operation. In Little Endian mode the D0–

D15 lines are driven when BS16 is inserted, in Big Endian mode the

D16– D31 lines are driven.

HOLD 123 O HOLD. The HOLD signal is active high, the 82596 uses it to request

local bus mastership. In normal operation HOLD goes inactive before

HLDA. The 82596 can be forced off the bus by deasserting HLDA or if

the bus throttle timers expire.

HLDA 118 I HOLD ACKNOWLEDGE. The HLDA signal is active high, it indicates

that bus mastership has been given to the 82596. HLDA is internally

synchronized; after HOLD is detected low, the CPU drives HLDA low.

NOTE

Do not connect HLDA to V

Ðit will cause a deadlock.

A user wanting

to give the 82596 permanent access to the bus should connect HLDA

to HOLD. If HLDA goes inactive before HOLD, the 82596 will release

the bus (by deasserting HOLD) within a specified number of system

clocks.

BREQ 115 I BUS REQUEST. This signal, when configured to an externally

activated mode, is used to trigger the bus throttle timers.

82596DX/SX

PIN DESCRIPTIONS (Continued)

Symbol PQFP Type Name and Function

Pin No.

PORT 3IPORT. When this signal is received, the 82596 latches the data on the

data bus into an internal 32-bit register. When the CPU is asserting this

signal it can write into the 82596 (via the data bus). This pin must be

activated twice during all CPU Port access commands.

RESET 69 I RESET. This active high, internally synchronized signal causes the

82596 to terminate current activity. The signal must be high for at least

five system clock cycles. After five system clock cycles and four TxC

clock cycles the 82596 will execute a Reset when it receives a high

RESET signal. When RESET returns to low, the 82596 waits for the

first CA signal and then begins the initialization sequence.

LE/BE 65 I LITTLE ENDIAN/BIG ENDIAN. This dual-function pin is used to

select byte ordering. When LE/BE is high, little endian byte ordering is

used; when low, big endian byte ordering is used for data in frames

(bytes) and for control (SCB, RFD, CBL, etc.).

CA 119 I CHANNEL ATTENTION. The CPU uses this pin to force the 82596 to

begin executing memory resident Command blocks. The CA signal is

internally synchronized. The signal must be high for at least one

system clock. It is latched internally on the high to low edge and then

detected by the 82596.

The first CA after a Reset forces the 82596 into the initialization

sequence beginning at location 00FFFFF6h or an SCP address written

to the 82596 using CPU Port access. All subsequent CA signals cause

the 82596 to begin executing new command sequences from the SCB.

INT/INT 125 O INTERRUPT. A high signal on this pin notifies the CPU that the 82596

is requesting an interrupt. This signal is an edge triggered interrupt

signal, and can be configured to be active high or low.

VCC 18 Pins (DX) POWER. a5V g10%.

19 Pins (SX)

VSS 19 Pins GROUND. 0V.

(DX and SX)

TxD 54 O TRANSMIT DATA. This pin transmits data to the serial link. It is high

when not transmitting.

TxC 64 I TRANSMIT CLOCK. This signal provides the fundamental timing for

the serial subsystem. The clock is also used to transmit data

synchronously on the TxD pin. For NRZ encoding, data is transferred

to the TxD pin on the high to low clock transition. For Manchester

encoding, the transmitted bit center is aligned with the low to high

transition. Transmit clock should always be running for proper device

operation.

82596DX/SX

PIN DESCRIPTIONS (Continued)

Symbol PQFP Type Name and Function

Pin No.

LPBK 58 O LOOPBACK. This TTL-level control signal enables the loopback

mode. In this mode serial data on the TxD input is routed through the

82C501 internal circuits and back to the RxD output without driving the

transceiver cable. To enable this signal, both internal and external

loopback need to be set with the Configure command.

RxD 60 I RECEIVE DATA. This pin receives NRZ serial data only. It must be

high when not receiving.

RxC 59 I RECEIVE CLOCK. This signal provides timing information to the

internal shifting logic. For NRZ data the state of the RxD pin is

sampled on the high to low transition of the clock.

RTS 57 O REQUEST TO SEND. When this signal is low the 82596 informs the

external interface that it has data to transmit. It is forced high after a

Reset or when transmission is stopped.

CTS 62 I CLEAR TO SEND. An active-low signal that enables the 82596 to

send data. It is normally used as an interface handshake to RTS.

Asserting CTS high stops transmission. CTS is internally synchronized.

If CTS goes inactive, meeting the setup time to the TxC negative edge,

the transmission will stop and RTS will go inactive within, at most, two

TxC cycles.

CRS 63 I CARRIER SENSE. This signal is active low, it is used to notify the

82596 that traffic is on the serial link. It is only used if the 82596 is

configured for external Carrier Sense. In this configuration external

circuitry is required for detecting traffic on the serial link. CRS is

internally synchronized. To be accepted, the signal must remain active

for at least two serial clock cycles (for CRSFe0).

CDT 61 I COLLISION DETECT. This active-low signal informs the 82596 that a

collision has occurred. It is only used if the 82596 is configured for

external Collision Detect. External circuitry is required for collision

detection. CDT is internally synchronized. To be accepted, the signal

must remain active for at least two serial clock cycles (for CDTFe0).

82596DX/SX

82596 AND HOST CPU INTERACTION

The 82596DX/SX and the host CPU communicate

through shared memory. Because of its on-chip

DMA capability, the 82596 can make data block

transfers (buffers and frames) independently of the

CPU; this greatly reduces the CPU byte transfer

overhead.

NOTE:

The 82596DX and 82596SX differ in their address

pin definitions and their data bus sizes. Information

in this data sheet applies to both versions unless

otherwise stated.

The 82596 is a multitasking coprocessor that com-

prises two independent logical unitsÐthe Command

Unit (CU) and the Receive Unit (RU). The CU exe-

cutes commands from shared memory. The RU han-

dles all activities related to frame reception. The in-

dependence of the CU and RU enables the 82596 to

engage in both activities simultaneouslyÐthe CU

can fetch and execute commands from memory

while the RU is storing received frames in memory.

The CPU is only involved with this process after the

CU has executed a sequence of commands or the

RU has finished storing a sequence of frames.

The CPU and the 82596 use the hardware signals

Interrupt (INT) and Channel Attention (CA) to initiate

communication with the System Control Block

(SCB), see Figure 4. The 82596 uses INT to alert the

CPU of a change in the contents of the SCB, the

CPU uses CA to alert the 82596.

The 82596 has a CPU Port Access state that allows

the CPU to execute certain functions without ac-

cessing memory. The 82596 PORT pin and data bus

pins are used to enable this feature. The CPU can

directly activate four operations when the 82596 is in

this state.

#Write an alternative System Configuration Pointer

(SCP). This can be used when the 82596 cannot

use the default SCP address space.

#Write a different Dump Command Pointer and ex-

ecute Dump. This can be used for troubleshoot-

ing No Response problems.

#The CPU can reset the 82596 via software with-

out disturbing the rest of the system.

#A self-test can be used for board testing; the

82596 will execute a self-test and write the re-

sults to memory.

82596 BUS INTERFACE

The 82596DX/SX has bus interface timings and pin

definitions that are compatible with Intel’s 32-bit i386

DX and i386 SX microprocessors. This eliminates

the need for additional bus interface logic. Operating

at 33 MHz, the 82596’s bus bandwidth can be as

high as 66 MB/s. Since Ethernet only requires

1.25 MB/s, this leaves a considerable amount of

bandwidth for the CPU. The 82596 also has a bus

throttle to regulate its use of the bus. Two timers can

be programmed through the SCB: one controls the

maximum time the 82596 can remain on the bus, the

other controls the time the 82596 must stay off the

bus (see Figure 5). The bus throttle can be pro-

grammed to trigger internally with HLDA or external-

ly with BREQ. These timers can restrict the 82596

HOLD activation time and improve bus utilization.

82596 MEMORY ADDRESSING

The 82596 has a 32-bit memory address range,

which allows addressing up to four gigabytes of

memory. The 82596 has three memory addressing

modes (see Table 1).

#82586 Mode. The 82596 has a 24-bit memory

address range. The System Control Block, Com-

mand List, Receive Descriptor List, and Buffer

Descriptors must reside in one 64-kB memory

segment. Transmit and Receive buffers can re-

side in a 24-bit address space.

#32-Bit Segmented Mode. The 82596 has a 32-

bit memory address range. The System Control

Block, Command List, Receive Descriptor List,

and Buffer Descriptors must reside in one 64-kB

memory segment. Transmit and Receive buffers

can reside in a 32-bit address space.

#Linear Mode. The 82596 has a 32-bit memory

address range. Any memory structure can reside

anywhere within the 32-bit memory address

range.

82596DX/SX

290219–4

Figure 4. 82596 and Host CPU Intervention

290219–5

Figure 5. Bus Throttle Timers

Table 1. 82596 Memory Addressing Formats

Operation Mode

Pointer or Offset 82586 32-Bit Linear

Segmented

ISCP ADDRESS 24-Bit Linear 32-Bit Linear 32-Bit Linear

SCB ADDRESS Base (24) aOffset (16) Base (32) aOffset (16) 32-Bit Linear

Command Block Pointers Base (24) aOffset (16) Base (32) aOffset (16) 32-Bit Linear

Rx Frame Descriptors Base (24) aOffset (16) Base (32) aOffset (16) 32-Bit Linear

Tx Frame Descriptors Base (24) aOffset (16) Base (32) aOffset (16) 32-Bit Linear

Rx Buffer Descriptors Base (24) aOffset (16) Base (32) aOffset (16) 32-Bit Linear

Tx Buffer Descriptors Base (24) aOffset (16) Base (32) aOffset (16) 32-Bit Linear

Rx Buffers 24-Bit Linear 32-Bit Linear 32-Bit Linear

Tx Buffers 24-Bit Linear 32-Bit Linear 32-Bit Linear

82596DX/SX

290219–6

Figure 6. 82596 Shared Memory Structure

82596 SYSTEM MEMORY

STRUCTURE

The Shared Memory structure consists of four parts:

the Initialization Root, the System Control Block, the

Command List, and the Receive Frame Area (see

Figure 6).

The Initialization Root is in an established location

known to the host CPU and the 82596 (00FFFFF6h).

However, the CPU can establish the Initialization

Root in another location by using the CPU Port ac-

cess. This root is accessed during initialization, and

points to the System Control Block.

The System Control Block serves as a bidirectional

mail drop for the host CPU and the 82596 CU and

RU. It is the central point through which the CPU and

the 82596 exchange control and status information.

The SCB has two areas. The first contains instruc-

tions from the CPU to the 82596. These include:

control of the CU and RU (Start, Abort, Suspend,

and Resume), a pointer to the list of CU commands,

a pointer to the Receive Frame Area, a set of Inter-

rupt Acknowledge bits, and the T-ON and T-OFF

timers for the bus throttle. The second area contains

status information the 82596 is sending to the CPU.

Such as, the CU and RU states (Idle, Active

82596DX/SX

Ready, Suspended, No Receive Resources, etc.), in-

terrupt bits (Command Completed, Frame Received,

CU Not Ready, and RU Not Ready), and statistical

counters.

The Command List functions as a program for the

CU; individual commands are placed in memory

units called Command Blocks (CBs). These CBs

contain the parameters and status of specific high-

level commands called Action Commands; e.g.,

Transmit or Configure.

Transmit causes the 82596 to transmit a frame. The

Transmit CB contains the destination address, the

length field, and a pointer to a list of linked buffers

holding the frame that is to be constructed from sev-

eral buffers scattered throughout memory. The

Command Unit operates without CPU intervention;

the DMA for each buffer, and the prefetching of ref-

erences to new buffers, is performed in parallel. The

CPU is notified only after a transmission is complete.

The Receive Frame Area is a list of Free Frame De-

scriptors (descriptors not yet used) and a list of user-

prepared buffers. Frames arrive at the 82596 unso-

licited; the 82596 must always be ready to receive

and store them in the Free Frame Area. The Re-

ceive Unit fills the buffers when it receives frames,

and reformats the Free Buffer List into received-

frame structures. The frame structure is, for all prac-

tical purposes, identical to the format of the frame to

be transmitted. The first Frame descriptor is refer-

enced by the SCB. Unless the 82596 is configured

to Save Bad Frames, the frame descriptor, and the

associated buffer descriptor, which is wasted when

a bad frame is received, are automatically reclaimed

and returned to the Free Buffer List.

Receive buffer chaining (storing incoming frames in

a linked buffer list) significantly improves memory

utilization. Without buffer chaining, the user must al-

locate consecutive blocks of memory, each capable

of containing a maximum frame (for Ethernet, 1518

bytes). Since an average frame is about 200 bytes,

this is very inefficient. With buffer chaining, the user

can allocate small buffers and the 82596 will only

use those that are needed.

Figure 7 A– D illustrates how the 82596 uses the

Receive Frame Area. Figure 7A shows an unused

Receive Frame Area composed of Free Frame De-

scriptors and Free Receive Buffers prepared by the

user. The SCB points to the first Frame Descriptor of

the Frame Descriptor List. Figure 7B shows the

same Receive Frame Area after receiving one

frame. This first frame occupies two Receive Buffers

and one Frame DescriptorÐa valid received frame

will only occupy one Frame Descriptor. After receiv-

ing this frame the 82596 sets the next Free Frame

Descriptor RBD pointer to the next Free RBD. Figure

7C shows the RFA after receiving a second frame.

In this example the second frame occupies only one

Receive Buffer and one RFD. The 82596 again sets

the RBD pointer. This process is repeated again in

Figure 7D, showing the reception of another frame

using one Receive Buffer; in this example there is an

extra Frame Descriptor.

TRANSMIT AND RECEIVE MEMORY

STRUCTURES

There are three memory structures for reception and

transmission. The 82586 memory structure, the

Flexible memory structure, and the Simplified memo-

ry structure. The 82586 mode is selected by config-

uring the 82596 during initialization. In this mode all

the 82596 memory structures are compatible with

the 82586 memory structures.

When the 82596 is not configured to the 82586

mode, the other two memory structures, Simplified

and Flexible, are available for transmitting and re-

ceiving. These structures are selected by setting the

S/F bit in the Transmit Command and/or the Re-

ceive Frame Descriptor (see Figures 29, 30, 41, and

42). It is recommended that any linked list of buffers

be relegated to a single typeÐeither simplified or

flexible. The Simplified memory structure offers a

simple structure for ease of programming (see Fig-

ure 8). All information about a frame is contained in

one structure; for example, during reception the RFD

and data field are contained in one structure.

The Flexible memory structure (see Figure 9) has a

control field that allows the programmer to specify

the amount of receive data the RFD will contain for

receive operations and the amount of transmit data

the Transmit Command Block will contain for trans-

mit operations. For example, when the control field

in the RFD is set to 20 bytes during a reception, the

first 20 bytes of the data field are stored in the RFD

(6 Bytes of Destination Address, 6 Bytes of Source

Address, 2 Bytes of Length Field, and 6 Bytes of

Data), and the remainder of the data field is stored in

the Receive Data Buffers. This is useful for capturing

frame headers when header information is con-

tained in the data field. The header information can

then be automatically stored in the RFD partitioned

from the Receive Data Buffer.

The control field can also be used for the Transmit

Command when the Flexible memory structure is

used. The quantity of data field bytes to be transmit-

ted from the Transmit Command Block is specified

by the variable control field.

82596DX/SX

290219–7

Figure 7. Frame Reception in the RFA

82596DX/SX

290219–8

Figure 8. Simplified Memory Structure

290219–9

Figure 9. Flexible Memory Structure

82596DX/SX

TRANSMITTING FRAMES

The 82596 executes high-level Action Commands

from the Command List in system memory. Action

Commands are fetched and executed in parallel with

the host CPU operation, thereby significantly improv-

ing system performance. The format of the Action

Commands is shown in Figure 10. Figure 28 shows

the 82586 mode, and Figures 29 and 30 shows the

command formats of the Linear and 32-bit Segment-

ed modes.

A single Transmit command contains, as part of the

command-specific parameters, the destination ad-

dress and length field of the transmitted frame and a

pointer to buffer area in memory containing the data

portion of the frame. The data field is contained in a

memory data structure consisting of a buffer de-

scriptor (BD) and a data bufferÐor a linked list of

buffer descriptors and buffersÐas shown in Figure

11.

Multiple data buffers can be chained together using

the BDs. Thus, a frame with a long data field can be

transmitted using several (shorter) data buffers

chained together. This chaining technique allows the

system designer to develop efficient buffer manage-

ment.

The 82596 automatically generates the preamble

(alternating 1s and 0s) and start frame delimiter,

fetches the destination address and length field from

the Transmit command, inserts its unique address

as the source address, fetches the data field speci-

fied by the Transmit command, and computes and

appends the CRC to the end of the frame (see Fig-

ure 12). In the Linear and 32-bit Segmented mode

the CRC can be optionally inserted on a frame-by-

frame basis by setting the NC bit in the Transmit

Command Block (see Figures 29 and 30).

The 82596 generates the standard End Of Carrier

(EOC) start and end frame delimiters. In EOC, the

start frame delimiter is 10101011 and the end frame

delimiter is indicated by the lack of a signal after the

last bit of the frame check sequence field has been

transmitted. In EOC, the 82596 can be configured to

extend short frames by adding pad bytes (7Eh) dur-

ing transmission, according to the length field.

When a collision occurs, the 82596 manages the

jam, random wait, and retry processes, reinitializing

DMA pointers without CPU intervention. Multiple

frames can be sent by linking the appropriate num-

ber of Transmit commands together. This is particu-

larly useful when transmitting a message larger than

the maximum frame size (1518 bytes for Ethernet).

290219–10

Figure 10. Action Command Format

290219–11

Figure 11. Data Buffer Descriptor and

Data Buffer Structure

82596DX/SX

START DESTINATION SOURCE LENGTH DATA FRAME END

PREAMBLE FRAME ADDRESS ADDRESS FIELD FIELD CHECK FRAME

DELIMITER SEQUENCE DELIMITER

Figure 12. Frame Format

RECEIVING FRAMES

To reduce CPU overhead, the 82596 is designed to

receive frames without CPU supervision. The host

CPU first sets aside an adequate receive buffer

space and then enables the 82596 Receive Unit.

Once enabled, the RU watches for arriving frames

and automatically stores them in the Receive Frame

Area (RFA). The RFA contains Receive Frame De-

scriptors, Receive Buffer Descriptors, and Data Buff-

ers (see Figure 13). The individual Receive Frame

Descriptors make up a Receive Descriptor List

(RDL) used by the 82596 to store the destination

and source addresses, the length field, and the

status of each frame received (see Figure 14).

Once enabled, the 82596 checks each passing

frame for an address match. The 82596 will recog-

nize its own unique address, one or more multicast

addresses, or the broadcast address. If a match is

found the 82596 stores the destination and source

addresses and the length field in the next available

RFD. It then begins filling the next available Data

Buffer on the FBL, which is pointed to by the current

RFD, with the data portion of the incoming frame. As

one Data Buffer is filled, the 82596 automatically

fetches the next DB on the FBL until the entire frame

is received. This buffer chaining technique is particu-

larly memory efficient because it allows the system

designer to set aside buffers to fit frames much

shorter than the maximum allowable frame length. If

AL-LOC e1, or if the flexible memory structure is

used, the addresses and length field can be placed

in the receive buffer.

Once the entire frame is received without error, the

82596 does the following housekeeping tasks.

#The actual count field of the last Buffer Descrip-

tor used to hold the frame just received is updat-

ed with the number of bytes stored in the associ-

ated Data Buffer.

#The next available Receive Frame Descriptor is

fetched.

#The address of the next available Buffer Descrip-

tor is written to the next available Receive Frame

Descriptor.

#A frame received interrupt status bit is posted in

the SCB.

#An interrupt is sent to the CPU.

If a frame error occurs, for example a CRC error, the

82596 automatically reinitializes its DMA pointers

and reclaims any data buffers containing the bad

frame. The 82596 will continue to receive frames

without CPU help as long as Receive Frame De-

scriptors and Data Buffers are available.

82596 NETWORK MANAGEMENT

AND DIAGNOSTICS

The behavior of data communication networks is

normally very complex because of their distributed

and asynchronous nature. It is particularly difficult to

pinpoint a failure when it occurs. The 82596 has ex-

tensive diagnostic and network management func-

tions that help improve reliability and testability. The

82596 reports on the following events after each

frame is transmitted.

#Transmission successful.

#Transmission unsuccessful. Lost Carrier Sense.

#Transmission unsuccessful. Lost Clear to Send.

#Transmission unsuccessful. A DMA underrun oc-

curred because the system bus did not keep up

with the transmission.

#Transmission unsuccessful. The number of colli-

sions exceeded the maximum allowed.

#Number of Collisions. The number of collisions

experienced during transmission of the frame.

#Heartbeat Indicator. This indicates the presence

of a heartbeat during the last Interframe Spacing

(IFS) after transmission.

When configured to Save Bad Frames the 82596

checks each incoming frame and reports the follow-

ing errors.

#CRC error. Incorrect CRC in a properly aligned

frame.

#Alignment error. Incorrect CRC in a misaligned

frame.

#Frame too short. The frame is shorter than the

value configured for minimum frame length.

#Overrun. Part of the frame was not placed in

memory because the system bus did not keep up

with incoming data.

#Out of buffer. Part of the frame was discarded

because of insufficient memory storage space.

#Receive collision. A collision was detected during

reception and the destination address of the in-

coming frame passes 82596 address filtering.

Collisions in the preamble are not counted.

#Length error. A frame not matching the frame

length parameter was detected.

82596DX/SX

290219–12

Figure 13. Receive Frame Area Diagram

290219–13

Figure 14. Receive Frame Descriptor

82596DX/SX

NETWORK PLANNING AND

MAINTENANCE

To properly plan, operate, and maintain a communi-

cation network, the network management entity

must accumulate information on network behavior.

The 82596 provides a rich set of network-wide diag-

nostics that can serve as the basis for a network

management entity.

Information on network activity is provided in the

status of each frame transmitted. The 82596 reports

the following activity indicators after each frame.

#Number of collisions. The number of collisions

the 82596 experienced while attempting to trans-

mit the frame.

#Deferred transmission. During the first transmis-

sion attempt the 82596 had to defer to traffic on

the link.

The 82596 updates its 32-bit statistical counters af-

ter each received frame that both passes address

filtering and is longer than the Minimum Frame

Length configuration parameter. The 82596 reports

the following statistics.

#CRC errors. The number of well-aligned frames

that experienced a CRC error.

#Alignment errors. The number of misaligned

frames that experienced a CRC error.

#No resources. The number of frames that were

discarded because of insufficient resources for

reception.

#Overrun errors. The number of frames that were

not completely stored in memory because the

system bus did not keep up with incoming data.

#Receive Collision counter. The number of colli-

sions detected during receive. Collisions occur-

ring before the minimum frame length will be

counted as short frames. Collisions in the pream-

ble will not be counted at all.

#Short Frame counter. The number of frames that

were discarded because they were shorter than

the configured minimum frame length.

Once again, these counters are not updated until the

82596 decodes a destination address match.

The 82596 can be configured to Promiscuous mode.

In this mode it captures all frames transmitted on the

network without checking the Destination Address.

This is useful when implementing a monitoring sta-

tion to capture all frames for analysis.

A useful method of capturing frame headers is to

use the Simplified memory mode, configure the

82596 to Save Bad Frames, and configure the

82596 to Promiscuous mode with space in the RFD

allocated for specific number of receive data bytes.

The 82596 will receive all frames and put them in the

RFD. Frames that exceed the available space in the

RFD will be truncated, the status will be updated,

and the 82596 will retrieve the next RFD. This allows

the user to capture the initial data bytes of each

frame (for instance, the header) and discard the re-

mainder of the frame.

The 82596 also has a monitor mode for network

analysis. During normal operation the receive func-

tion enables the 82596 to receive frames which pass

address filtering. These frames must have the Start

of Frame Delimiter (SFD) field and must be longer

than the absolute minimum frame length of 5 bytes

(6 bytes in case of Multicast address filtering). Con-

tents and status of the received frames are trans-

ferred to memory. The monitor function enables the

82596 to simply evaluate the incoming frames. The

82596 can monitor the frames that pass or do not

pass the address filtering. It can also monitor frames

which do not have the SFD fields. The 82596 can be

configured to only keep statistical information about

monitor frames. Three options are available in the

Monitor mode. These modes are selectable by the

two monitor mode configuration bits available in the

configuration command.

When the first option is selected, the 82596 receives

good frames that pass address filtering and trans-

fers them to memory while monitoring frames that

do not pass address filtering or are shorter than the

minimum frame size (these frames are not trans-

ferred to memory). When this option is used the

82596 updates six counters: CRC errors, alignment

errors, no resource errors, overrun errors, short

frames, and total good frames received.

When the second option is selected, the receive

function is completely disabled. The 82596 monitors

only those frames that pass address filterings and

meet the minimum frame length requirement. When

this option is used the 82596 updates six counters:

CRC errors, alignment errors, total frames (good and

bad), short frames, collisions detected, and total

good frames.

When the third option is selected, the receive func-

tion is completely disabled. The 82596 monitors all

frames, including frames that do not have a Start

Frame Delimiter. When this option is used the 82596

updates six counter (CRC errors, alignment errors,

total frames (good and bad), short frames, collisions

detected, and total good frames.

82596DX/SX

STATION DIAGNOSTICS

AND SELF-TEST

The 82596 provides a large set of diagnostic and

network management functions. These include inter-

nal and external loopback and time domain reflec-

tometry for locating fault points in the network cable.

The 82596 ensures software reliability by dumping

the contents of the 82596 internal registers into sys-

tem memory. The 82596 has a self-test mode that

enables it to run an internal self-test and place the

results in system memory.

82586 SOFTWARE COMPATIBILITY

The 82596 has a software-compatible state in which

all its memory structures are compatible with the

82586 memory structure. This includes all the Action

Commands, the Receive Frame Area (including the

RFD, Buffer Descriptors, and Data Buffers), the Sys-

tem Control Block, and the initialization procedures.

There are two minor differences between the 82596

in the 82586-Compatible memory structure and the

82586.

#When the internal and external loopback bits in

the Configure command are set to 11 the 82596

is in external loopback and the LPBK pin is acti-

vated; in the 82586 this situation would produce

internal loopback.

#During a Dump command both the 82596 and

82586 dump the same number of bytes; however,

the data format is different.

INITIALIZING THE 82596

A Reset command is issued to the 82596 to prepare

it for normal operation. The 82596 is initialized

through two data structures that are addressed by

two pointers, the System Configuration Pointer

(SCP) and the Intermediate System Configuration

Pointer (ISCP). The initialization procedure begins

when a Channel Attention signal is asserted after

RESET. The 82596 uses the address of the double

word that contains the SCP as a defaultÐ

00FFFFF4h. Before the CA signal is asserted this

default address can be changed to any other avail-

able address by asserting the PORT pin and provid-

ing the desired address over the D31–D4pins of the

address bus. Pins D3–D0must be 0010; i.e., any

alternative address must be aligned to 16 byte

boundaries. All addresses sent to the 82596 must be

word aligned, which means that all pointers and

memory structures must start on an even address

(A0ezero).

SYSTEM CONFIGURATION POINTER

(SCP)

The SCP contains the SYSBUS byte and the loca-

tion of the next structure of the initialization process,

the ISCP. The following parameters are selected in

the SYSBUS.

#The 82596 operation mode.

#The Bus Throttle timer triggering method.

#Lock enabled.

#Interrupt polarity.

#Big Endian 32-bit entity mode.

Byte ordering is determined by the LE/BE pin.

LE/BEe1 selects little endian byte ordering and

LE/BEe0 selects big endian byte ordering.

NOTE:

In the following, X indicates a bit not checked in

82586 mode. This bit must be set to 0 in all other

modes.

82596DX/SX

The following diagram illustrates the format of the SCP.

31 16ODD WORD 15 0EVEN WORD

XXXXXXXX SYSBUS 00000000000000000FFFFF4h

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0FFFFF8h

A31ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀA24 A23 A0ISCP ADDRESS 0FFFFFCh

A31ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀA24 are not checked in 82586 mode.

XÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀX areas are not checked in 82586 mode; they must be 0 in all other modes.

290219–14

ISCP ADDRESSÐ The physical address of the ISCP. In the 82586 mode, bits A31 –A24 are considered to

be zero.

Figure 15. The System Configuration Pointer

Writing the Sysbus

When writing the Sysbus byte it is important to pay attention to the byte order.

#When a Little Endian processor is used, the Sysbus byte is located at byte address 00FFFFF6h (or address

a2 if an alternative SCP address

was programmed).

#When a processor using Big Endian byte ordering is used, the SYSBUS, alternative SCP, and ISCP ad-

dresses will be different.

#The Sysbus byte is located at 00FFFFF7h.

#If an alternative SCP address is programmed, the SYSBUS byte should be at byte address

a1.

82596DX/SX

INTERMEDIATE SYSTEM CONFIGURATION POINTER (ISCP)

The ISCP indicates the location of the System Control Block. Often the SCP is in ROM and the ISCP is in RAM.

The CPU loads the SCB address (or an equivalent data structure) into the ISCP and asserts CA. This Channel

Attention signal causes the 82596 to begin its initialization procedure and to get the SCB address from the

ISCP and SCP. In 82586 and 32-bit Segmented modes the SCP base address is also the base address of all

Command Blocks, Frame Descriptors, and Buffer Descriptors (but not buffers). All these data structures must

reside in one 64-kB segment; however, in Linear mode no such limitation is imposed.

The following diagram illustrates the ISCP format.

ODD WORD EVEN WORD

31 16 15 8 7 0

A15 A0SCB OFFSET BUSY ISCP

A23 A0SCB BASE ADDRESS ISCP a4

x x x x x x x x Ð in 82586 mode

A31 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀA24 Ð in 32-bit segmented mode

BUSY Ð Indicates that the 82596 is being initialized. The CPU sets the ISCP to 01h before it gives

the first CA to the 82596. The ISCP is cleared by the 82596 after the SCB base and offset

are read. Note that the most significant byte of the first word of the ISCP is not modified

when BUSY is cleared.

SCB OFFSETÐ This 16-bit quantity specifies the offset portion of the address of the SCB.

SCB BASE Ð Specifies the base portion of the address of the SCB. The base of SCB is also the base of

all 82596 Command Blocks, Frame Descriptors and Buffer Descriptors. In the 82586

mode, bits A31– A24 are considered to be zero.

Figure 16. The Intermediate System Configuration PointerÐ82586 and 32-Bit Segmented Modes

ODD WORD EVEN WORD

31 16 15 8 7 0

0 0 0 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0 0 0 BUSY ISCP

A31 A0SCB ABSOLUTE ADDRESS ISCP a4

BUSY Ð Indicates that the 82596 is being initialized. The ISCP is set to 01h by the CPU before its

first CA to the 82596. It is cleared by the 82596 after the SCB address is read.

SCB ADDRESSÐ This 32-bit quantity specifies the physical address of the SCB.

Figure 17. The Intermediate System Configuration PointerÐLinear Mode.

INITIALIZATION PROCESS

The CPU sets up the SCP, ISCP, and the SCB structures, and, if desired, an alternative SCP address. It also

sets BUSY to 01h. The 82596 is initialized when a Channel Attention signal follows a Reset signal, causing the

82596 to access the System Configuration Pointer. The sysbus byte, the operational mode, the bus throttle

timer triggering method, the interrupt polarity, and the state of LOCK are read. After reset the bus throttle

82596DX/SX

timers are essentially disabledÐthe T-ON value is infinite, the T-OFF value is zero. After the SCP is read, the

82596 reads the ISCP and saves the SCB address. In 82586 and 32-bit Segmented modes this address is

represented as a base address plus the offset (this base address is also the base address of all the control

blocks). In Linear mode the base address is also an absolute address. The 82596 clears BUSY, sets CX and

CNR to equal 1 in the SCB, clears the SCB command word, sends an interrupt to the CPU, and awaits another

Channel Attention signal. RESET configures the 82596 to its default state before CA is asserted.

CONTROLLING THE 82596DX/SX

The host CPU controls the 82596 with the commands, data structures, and methods described in this section.

The CPU and the 82596 communicate through shared memory structures. The 82596 contains two indepen-

dent units: the Command Unit and the Receive Unit. The Command Unit executes commands from the CPU,

and the Receive Unit handles frame reception. These two units are controlled and monitored by the CPU

through a shared memory structure called the System Control Block (SCB). The CPU and the 82596 use the

CA and INT signals to communicate with the SCB.

82596 CPU ACCESS INTERFACE (PORT)

The 82596 has a CPU access interface that allows the host CPU to do four things.

#Write an alternative System Configuration Pointer address.

#Write an alternative Dump area pointer and perform Dump.

#Execute a software reset.

#Execute a self-test.

The following events initiate the CPU access state.

#Presence of an address on the D31 –D4data bus pins.

#The D3–D0pins are used to select one of the four functions.

#The PORT input pin is asserted, as in a regular write cycle.

NOTE

The SCP Dump and Self-Test addresses must be 16-byte aligned.

The 82596 requires two 16-bit write cycles for a port command. The first write holds the internal machines and

reads the first 16 bits, the second activates the PORT command and reads the second 16 bits.

The PORT Reset is useful when only the 82596 needs to be reset. The CPU must wait for 10-system and 5-se-

rial clocks before issuing another CA to the 82596; this new CA begins a new initialization process.

The Dump function is useful for troubleshooting No Response problems. If the chip is in a No Response state,

the PORT Dump operation can be executed and a PORT Reset can be used to reinitialize the 82596 without

disturbing the rest of the system.

The Self-Test function can be used for board testing; the 82596 will execute a self-test and write the results to

memory.

Table 2. PORT Function Selection

D31 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀD4ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀD0

Function Addresses and Results D3D2D1D0

Reset A31 Don’t Care A4 0 0 0 0

Self-Test A31 Self-Test Results Address A4 0 0 0 1

SCP A31 Alternative SCP Address A4 0 0 1 0

Dump A31 Dump Area Pointer A4 0 0 1 1

82596DX/SX

MEMORY ADDRESSING FORMATS

The 82596 accesses memory by 32-bit addresses. There are two types of 32-bit addresses: linear and seg-

mented. The type of address used depends on the 82596 operating mode and the type of memory structure it

is addressing. The 82596 has three operating modes.

#82586 Mode

#A Linear address is a single 24-bit entity. Address pins A31–A24 are always zero.

#A Segmented address uses a 24-bit base and a 16-bit offset.

#32-bit Segmented Mode

#A Linear address is a single 32-bit entity.

#A Segmented address uses a 32-bit base and a 16-bit offset.

NOTE:

In the previous two memory addressing modes, each command header (CB, TBD, RFD, RBD, and SCB)

must wholly reside within one segment. If the 82596 encounters a memory structure that does not follow this

restriction, the 82596 will fetch the next contiguous location in memory (beyond the segment).

#Linear Mode

#A Linear address is a single 32-bit entity.

#There are no Segmented addresses.

Linear addresses are primarily used to address transmit and receive data buffers. In the 82586 and 32-bit

Segmented modes, segmented addresses (base plus offset) are used for all Command Blocks, Buffer Descrip-

tors, Frame Descriptors, and System Control Blocks. When using Segmented addresses, only the offset

portion of the entity being addressed is specified in the block. The base for all offsets is the sameÐthat of the

SCB. See Table A.

LITTLE ENDIAN AND BIG ENDIAN BYTE ORDERING

The 82596 supports both Little Endian and Big Endian byte ordering for its memory structures.

The 82596A1 stepping supports Big Endian byte ordering for word and byte entities. Dword entities are not

supported with 82596A1 Big Endian byte ordering. This results in slightly different 82596 memory structures

for Big Endian operation. These structures are defined in the

32-Bit LAN Components A1 Manual.

82596DX/SX

The 82596 B stepping supports Big Endian byte ordering for dword, word, and byte entities in Linear mode

only. All 82596 B 32-bit address pointers are treated as 32-bit Big Endian entities, however, the SCB absolute

address and statistical counters are treated as two 16-bit Big Endian entities. This 32-bit Big Endian entity

support is configured via bit 7 in the SYSBUS byte.

The 82596 C-step has a New Enhanced Big Endian Mode where in Linear Addressing mode, true 32-bit Big

Endian functionality is achieved. New Enhanced Big Endian Mode is enabled exactly the same as the B-step,

by setting bit 7 of the SYSBUS byte. This mode is software compatible with the big endian mode of the B-step

with one exceptionÐno 32-bit addresses need to be swapped by software in the C-step. In this new mode, the

82596 C-step treats 32-bit address pointers as true 32-bit entities and the SCB absolute address and statistical

counters are still treated as two 16-bit big endian entities. Not setting this mode will configure the 82596 C-step

to be 100% compatible to the A1-step big endian mode.

NOTE:

All 82596 memory entities must be word or dword aligned, except the transmit buffers can be byte aligned

for the 82596 B or C steppings.

An example of a double word entity is a frame descriptor command/status dword, whereas the raw data of the

frame are byte entities. Both 32- and 16-bit buses are supported. When a 16-bit bus is used with Big Endian

memory organization, data lines D15–D0are used. The 82596 has an internal crossover that handles these

swap operations.

COMMAND UNIT (CU)

The Command Unit is the logical unit that executes Action Commands from a list of commands very similar to

a CPU program. A Command Block is associated with each Action Command. The CU is modeled as a logical

machine that takes, at any given time, one of the following states.

#Idle. The CU is not executing a command and is not associated with a CB on the list. This is the initial state.

#Suspended. The CU is not executing a command; however, it is associated with a CB on the list. The

suspend state can only be reached if the CPU forces it through the SCB or sets the suspend bit in the RFD.

#Active. The CU is executing an Action Command and pointing to its CB.

The CPU can affect CU operation in two ways: by issuing a CU Control Command or by setting bits in the

Command word of the Action Command.

When programming the 82596 CU, it is important to consider the asynchronous way the 82596 processes

commands. If a command is issued to the 82596 CU, it may be busy processing other commands. In order to

avoid asynchronous race conditions, the following guidelines are recommended to the 82596 programmer:

#If the CU is already in the Active state, and another command needs to be executed, it is unwise to

immediately issue another CU Start command. If a new command (or list of commands) needs to be

started, first issue a CU Suspend command, wait for the CU to become Suspended, then issue the new CU

Start. This will insure that all commands are processed correctly.

#In general, it is a good idea to make sure any CU command has been accepted and executed before

issuing a new control command to the CU.

82596DX/SX

RECEIVE UNIT (RU)

The Receive Unit is the logical unit that receives frames and stores them in memory. The RU is modeled as a

logical machine that takes, at any given time, one of the following states.

#Idle. The RU has no memory resources and is discarding incoming frames. This is the initial state.

#No Resources. The RU has no memory resources and is discarding incoming frames. This state differs

from Idle in that the RU accumulates statistics on the number of discarded frames.

#Suspended. The RU has memory available for storing frames, but is discarding them. The suspend state

can only be reached if the CPU forces it through the SCB or sets the suspend bit in the RFD.

#Ready. The RU has memory available and is storing incoming frames.

The CPU can affect RU operation in three ways: by issuing a RU Control Command, by setting bits in the

Frame Descriptor Command word of the frame being received, or by setting the EL bit of the current buffer’s

Buffer Descriptor.

When programming the 82596 RU, it is important to consider the asynchronous way the 82596 processes

receive frames. If an RU Start is issued to the 82596 RU, it may be busy processing other incoming packets. In

order to avoid asynchronous race conditions, the following guidelines are recommended to the 82596 pro-

grammer:

#If the RU is already in the Ready state, and a new RFA is required to be started, it is unwise to immediately

issue another RU Start command. If the new RFA needs to be started, first issue an RU Suspend com-

mand, wait for the RU to become Suspended, then issue the new RU Start. This will insure that all incoming

frames are received correctly.

#In general, it is a good idea to make sure any RU command has been accepted and executed before

issuing a new control command to the RU.

SYSTEM CONTROL BLOCK (SCB)

The SCB is a memory block that plays a major role in communications between the CPU and the 82596. Such

communications include the following.

#Commands issued by the CPU

#Status reported by the 82596

Control commands are sent to the 82596 by writing them into the SCB and then asserting CA. The 82596

examines the command, performs the required action, and then clears the SCB command word. Control

commands perform the following types of tasks.

#Operation of the Command Unit (CU). The SCB controls the CU by specifying the address of the Command

Block List (CBL) and by starting, suspending, resuming, or aborting execution of CBL commands.

82596DX/SX

#Operation of the Bus Throttle. The SCB controls the Bus Throttle timers by providing them with new values

and sending the Load and Start timer commands. The timers can be operated in both the 32-bit Segmented

and Linear modes.

#Reception of frames by the Receive Unit (RU). The SCB controls the RU by specifying the address of the

Receive Frame Area and by starting, suspending, resuming, or aborting frame reception.

#Acknowledgment of events that cause interrupts.

#Resetting the chip.

The 82596 sends status reports to the CPU via the System Control Block. The SCB contains four types of

status reports.

#The cause of the current interrupts. These interrupts are caused by one or more of the following 82596

events.

#The Command Unit completes an Action Command that has its

bit set.

#The Receive Unit receives a frame.

#The Command Unit becomes inactive.

#The Receive Unit becomes not ready.

#The status of the Command Unit.

#The status of the Receive Unit.

#Status reports from the 82596 regarding reception of corrupted frames.

Events can be cleared only by CPU acknowledgment. If some events are not acknowledged by the ACK field

the Interrupt signal (INT) will be reissued after Channel Attention (CA) is processed. Furthermore, if a new

event occurs while an interrupt is set, the interrupt is temporarily cleared to trigger edge-triggered interrupt

controllers.

The CPU uses the Channel Attention line to cause the 82596 to examine the SCB. This signal is trailing-edge

triggeredÐthe 82596 latches CA on the trailing edge. The latch is cleared by the 82596 before the SCB

control command is read.

31 16ODD WORD 15 0EVEN WORD

ACK X CUC R RUC X X X X STAT 0 CUS 0 RUS 0000SCB

RFA OFFSET CBL OFFSET SCB a4

ALIGNMENT ERRORS CRC ERRORS SCB a8

OVERRUN ERRORS RESOURCE ERRORS SCB a12

Figure 18. SCBÐ82586 Mode

31 16ODD WORD 15 0EVEN WORD

ACK 0 CUC R RUC 0 0 0 0 STAT 0 CUS RUS T 0 0 0 SCB

RFA OFFSET CBL OFFSET SCB a4

CRC ERRORS SCB a8

ALIGNMENT ERRORS SCB a12

RESOURCE ERRORS (*) SCB a16

OVERRUN ERRORS (*) SCB a20

RCVCDT ERRORS (*) SCB a24

SHORT FRAME ERRORS SCB a28

T-ON TIMER T-OFF TIMER SCB a32

*In MONITOR mode these counters change function

Figure 19. SCBÐ32-Bit Segmented Mode

82596DX/SX

31 16ODD WORD 15 0EVEN WORD

ACK 0 CUC R RUC 0 0 0 0 STAT 0 CUS RUS T 0 0 0 SCB

COMMAND BLOCK ADDRESS SCB a4

RECEIVE FRAME AREA ADDRESS SCB a8

CRC ERRORS SCB a12

ALIGNMENT ERRORS SCB a16

RESOURCE ERRORS (*) SCB a20

OVERRUN ERRORS (*) SCB a24

RCVCDT ERRORS (*) SCB a28

SHORT FRAME ERRORS SCB a32

T-ON TIMER T-OFF TIMER SCB a36

*In MONITOR mode these counters change function

Figure 20. SCBÐLinear Mode

Command Word

31 16

ACK 0 CUC R RUC 0 0 0 0 SCB a2

These bits specifiy the action to be performed as a result of a CA. This word is set by the CPU and cleared by

the 82596. Defined bits are:

Bit 31 ACK-CX Ð Acknowledges that the CU completed an Action Command.

Bit 30 ACK-FR Ð Acknowledges that the RU received a frame.

Bit 29 ACK-CNA Ð Acknowledges that the Command Unit became not active.

Bit 28 ACK-RNR Ð Acknowledges that the Receive Unit became not ready.

Bits 24– 26 CUC Ð (3 bits) This field contains the command to the Command Unit. Valid values are:

0 Ð NOP (does not affect current state of the unit).

1 Ð Start execution of the first command on the CBL. If a command is executing,

complete it before starting the new CBL. The beginning of the CBL is in CBL

OFFSET (address).

2 Ð Resume the operation of the Command Unit by executing the next command.

This operation assumes that the Command Unit has been previously sus-

pended.

3 Ð Suspend execution of commands on CBL after current command is complete.

4 Ð Abort current command immediately.

5 Ð Loads the Bus Throttle timers so they will be initialized with their new values

after the active timer (T-ON or T-OFF) reaches Terminal Count. If no timer is

active new values will be loaded immediately. This command is not valid in

82586 mode.

6 Ð Loads and immediately restarts the Bus Throttle timers with their new values.

This command is not valid in 82586 mode.

7 Ð Reserved.

82596DX/SX

Bits 20– 22 RUC Ð (3 bits) This field contains the command to the Receive Unit. Valid values are:

0 Ð NOP (does not alter current state of unit).

1 Ð Start reception of frames. The beginning of the RFA is contained in the RFA

OFFSET (address). If a frame is being received complete reception before

starting.

2 Ð Resume frame reception (only when in suspended state).

3 Ð Suspend frame reception. If a frame is being received complete its reception

before suspending.

4 Ð Abort receiver operation immediately.

5– 7 Ð Reserved.

Bit 23 RESET Ð Reset chip (logically the same as hardware RESET).

Status Word

15 0

STAT 0 CUS 0 RUS 0 0 0 0 SCB

82586 Mode

15 0

STAT 0 CUS RUS T 0 0 0 SCB

32-Bit Segmented and Linear Modes

Indicates the status of the 82596. This word is modified only by the 82596. Defined bits are:

Bit 15 CX Ð The CU finished executing a command with its

(interrupt) bit set.

Bit 14 FR Ð The RU finished receiving a frame.

Bit 13 CNA Ð The Command Unit left the Active state.

Bit 12 RNR Ð The Receive Unit left the Ready state.

Bits 8– 10 CUS Ð (3 bits) This field contains the status of the command unit. Valid values are:

0 Ð Idle

1 Ð Suspended

2 Ð Active

3– 7 Ð Not used

Bits 4– 7 RUS Ð This field contains the status of the receive unit. Valid values are:

0h (0000) Ð Idle

1h (0001) Ð Suspended

2h (0010) Ð No resources. This bit indicates both no resources due to lack of RFDs

in the RDL and no resources due to lack of RBDs in the FBL.

4h (0100) Ð Ready

Ah (1010) Ð No resources due to no more RBDs. (Not in the 82586 mode.)

Ch (1100) Ð No more RBDs (not in the 82586 mode).

No other combinations are allowed.

Bit 3 T Ð Bus Throttle timers loaded (not in 82586 mode).

SCB OFFSET ADDRESSES

CBL Offset (Address)

In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the

first Command Block on the CBL. In Linear mode it is a 32-bit linear address for the first Command Block on

the CBL. It is accessed only if CUC equals Start.

82596DX/SX

RFA Offset (Address)

In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the

Receive Frame Area. In Linear mode it is a 32-bit linear address for the Receive Frame Area. It is accessed

only if RUC equals Start.

SCB STATISTICAL COUNTERS

Statistical Counter Operation

#The CPU is responsible for clearing all error counters before initializing the 82596. The 82596 updates

these counters by reading them, adding 1, and then writing them back to the SCB.

#The counters are wraparound counters. After reaching FFFFFFFFh the counters wrap around to zero.

#The 82596 updates the required counters for each frame. It is possible for more than one counter to be

updated; multiple errors will result in all affected counters being updated.

#The 82596 executes the read-counter/increment/write-counter operation without relinquishing the bus

(locked operation). This is to ensure that no logical contention exists between the 82596 and the CPU due

to both attempting to write to the counters simultaneously. In the dual-port memory configuration the CPU

should not execute any write operation to a counter if LOCK is asserted.

#The counters are 32-bits wide and their behavior is fully compatible with the IEEE 802.3 standard. The

82596 supports all relevant statistics (mandatory, optional, and desired) through the status of the transmit

and receive header and directly through SCB statistics.

CRCERRS

This 32-bit quantity contains the number of aligned frames discarded because of a CRC error. This counter is

updated, if needed, regardless of the RU state.

ALNERRS

This 32-bit quantity contains the number of frames that both are misaligned (i.e., where CRS deasserts on a

nonoctet boundary) and contain a CRC error. The counter is updated, if needed, regardless of the RU state.

SHRTFRM

This 32-bit quantity contains the number of received frames shorter than the minimum frame length.

The last three counters change function in monitor mode.

RSCERRS

This 32-bit quantity contains the number of good frames discarded because there were no resources to

contain them. Frames intended for a host whose RU is in the No Receive Resources state, fall into this

category. This counter is updated only if the RU is in the No Resources state. When in Moniitor mode, this

counter counts the total number of frames.

OVRNERRS

This 32-bit quantity contains the number of frames known to be lost because the local system bus was not

available. If the traffic problem lasts longer than the duration of one frame, the frames that follow the first are

lost without an indicator, and they are not counted. This counter is updated, if needed, regardless of the RU

state.

RCVCDT

This 32-bit counter contains the number of collisions detected during frame reception. This counter will only be

updated if at least 64 bytes of data are received before the collision occurs. If a collision occurs before 64

bytes of data are received, the frame is counted as a short frame. If the collisions occurs in the preamble, no

counters are incremented.

82596DX/SX

ACTION COMMANDS AND OPERATING MODES

This section lists all the Action Commands of the Command Unit Command Block List (CBL). Each command

contains the Command field, the Status and Control fields, the link to the next Action Command, and any

command-specific parameters. There are three basic types of action commands: 82596 Configuration and

Setup, Transmission, and Diagnostics. The following is a list of the actual commands.

#NOP

#Individual Address Setup

#Configure

#MC Setup

#Transmit

#TDR

#Dump

#Diagnose

The 82596 has three addressing modes. In the 82586 mode all the Action Commands look exactly like those

of the 82586.

#82586 Mode. The 82596 software and memory structure is compatible with the 82586.

#32-Bit Segmented Mode. The 82596 can access the entire system memory and use the two new memory

structuresÐSimplified and FlexibleÐwhile still using the segmented approach. This does not require any

significant changes to existing software.

#Linear Mode. The 82596 operates in a flat, linear, 4 gigabyte memory space without segmentation. It can

also use the two new memory structures.

In the 32-bit Segmented mode there are some differences between the 82596 and 82586 action commands,

mainly in programming and activating new 82596 features. Those bits marked ‘‘don’t care’’ in the compatible

mode are not checked; however, we strongly recommend that those bits all be zeroes; this will allow future

enchancements and extensions.

In the Linear mode all of the address offsets become 32-bit address pointers. All new 82596 features are

accessible in this mode, and all bits previously marked ‘‘don’t care’’ must be zeroes.

The Action Commands, and all other 82596 memory structures, must begin on even byte boundaries, i.e., they

must be word aligned.

NOP

This command results in no action by the 82596 except for those performed in the normal command process-

ing. It is used to manipulate the CBL manipulation. The format of the NOP command is shown in Figure 21.

NOPÐ82586 and 32-Bit Segmented Modes

31 16ODD WORD 15 0EVEN WORD

ELS I XXXXXXXXXX000CBOK00000000000000

XXXXXXXXXXXXXXXXA15 A0LINK OFFSET 4

NOPÐLinear Mode

31 16ODD WORD 15 0EVEN WORD

ELSI 0000000000000CBOK00000000000000

A31 A0LINK ADDRESS 4

Figure 21

82596DX/SX

where:

LINK POINTER Ð In the 82586 or 32-bit Segmented modes this is a 16-bit offset to the next Command

Block. In the Linear mode this is the 32-bit address of the next Command Block.

EL Ð If set, this bit indicates that this command block is the last on the CBL.

S Ð If set to one, suspend the CU upon completion of this CB.

I Ð If set to one, the 82596 will generate an interrupt after execution of the command is

complete. If I is not set to one, the CX bit will not be set.

CMD (bits 16– 18) Ð The NOP command. Value: 0h.

Bits 19– 28 Ð Reserved (zero in the 32-bit Segmented and Linear modes).

C Ð This bit indicates the execution status of the command. The CPU initially resets it to zero

when the Command Block is placed on the CBL. Following a command Completion, the

82596 will set it to one.

B Ð This bit indicates that the 82596 is currently executing the NOP command. It is initially

reset to zero by the CPU. The 82596 sets it to one when execution begins and to zero

when execution is completed. This bit is also set when the 82596 prefetches the com-

mand.

NOTE:

The C and B bits are modified in one operation.

OK Ð Indicates that the command was executed without error. If set to one no error occurred

(command executed OK). If zero an error occur.

INDIVIDUAL ADDRESS SETUP

This command is used to load the 82596 with the Individual Address. This address is used by the 82596 for

inserting the Source Address during transmission and recognizing the Destination Address during reception.

After RESET, and prior to Individual Address Setup Command execution, the 82596 assumes the Broadcast

Address is the Individual Address in all aspects, i.e.:

#This will be the Individual Address Match reference.

#This will be the Source Address of a transmitted frame (for AL-LOCe0 mode only).

The format of the Individual Address Setup command is shown in Figure 22.

IA SetupÐ82586 and 32-Bit Segmented Modes

31 16ODD WORD 15 0EVEN WORD

ELS I XXXXXXXXXX001CBOKA0000000000000

INDIVIDUAL ADDRESS 1st byte A15 A0LINK OFFSET 4

6th byte 5th byte 4th byte 3rd byte 8

IA SetupÐLinear Mode

31 16ODD WORD 15 0EVEN WORD

ELSI 0000000000001CBOKA0000000000000

A31 A0LINK ADDRESS 4

4th byte 3rd byte INDIVIDUAL ADDRESS 1st byte 8

6th byte 5th byte C

Figure 22

where:

LINK ADDRESS, Ð As per standard Command Block (see the NOP command for details)

EL, B, C, I, S

A Ð Indicates that the command was abnormally terminated due to CU Abort control

command. If one, then the command was aborted, and if necessary it should be

repeated. If this bit is zero, the command was not aborted.

82596DX/SX

Bits 19– 28 Ð Reserved (zero in the 32-bit Segmented and Linear modes).

CMD (bits 16– 18) Ð The Address Setup command. Value: 1h.

INDIVIDUAL ADDRESS Ð The individual address of the node, 0 to 6 bytes long.

The least significant bit of the Individual Address must be zero for Ethernet (see the Command Structure).

However, no enforcement of 0 is provided by the 82596. Thus, an Individual Address with 1 as its least

significant bit is a valid Individual Address in all aspects.

The default address length is 6 bytes long, as in 802.3. If a different length is used the IA Setup command

should be executed after the Configure command.

CONFIGURE

The Configure command loads the 82596 with its operating parameters. It allows changing some of the

parameters by specifying a byte count less than the maximum number of configuration bytes (11 in the 82586

mode, 14 in the 32-Bit Segmented and Linear modes). The 82596 configuration depends on its mode of

operation.

#In the 82586 mode the maximum number of configuration bytes is 12. Any number larger than 12 will be

reduced to 12 and any number less than 4 will be increased to 4. When configuring the 12th byte (Byte 11

undefined) in 82586 mode this byte should be all ones.

#The additional features of the serial side are disabled in the 82586 mode.

#In both the 32-Bit Segmented and Linear modes there are four additional configuration bytes, which hold

parameters for additional 82596 features. If these parameters are not accessed, the 82596 will follow their

default values.

#For more detailed information refer to the

32-Bit LAN Components User’s Manual.

The format of the Configure command is shown in Figures 23, 24, and 25.

31 16ODD WORD 15 0EVEN WORD

ELS I XXXXXXXXXX010CBOKA0000000000000

Byte 1 Byte 0 A15 A0LINK OFFSET 4

Byte 5 Byte 4 Byte 3 Byte 2 8

Byte 9 Byte 8 Byte 7 Byte 6 12

XXXXXXXXXXXXXXXXXXXXXXXX Byte 10 16

Figure 23. CONFIGUREÐ82586 Mode

31 16ODD WORD 15 0EVEN WORD

ELS I 0000000000010CBOKA0000000000000

Byte 1 Byte 0 A15 A0LINK OFFSET 4

Byte 5 Byte 4 Byte 3 Byte 2 8

Byte 9 Byte 8 Byte 7 Byte 6 12

Byte 13 Byte 12 Byte 11 Byte10 16

Figure 24. CONFIGUREÐ32-Bit Segmented Mode

82596DX/SX

31 16ODD WORD 15 0EVEN WORD

ELS I 0000000000010CBOKA0000000000000

A31 A0LINK ADDRESS 4

Byte 3 Byte 2 Byte 1 Byte 0 8

Byte 7 Byte 6 Byte 5 Byte 4 12

Byte 11 Byte 10 Byte 9 Byte 8 16

XXXXXXXXXXXXXXXX Byte 13 Byte 12 20

Figure 25. CONFIGUREÐLinear Mode

LINK ADDRESS, Ð As per standard Command Block (see the NOP command for details)

EL, B, C, I, S

A Ð Indicates that the command was abnormally terminated due to a CU Abort control com-

mand. If 1, then the command was aborted and if necessary it should be repeated. If this

bit is 0, the command was not aborted.

Bits 19– 28 Ð Reserved (zero in the 32-Bit Segmented and Linear Modes)

CMD (bits 16– 18) Ð The CONFIGURE command. Value: 2h.

The interpretation of the fields follows:

76543210

P X X X BYTE COUNT

BYTE 0

BYTE CNT (Bits 0– 3) Byte Count. Number of bytes, including this one, that hold pa-

rameters to be configured.

PREFETCHED (Bit 7) Enable the 82596 to write the prefetched bit in all prefetch

RBDs.

NOTE:

The P bit is valid only in the new memory structure modes. In 82586 mode this bit is disabled

(i.e., no prefetched mark).

7 0

MONITOR X X FIFO LIMIT

BYTE 1

FIFO Limit (Bits 0– 3) FIFO limit.

MONITORÝ(Bits 6–7) Receive monitor options. If the Byte Count of the configure

command is less than 12 bytes then these Monitor bits are

ignored.

DEFAULT: C8h

7 0

SAVBF10000RESUMEÐRD 0

BYTE 2

RESUMEÐRD (Bit 1) 0Ð The 82596 does not reread the next CB on the list when a CU RESUME

Control Command is issued.

1Ð The 82596 will reread the next CB on the list when a CU RESUME

Control Command is issued. This is available only on the 82596B step-

ping.

SAV BF (Bit 7) 0Ð Received bad frames are not saved in the memory.

1Ð Received bad frames are saved in the memory.

DEFAULT: 40h

82596DX/SX

7 0

LOOP BACK PREAMBLE LENGTH NO SRC ADDRESS LENGTH

MODE ADD INS

BYTE 3

ADR LEN (Bits 0– 2) Address length (any kind).

NO SCR ADD INS (Bit 3) No Source Address Insertion.

In the 82586 this bit is called AL LOC.

PREAM LEN (Bits 4– 5) Preamble length.

LP BCK MODE (Bits 6– 7) Loopback mode.

DEFAULT: 26h

7 0

BOF METD EXPONENTIAL PRIORITY 0 LINEAR PRIORITY

BYTE 4

LIN PRIO (Bits 0– 2) Linear Priority.

EXP PRIO (Bits 4– 6) Exponential Priority.

BOF METD (Bit 7) Exponential Backoff method.

DEFAULT: 00h

7 0

INTER FRAME SPACING

BYTE 5

INTERFRAME SPACING Interframe spacing.

DEFAULT: 60h

7 0

SLOT TIME - LOW

BYTE 6

SLOT TIME (L) Slot time, low byte.

DEFAULT: 00h

7 0

MAXIMUM RETRY NUMBER 0 SLOT TIME - HIGH

BYTE 7

SLOT TIME (H) Slot time, high part.

(Bits 0– 2)

RETRY NUM (Bits 4– 7) Number of transmission retries on collision.

DEFAULT: F2h

82596DX/SX

7 0

PAD BIT CRC16/ NO CRC Tx ON MAN/ BC PRM

STUFF CRC32 INSER NO CRS NRZ DIS MODE

BYTE 8

PRM (Bit 0) Promiscuous mode.

BC DIS (Bit 1) Broadcast disable.

MANCH/NRZ (Bit 2) Manchester or NRZ encoding. See specific timing require-

ments for TxC in Manchester mode.

TONO CRS (Bit 3) Transmit on no CRS.

NOCRC INS (Bit 4) No CRC insertion.

CRC-16/CRC-32 (Bit 5) CRC type.

BIT STF (Bit 6) Bit stuffing.

PAD (Bit 7) Padding.

DEFAULT: 00h

7 0

CDT SRC COLLISION DETECT FILTER CRS SRC CARRIER SENSE FILTER

BYTE 9

CRSF (Bits 0– 2) Carrier Sense filter (length).

CRS SRC (Bit 3) Carrier Sense source.

CDTF (Bits 4– 6) Collision Detect filter (length).

CDT SRC (Bit 7) Collision Detect source.

DEFAULT: 00h

7 0

MINIMUM FRAME LENGTH

BYTE 10

MIN FRAME LEN Minimum frame length.

DEFAULT: 40h

7 0

MONITOR MCÐALL CDBSAC AUTOTX CRCINM LNGFLD PRECRS

BYTE 11

PRECRS (Bit 0) Preamble until Carrier Sense

LNGFLD (Bit 1) Length field. Enables padding at the End-of-Carrier framing

(802.3).

CRCINM (Bit 2) Rx CRC appended to the frame in memory.

AUTOTX (Bit 3) Auto retransmit.

CDBSAC (Bit 4) Collision Detect by source address recognition.

MCÐALL (Bit 5) Enable to receive all MC frames.

MONITOR (Bits 6– 7) Receive monitor options.

DEFAULT: FFH

82596DX/SX

7 0

0FDX000000

BYTE 12

FDX (Bit 6) Enables Full Duplex operation.

DEFAULT: 00h

7 0

DISÐBOF MULTÐIA111111

BYTE 13

MULTÐIA (Bit 6) Multiple individual address.

DISÐBOF (Bit 7) Disable the backoff algorithm.

DEFAULT: 3Fh

82596DX/SX

A reset (hardware or software) configures the 82596 according to the following defaults.

Table 4. Configuration Defaults

Parameter Default Value Units/Meaning

ADDRESS LENGTH **6 Bytes

A/L FIELD LOCATION 0 Located in FD

*AUTO RETRANSMIT 1 Auto Retransmit Enable

BITSTUFFING/EOC 0 EOC

BROADCAST DISABLE 0 Broadcast Reception Enabled

*CDBSAC 1 Disabled

CDT FILTER 0 Bit Times

CDT SRC 0 External Collision Detection

*CRC IN MEMORY 1 CRC Not Transferred to Memory

CRC-16/CRC-32 **0 CRC-32

CRS FILTER 0 0 Bit Times

CRS SRC 0 External CRS

*DISBOF 0 Backoff Enabled

EXT LOOPBACK 0 Disabled

EXPONENTIAL PRIORITY **0 802.3 Algorithm

EXPONENTIAL BACKOFF METHOD **0 802.3 Algorithm

*FULL DUPLEX (FDX) 0 CSMA/CD Protocol (No FDX)

FIFO THRESHOLD 8 TX: 32 Bytes, RX: 64 Bytes

INT LOOPBACK 0 Disabled

INTERFRAME SPACING **96 Bit Times

LINEAR PRIORITY **0 802.3 Algorithm

*LENGTH FIELD 1 Padding Disabled

MIN FRAME LENGTH **64 Bytes

*MC ALL 1 Disabled

*MONITOR 11 Disabled

MANCHESTER/NRZ 0 NRZ

*MULTI IA 0 Disabled

NUMBER OF RETRIES **15 Maximum Number of Retries

NO CRC INSERTION 0 CRC Appended to Frame

PREFETCH BIT IN RBD 0 Disabled (Valid Only in New Modes)

PREAMBLE LENGTH **7 Bytes

*Preamble Until CRS 1 Disabled

PROMISCUOUS MODE 0 Address Filter On

PADDING 0 No Padding

SLOT TIME **512 Bit Times

SAVE BAD FRAME 0 Discards Bad Frames

TRANSMIT ON NO CRS 0 Disabled

NOTES:

1. This configuration setup is compatible with the IEEE 802.3 specification.

2. The Asterisk ‘‘*’’ signifies a new configuration parameter not available in the 82586.

3. The default value of the Auto retransmit configuration parameter is enabled (1).

4. Double Asterisk ‘‘**’’ signifies IEEE 802.3 requirements.

82596DX/SX

MULTICAST-SETUP

This command is used to load the 82596 with the Multicast-IDs that should be accepted. As noted previously,

the filtering done on the Multicast-IDs is not perfect and some unwanted frames may be accepted. This

command resets the current filter and reloads it with the specified Multicast-IDs. The format of the Multicast-

addresses setup command is:

31 16ODD WORD 15 0EVEN WORD

ELS IXXXXXXXXXX011CBOKA000000000000

X X MC COUNT A15 A0LINK OFFSET

4th byte 1st byte

MULTICAST ADDRESSES LIST

Nth byte

Figure 26. MC SetupÐ82586 and 32-Bit Segmented Modes

31 16ODD WORD 15 0EVEN WORD

ELS I 0000000000011CBOKA000000000000

A31 A0LINK ADDRESS

2nd byte 1st byte X X MC COUNT

MULTICAST ADDRESSES LIST

Nth byte

Figure 27. MC SetupÐLinear Mode

where:

LINK ADDRESS, Ð As per standard Command Block (see the NOP command for details)

EL, B, C, I, S

A Ð Indicates that the command was abnormally terminated due to a CU Abort control

command. If one, then the command was aborted and if necessary it should be

repeated. If this bit is zero, the command was not aborted.

Bits 19– 28 Ð Reserved (0 in both the 32-Bit Segmented and Linear Modes).

CMD (bits 16– 18) Ð The MC SETUP command value: 3h.

MC-CNT This 14-bit field indicates the number of bytes in the MC LIST field. The MC CNT

must be a multiple of the ADDR LEN; otherwise, the 82596 reduces the MC CNT to

the nearest ADDR LEN multiple. MC CNTe0 implies resetting the Hash table

which is equivalent to disabling the Multicast filtering mechanism.

MC LIST Ð A list of Multicast Addresses to be accepted by the 82596. The least significant bit

of each MC address must be 1.

NOTE:

The list is sequential; i.e., the most significant byte of an address is immediately followed by the least signifi-

cant byte of the next address.

Ð When the 82596 is configured to recognize multiple Individual Address (Multi-IA),

the MC-Setup command is also used to set up the Hash table for the individual

address.

The least significant bit in the first byte of each IA address must be 0.

82596DX/SX

TRANSMIT

This command is used to transmit a frame of user data onto the serial link. The format of a Transmit command

is as follows.

31 16ODD WORD 15 0EVEN WORD

EL S I X X X X X X X X X X 1 0 0 C B STATUS BITS MAXCOLL 0

A15 A0TBD OFFSET A15 A0LINK OFFSET 4

4th byte DESTINATION ADDRESS 1st byte 8

LENGTH FIELD 6th byte 12

Figure 28. TRANSMITÐ82586 Mode

31 16ODD WORD 15 0EVEN WORD

EL S I 0 0 0 0 0 0 0 0 NC SF 1 0 0 C B STATUS BITS MAXCOLL 0

A15 A0TBD OFFSET A15 A0LINK OFFSET 4

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOF 0 TCB COUNT 8

4th byte DESTINATION ADDRESS 1st byte 12

LENGTH FIELD 6th byte 16

OPTIONAL DATA

Figure 29. TRANSMITÐ32-Bit Segmented Mode

31 16ODD WORD 15 0EVEN WORD

EL S I 0 0 0 0 0 0 0 0 NC SF 1 0 0 C B STATUS BITS MAXCOLL 0

A31 A0LINK ADDRESS 4

A31 A0TRANSMIT BUFFER DESCRIPTOR ADDRESS 8

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOF 0 TCB COUNT 12

4th byte DESTINATION ADDRESS 1st byte 16

20 LENGTH FIELD 6th byte

OPTIONAL DATA

Figure 30. TRANSMITÐLinear Mode

31 16COMMAND WORD

ELSI 00000000NCSF1002

0: No CRC Insertion disable; when the 0: Simplified Mode, all the Tx data is in

configure command is configured to the Transmit Command Block. The

not insert the CRC during Transmit Buffer Descriptor Address

transmission the NC has no effect. field is all 1s.

1: No CRC Insertion enable; when the 1: Flexible Mode. Data is in the TCB and

configure command is configured to in a linked list of TBDs.

insert the CRC during transmission

the CRC will not be inserted when

NC e1.

82596DX/SX

where:

EL, B, C, I, S Ð As per standard Command Block (see the NOP command for details).

OK (Bit 13) Ð Error free completion.

A (Bit 12) Ð Indicates that the command was abnormally terminated due to CU Abort control

command. If 1, then the command was aborted, and if necessary it should be

repeated. If this bit is 0, the command was not aborted.

Bits 19– 28 Ð Reserved (0 in the 32-bit Segmented and Linear modes).

CMD (Bits 16– 18) Ð The transmit command: 4h.

Status Bit 11 Ð Late collision. A late collision (a collision after the slot time is elapsed) is detected.

Status Bit 10 Ð No Carrier Sense signal during transmission. Carrier Sense signal is monitored

from the end of Preamble transmission until the end of the Frame Check Sequence

for TONOCRSe1 (Transmit On No Carrier Sense mode) it indicates that transmis-

sion has been executed despite a lack of CRS. For TONOCRSe0 (Ethernet

mode), this bit also indicates unsuccessful transmission (transmission stopped

when lack of Carrier Sense has been detected).

Status Bit 9 Ð Transmission unsuccessful (stopped) due to Loss of CTS.

Status Bit 8 Ð Transmission unsuccessful (stopped) due to DMA Underrun; i.e., the system did

not supply data for transmission.

Status Bit 7 Ð Transmission Deferred, i.e., transmission was not immediate due to previous link

activity.

Status Bit 6 Ð Heartbeat Indicator, Indicates that after a previously performed transmission, and

before the most recently performed transmission, (Interframe Spacing) the CDT

signal was monitored as active. This indicates that the Ethernet Transceiver Colli-

sion Detect logic is performing properly. The Heartbeat is monitored during the

Interframe Spacing period.

Status Bit 5 Ð Transmission attempt was stopped because the number of collisions exceeded the

maximum allowable number of retries.

Status Bit 4 Ð 0 (Reserved).

MAX-COL Ð The number of Collisions experienced during this frame. Max Col e0 plus S5 e1

(Bits 3– 0) indicates 16 collisions.

LINK OFFSET Ð As per standard Command Block (see the NOP for details).

TBD POINTER Ð In the 82586 and 32-bit Segmented modes this is the offset of the first Tx Buffer

Descriptor containing the data to be transmitted. In the Linear mode this is the 32-

bit address of the first Tx Buffer Descriptor on the list. If the TBD POINTER is all 1s

it indicates that no TBD is used.

DEST ADDRESS Ð Contains the Destination Address of the frame. The least significant bit (MC) indi-

cates the address type.

MCe0: Individual Address.

MCe1: Multicast or Broadcast Address.

If the Destination Address bits are all 1s this is a Broadcast Address.

LENGTH FIELD Ð The contents of this 2-byte field are user defined. In 802.3 it contains the length of

the data field. It is placed in memory in the same order it is transmitted; i.e., most

significant byte first, least significant byte second.

TCB COUNT Ð This 14-bit counter indicates the number of bytes that will be transmitted from the

Transmit Command Block, starting from the third byte after the TCB COUNT field

(address

a12 in the 32-bit Segmented mode,

a16 in the Linear mode). The

TCB COUNT field can be any number of bytes (including an odd byte), this allows

the user to transmit a frame with a header having an odd number of bytes. The

TCB COUNT field is not used in the 82586 mode.

EOF Bit Ð Indicates that the whole frame is kept in the Transmit Command Block. In the

Simplified memory model it must be always asserted.

82596DX/SX

The interpretation of what is transmitted depends on the No Source Address insertion configuration bit and the

memory model being used.

NOTES

1. The Destination Address and the Length Field are sequential of the Length Field immediately follows the

most significant byte of the Destination Address.

2. In case the 82596 is configured with No Source Address insertion bit equal to 0, the 82596 inserts its

configured Source Address in the transmitted frame.

#In the 82586 mode, or when the Simplified memory model is used, the Destination and Length fields of the

transmitted frame are taken from the Transmit Command Block.

#If the FLEXIBLE memory model is used, the Destination and Length fields of the transmitted frame can be

found either in the TCB or TBD, depending on the TCB COUNT.

3. If the 82596 is configured with the Address/Length Field Location equal to 1, the 82596 does not insert its

configured Source Address in the transmitted frame. The first (2 cAddress Length) a2 bytes of the

transmitted frame are interpreted as Destination Address, Source Address, and Length fields respectively.

The location of the first transmitted byte depends on the operational mode of the 82596:

#In the 82586 mode, it is always the first byte of the first Tx Buffer.

#In both the 32-bit Segmented and Linear modes it depends on the SF bit and TCB COUNT:

Ð In the Simplified memory mode the first transmitted byte is always the third byte after the TCB COUNT

field.

Ð In the Flexible mode, if the TCB COUNT is greater than 0 then it is the third byte after the TCB COUNT

field. If TCB COUNT equals 0 then it is first byte of the first Tx Buffer.

#Transmit frames shorter than six bytes are invalid. The transmission will be aborted (only in 82586 mode)

because of a DMA Underrun.

4. Frames which are aborted during transmission are jammed. Such an interruption of transmission can be

caused by any reason indicated by any of the status bits 8, 9, 10 and 12.

JAMMING RULES

1. Jamming will not start before completion of preamble transmission.

2. Collisions detected during transmission of the last 11 bits will not result in jamming.

The format of a Transmit Buffer Descriptor is:

82586 Mode

31 16ODD WORD 15 013 EVEN WORD

NEXT TBD OFFSET EOF X SIZE (ACT COUNT) 0

XXXXXXXX TRANSMIT BUFFER ADDRESS 4

32-Bit Segmented Mode

31 16ODD WORD 15 013 EVEN WORD

NEXT TBD OFFSET EOF 0 SIZE (ACT COUNT) 0

TRANSMIT BUFFER ADDRESS 4

Linear Mode

31 16ODD WORD 15 013 EVEN WORD

0000000000000000EOF0 SIZE (ACT COUNT) 0

NEXT TBD ADDRESS 4

TRANSMIT BUFFER ADDRESS 8

Figure 31

82596DX/SX

where:

EOF Ð This bit indicates that this TBD is the last one associated with the frame being

transmitted. It is set by the CPU before transmit.

SIZE (ACT COUNT) Ð This 14-bit quantity specifies the number of bytes that hold information for the

current buffer. It is set by the CPU before transmission.

NEXT TBD ADDRESS Ð In the 82586 and 32-bit Segmented modes, it is the offset of the next TBD on the

list. In the Linear mode this is the 32-bit address of the next TBD on the list. It is

meaningless if EOFe1.

BUFFER ADDRESS Ð The starting address of the memory area that contains the data to be sent. In the

82586 mode, this is a 24-bit address (A31– A24 are considered to be zero). In the

32-bit Segmented and Linear modes this is a 32-bit address. This buffer can be

byte aligned for the 82596 B-step.

TDR

This operation activates Time Domain Reflectometry, which is a mechanism to detect open or short circuits on

the link and their distance from the diagnosing station. The TDR command has no parameters. The TDR

transmit sequence was changed, compared to the 82586, to form a regular transmission. The TDR command

is designed to be used statically. Make sure that both the CU and RU are idle before attempting a TDR

command. The TDR bit stream is as follows.

Ð Preamble

Ð Source address

Ð Another Source address (the TDR frame is transmitted back to the sending station,

so DEST ADR eSRC ADR).

Ð Data field containing 7Eh patterns.

Ð Jam Pattern, which is the inverse CRC of the transmitted frame.

Maximum length of the TDR frame is 2048 bits. If the 82596 senses collision while transmitting the TDR frame

it transmits the jam pattern and stops the transmission. The 82596 then triggers an internal timer (STC); the

timer is reset at the beginning of transmission and reset if CRS is returned. The timer measures the time

elapsed from the start of transmission until an echo is returned. The echo is indicated by Collision Detect going

active or a drop in the Carrier Sense signal. The following table lists the possible cases that the 82596 is able

to analyze.

Conditions of TDR as Interpreted by the 82596

Transceiver Type Ethernet Non Ethernet

Condition

Carrier Sense was inactive for 2048-bit-time Short or Open on the NA

periods Transceiver Cable

Carrier Sense signal dropped Short on the Ethernet cable NA

Collision Detect went active Open on the Ethernet cable Open on the Serial Link

The Carrier Sense Signal did not drop or the No Problem No Problem

Collision Detect did not go active within

2048-bit time period

An Ethernet transceiver is defined as one that returns transmitted data on the receive pair and activates the

Carrier Sense Signal while transmitting. A Non-Ethernet Transceiver is defined as one that does not do so.

82596DX/SX

The format of the Time Domain Reflectometer command is:

82586 and 32-Bit Segmented Modes

31 16ODD WORD 15 0EVEN WORD

EL S I X XXXXXXXXX101CBOK0000000000000

LNK XVR ET ET X TIME A15 A0LINK OFFSET

OK PRB OPN SRT (11 bits)

Linear Mode

31 16ODD WORD 15 0EVEN WORD

ELS I 0000000000101CBOK0000000000000

A31 A0LINK ADDRESS

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNK XVR ET ET X TIME

OK PRB OPN SRT (11 bits)

Figure 32. TDR

where:

LINK ADDRESS, Ð As per standard Command Block (see the NOP command for details).

EL, B, C, I, S

A Ð Indicates that the command was abnormally terminated due to CU Abort control

command. If one, then the command was aborted, and if necessary it should be

repeated. If this bit is zero, the command was not aborted.

Bits 19– 28 Ð Reserved (0 in the 32-bit Segmented and Linear Modes).

CMD (Bits 16– 18) Ð The TDR command. Value: 5h.

TIME Ð An 11-bit field that specifies the number of TxC cycles that elapsed before an echo

was observed. No echo is indicated by a reception consisting of ‘‘1s’’ only. Be-

cause the network contains various elements such as transceiver links, transceiv-

ers, Ethernet, repeaters etc., the TIME is not exactly proportional to the problems

distance.

LNK OK (Bit 15) Ð No link problem identified. TIMEe7FFh.

XCVR PRB (Bit 14) Ð Indicates a Transceiver problem. Carrier Sense was inactive for 2048-bit time peri-

od. LNK OKe0. TIMEe7FFh.

ET OPN (Bit 13) Ð The transmission line is not properly terminated. Collision Detect went active and

LNK OKe0.

ET SRT (Bit 12) Ð There is a short circuit on the transmission line. Carrier Sense Signal dropped and

LNK OKe0.

82596DX/SX

DUMP

This command causes the contents of various 82596 registers to be placed in a memory area specified by the

user. It is supplied as a 82596 self-diagnostic tool, and to provide registers of interest to the user. The format

of the DUMP command is:

82586 and 32-Bit Segmented Modes

31 16ODD WORD 15 0EVEN WORD

ELS IXXXXXXXXXX110CBOK0000000000000

A15 A0BUFFER OFFSET A15 A0LINK OFFSET

Linear Mode

31 16ODD WORD 15 0EVEN WORD

ELS IXXXXXXXXXX110CBOK0000000000000

A31 A0LINK ADDRESS

A31 A0BUFFER ADDRESS

Figure 33. Dump

where:

LINK ADDRESS, Ð As per standard Command Block (see the NOP command for details).

EL, B, C, I, S

OK Ð Indicates error free completion.

Bits 19– 28 Ð Reserved (0 in the 32-bit Segmented and Linear Modes).

CMD (Bits 16– 18) Ð The Dump command. Value: 6h.

BUFFER POINTER Ð In the 82586 and 32-bit Segmented modes this is the 16-bit-offset portion of the

dump area address. In the Linear mode this is the 32-bit linear address of the dump

area.

Dump Area Information Format

#The 82596 is not Dump compatible with the 82586 because of the 32-bit internal architecture. In 82586

mode the 82596 will dump the same number of bytes as the 82586. The compatible data will be marked

with an asterisk.

#In 82586 mode the dump area is 170 bytes.

#The dump area format of the 32-bit Segmented and Linear modes is described in Figure 35.

#The size of the dump area of the 32-bit Segmented and Linear modes is 304 bytes.

#When the dump is executed by the Port command an extra word will be appended to the Dump Area. The

extra word is a copy of the Dump Area status word (containing the

C, B,

and

bits). The

and

bits

are set when the 82596 has completed the Port Dump command.

82596DX/SX

1514131211109876543210

DMA CONTROL REGISTER*00

CONFIGURE BYTES 3, 2 02

CONFIGURE BYTES 5, 4 04

CONFIGURE BYTES 7, 6 06

CONFIGURE BYTES 9, 8 08

CONFIGURE BYTES 10 0A

I.A. BYTES 1, 0*0C

I.A. BYTES 3, 2*0E

I.A. BYTES 5, 4*10

LAST T.X. STATUS*12

T.X. CRC BYTES 1, 0*14

T.X. CRC BYTES 3, 2*16

R.X. CRC BYTES 1, 0*18

R.X. CRC BYTES 3, 2*1A

R.X. TEMP MEMORY 1, 0*1C

R.X. TEMP MEMORY 3, 2*1E

R.X. TEMP MEMORY 5, 4*20

LAST RECEIVED STATUS*22

HASH REGISTER BYTES 1, 0*24

HASH REGISTER BYTES 3, 2*26

HASH REGISTER BYTES 5, 4*28

HASH REGISTER BYTES 7, 6*2A

SLOT TIME COUNTER*2C

WAIT TIME COUNTER*2E

MICRO MACHINE** 30

60 BYTES 6A

MICRO MACHINE LFSR** 6C

MICRO MACHINE 6E

FLAG ARRAY .

14 BYTES 7A

QUEUE MEMORY** 7C

CU PORT .

8 BYTES 82

MICRO MACHINE ALU** 84

RESERVED** 86

M.M. TEMP A ROTATE R** 88

M.M. TEMP A** 8A

T.X. DMA BYTE COUNT** 8C

M.M. INPUT PORT ADDRESS** 8E

T.X. DMA ADDRESS** 90

M.M. OUTPUT PORT** 92

R.X. DMA BYTE COUNT** 94

M.M. OUTPUT PORT ADDRESS REGISTER** 96

R.X. DMA ADDRESS** 98

RESERVED** 9A

BUS THROTTLE TIMERS 9C

DIU CONTROL REGISTER** 9E

RESERVED** A0

DMA CONTROL REGISTER** A2

BIU CONTROL REGISTER** A4

M.M. DISPATCHER REGISTER** A6

M.M. STATUS REGISTER** A8

Figure 34. Dump Area FormatÐ82586 Mode

NOTE:

*The 82596 is not Dump compatible

with the 82586 because of the 32-bit

internal architecture. In 82586 mode

the 82596 will dump the same number

of bytes as the 82586. The compati-

ble data will be marked with an aster-

isk.

**These bytes are not user defined,

results may vary from Dump com-

mand to Dump command.

82596DX/SX

31 0

CONFIGURE BYTES 5, 4, 3, 2 00

CONFIGURE BYTES 9, 8, 7, 6 04

CONFIGURE BYTES 13, 12, 11, 10 08

I.A. BYTES 1, 0 X X X X X X X X 0C

I.A. BYTES 5, 2 10

TX CRC BYTES 0, 1 LAST T.X. STATUS 14

RX CRC BYTES 0, 1 TX CRC BYTES 3, 2 18

RX TEMP MEMORY 1, 0 RX CRC BYTES 3, 2 1C

R.X. TEMP MEMORY 5, 2 20

HASH REGISTERS 1, 0 LAST R.X. STATUS 24

HASH REGISTER BYTES 5, 2 28

SLOT TIME COUNTER HASH REGISTERS 7, 6 2C

RECEIVE FRAME LENGTH WAIT-TIME COUNTER 30

MICRO MACHINE** 34

128 BYTES B0

MICRO MACHINE LFSR** B4

MICRO MACHINE** B8

FLAG ARRAY .

28 BYTES D0

M.M. INPUT PORT** D4

16 BYTES E0

MICRO MACHINE ALU** E4

RESERVED** E8

M.M. TEMP A ROTATE R.** EC

M.M. TEMP A** F0

T.X. DMA BYTE COUNT** F4

M.M. INPUT PORT ADDRESS REGISTER** F8

T.X. DMA ADDRESS** FC

M.M. OUTPUT PORT REGISTER** 100

R.X. DMA BYTE COUNT** 104

M.M. OUTPUT PORT ADDRESS REGISTER** 108

R.X. DMA ADDRESS REGISTER** 10C

RESERVED** 110

BUS THROTTLE TIMERS 114

DIU CONTROL REGISTER** 118

RESERVED** 11C

DMA CONTROL REGISTER** 120

BIU CONTROL REGISTER** 124

M.M. DISPATCHER REG.** 128

M.M. STATUS REGISTER** 12C

Figure 35. Dump Area FormatÐLinear and 32-Bit Segmented Mode

NOTE:

The 82596 is not Dump compatible

with the 82586 because of the 32-bit

internal architecture. In 82586 mode

the 82596 will dump the same number

of bytes as the 82586. The compati-

ble data will be marked with an aster-

isk.

**These bytes are not user defined,

results may vary from Dump com-

mand to Dump command.

82596DX/SX

DIAGNOSE

The Diagnose Command triggers an internal self-test procedure that checks internal 82596 hardware, which

includes:

#Exponential Backoff Random Number Generator (Linear Feedback Shift Register).

#Exponential Backoff Timeout Counter.

#Slot Time Period Counter.

#Collision Number Counter.

#Exponential Backoff Shift Register.

#Exponential Backoff Mask Logic.

#Timer Trigger Logic.

This procedure checks the operation of the Backoff block, which resides in the serial side and is not easily

controlled. The Diagnose command is performed in two phases.

The format of the 82596 Diagnose command is:

82586 and 32-Bit Segmented Modes

31 16ODD WORD 15 0EVEN WORD

ELS IXXXXXXXXXX111CBOK0F00000000000

XXXXXXXXXXXXXXXXA15 A0LINK OFFSET

Linear Mode

31 16ODD WORD 15 0EVEN WORD

ELS I 0000000000111CBOK0F00000000000

A31 A0LINK ADDRESS

Figure 36. Diagnose

where:

LINK ADDRESS, Ð As per standard Command Block (see the NOP command for details).

EL, B, C, I, S

Bits 19– 28 Ð Reserved (0 in the 32-bit Segmented and Linear Modes).

CMD (bits 16– 18) Ð The Diagnose command. Value: 7h.

OK (bit 13) Ð Indicates error free completion.

F (bit 11) Ð Indicates that the self-test procedure has failed.

RECEIVE FRAME DESCRIPTOR

Each received frame is described by one Receive Frame Descriptor (see Figure 37). Two new memory

structures are available for the received frames. The structures are available only in the Linear and 32-bit

Segmented modes.

82596DX/SX

290219–15

Figure 37. The Receive Frame Area

Simplified Memory Structure

The first is the Simplified memory structure, the data section of the received frame is part of the RFD and is

located immediately after the Length Field. Receive Buffer Descriptors are not used with the Simplified struc-

ture, it is primarily used to make programming easier. If the length of the data area described in the Size Field

is smaller than the incoming frame, the following happens.

1. The received frame is truncated.

2. The No Resource error counter is updated.

3. If the 82596 is configured to Save Bad Frames the RFD is not reused; otherwise, the same RFD is used to

hold the next received frame, and the only action taken regarding the truncated frame is to update the

counter.

4. The 82596 continues to receive the next frame in the next RFD.

82596DX/SX

Note that this sequence is very useful for monitoring. If the 82596 is configured to Save Bad Frames, to

receive in Promiscuous mode, and to use the Simplified memory structure, any programmed length of received

data can be saved in memory.

The Simplified memory structure is shown in Figure 38.

290219–16

Figure 38. RFA Simplified Memory Structure

Flexible Memory Structure

The second structure is the Flexible memory structure, the data structure of the received frame is stored in

both the RFD and in a linked list of Receive BuffersÐReceive Buffer Descriptors. The received frame is placed

in the RFD as configured in the Size field. Any remaining data is placed in a linked list of RBDs.

The Flexible memory structure is shown in Figure 39.

82596DX/SX

Buffers on the receive side can be different lengths. The 82596 will not place more bytes into a buffer than

indicated in the associated RBD. The 82596 will fetch the next RBD before it is needed. The 82596 will

attempt to receive frames as long as the FBL is not exhausted. If there are no more buffers, the 82596

Receive Unit will enter the No Resources state. Before starting the RU, the CPU must place the FBL pointer in

the RBD pointer field of the first RFD. All remaining RBD pointer fields for subsequent RFDs should be ‘‘1s.’’ If

the Receive Frame Descriptor and the associated Receive Buffers are not reused (e.g., the frame is properly

received or the 82596 is configured to Save Bad Frames), the 82596 writes the address of the next free RBD

to the RBD pointer field of the next RFD.

RECEIVE BUFFER DESCRIPTOR (RBD)

The RBDs are used to store received data in a flexible set of linked buffers. The portion of the frame’s data

field that is outside the RFD is placed in a set of buffers chained by a sequence of RBDs. The RFD points to

the first RBD, and the last RBD is flagged with an EOF bit set to 1. Each buffer in the linked list of buffers

related to a particular frame can be any size up to 214 bytes but must be word aligned (begin on an even

numbered byte). This ensures optimum use of the memory resources while maintaining low overhead. All

buffers in a frame are filled with the received data except for the last, in which the actual count can be smaller

than the allocated buffer space.

290219–17

Figure 39. RFA Flexible Memory Structure

82596DX/SX

31 16ODD WORD 15 0EVEN WORD

ELSXXXXXXXXXXXXXXCBOK0 STATUS BITS 0 000000

A15 A0RBD OFFSET A15 A0LINK OFFSET 4

4th byte DESTINATION ADDRESS 1st byte 8

SOURCE ADDRESS 1st byte 6th byte 12

6th byte 4th byte 16

XXXXXXXXXXXXXXXX LENGTH FIELD 20

Figure 40. Receive Frame DescriptorÐ82586 Mode

31 16ODD WORD 15 0EVEN WORD

ELS0000000000SF000 C BOK STATUS BITS 0

A15 A0RBD OFFSET A15 A0LINK OFFSET 4

0 0 SIZE EOF F ACTUAL COUNT 8

4th byte DESTINATION ADDRESS 1st byte 12

SOURCE ADDRESS 1st byte 6th byte 16

6th byte 4th byte 20

LENGTH FIELD 24

OPTIONAL DATA AREA

Figure 41. Receive Frame DescriptorÐ32-Bit Segmented Mode

31 16ODD WORD 15 0EVEN WORD

ELS0000000000SF000 C BOK STATUS BITS 0

A31 A0LINK ADDRESS 4

A31 A0RECEIVE BUFFER DESCRIPTOR ADDRESS 8

0 0 SIZE EOF F ACTUAL COUNT 12

4th byte DESTINATION ADDRESS 1st byte 16

SOURCE ADDRESS 1st byte 6th byte 20

6th byte 4th byte 24

LENGTH FIELD 28

OPTIONAL DATA AREA

Figure 42. Receive Frame DescriptorÐLinear Mode

82596DX/SX

where:

EL Ð When set, this bit indicates that this RFD is the last one on the RDL.

S Ð When set, this bit suspends the RU after receiving the frame.

SF Ð This bit selects between the Simplified or the Flexible mode.

0 Ð Simplified mode, all the RX data is in the RFD. RBD ADDRESS field is all

‘‘1s.’’

1 Ð Flexible mode. Data is in the RFD and in a linked list of Receive Buffer De-

scriptors.

C Ð This bit indicates the completion of frame reception. It is set by the 82596.

B Ð This bit indicates that the 82596 is currently receiving this frame, or that the 82596

is ready to receive the frame. It is initially set to 0 by the CPU. The 82596 sets it to

1 when reception set up begins, and to 0 upon completion. The C and B bits are

set during the same operation.

OK (bit 13) Ð Frame received successfully, without errors. RFDs with bit 13 equal to 0 are possi-

ble only if the save bad frames configuration option is selected. Otherwise all

frames with errors will be discarded, although statistics will be collected on them.

STATUS Ð The results of the Receive operation. Defined bits are,

Bit 12: Length error if configured to check length

Bit 11: CRC error in an aligned frame

Bit 10: Alignment error (CRC error in misaligned frame)

Bit 9: Ran out of buffer spaceÐno resources

Bit 8: DMA Overrun failure to acquire the system bus.

Bit 7: Frame too short.

Bit 6: No EOP flag (for Bit stuffing only)

Bit 5: When the SF bit equals zero, and the 82596 is configured to save bad

frames, this bit signals that the received frame was truncated. Otherwise

it is zero.

Bits 2– 4: Zeros

Bit 1: When it is zero, the destination address of the received frame matches

the IA address. When it is 1, the destination address of the received

frame does not match the individual address. For example, a multicast

address or broadcast address will set this bit to a 1.

Bit 0: Receive collision. A collision is detected during reception, and the colli-

sion occurred after the destination address was received.

LINK ADDRESS Ð A 16-bit offset (32-bit address in the Linear mode) to the next Receive Frame

Descriptor. The Link Address of the last frame can be used to form a cyclical list.

RBD POINTER Ð The offset (address in the Linear mode) of the first RBD containing the received

frame data. An RBD pointer of all ones indicates no RBD.

EOF Ð These fields are for the Simplified and Flexible memory models. They are exactly

F the same as the respective fields in the Receive Buffer Descriptor. See the next

section for detailed explanation of their functions.

SIZE

ACT COUNT

MC Ð Multicast bit.

ÐDESTINATION The contents of the destination address of the receive frame. The field is 0 to 6

ADDRESS bytes long.

SOURCE ADDRESS Ð The contents of the Source Address field of the received frame. It is 0 to 6 bytes

long.

82596DX/SX

LENGTH FIELD Ð The contents of this 2-byte field are user defined. In 802.3 it contains the length of

the data field. It is placed in memory in the same order it is received, i.e., most

significant byte first, least significant byte second.

NOTES

1. The Destination address, Source address and Length fields are packed, i.e., one field immediately follows

the next.

2. The affect of Address/Length Location (No Source Address Insertion) configuration parameter while re-

ceiving is as follows:

Ð 82586 Mode: The Destination address, Source address and Length field are not used, they are placed in

the RX data buffers.

Ð 32-Bit Segmented and Linear Modes: when the Simplified memory model is used, the Destination address,

Source address and Length fields reside in their respective fields in the RFD. When the Flexible memory

strucrture is used the Destination address, Source address, and Length field locations depend on the SIZE

field of the RFD. They can be placed in the RFD, in the RX data buffers, or partially in the RFD and the rest

in the RX data buffers, depending on the SIZE field value.

82586 Mode

31 16ODD WORD 15 0EVEN WORD

A15 A0NEXT RBD OFFSET EOF F ACTUAL COUNT 0

XXXXXXXXA23 A0RECEIVE BUFFER ADDRESS 4

XXXXXXXXXXXXXXXXELX SIZE 8

32-Bit Segmented Mode

31 16ODD WORD 15 0EVEN WORD

A15 A0NEXT RBD OFFSET EOF F ACTUAL COUNT 0

A31 A0RECEIVE BUFFER ADDRESS 4

0000000000000000ELP SIZE 8

Linear Mode

31 16ODD WORD 15 0EVEN WORD

0000000000000000EOFF ACTUAL COUNT 0

A31 A0NEXT RBD ADDRESS 4

A31 A0RECEIVE BUFFER ADDRESS 8

0000000000000000ELP SIZE

Figure 43. Receive Buffer Descriptor

82596DX/SX

where:

EOF Ð Indicates that this is the last buffer related to the frame. It is cleared by the CPU

before starting the RU, and is written by the 82596 at the end of reception of the

frame.

F Ð Indicates that this buffer has already been used. The Actual Count has no meaning

unless the F bit equals one. This bit is cleared by the CPU before starting the RU,

and is set by the 82596 after the associated buffer has been. This bit has the same

meaning as the Complete bit in the RFD and CB.

ACT COUNT Ð This 14-bit quantity indicates the number of meaningful bytes in the buffer. It is

cleared by the CPU before starting the RU, and is written by the 82596 after the

associated buffer has already been used. In general, after the buffer is full, the

Actual Count value equals the size field of the same buffer. For the last buffer of

the frame, Actual Count can be less than the buffer size.

NEXT BD ADDRESS Ð The offset (absolute address in the Linear mode) of the next RBD on the list. It is

meaningless if ELe1.

BUFFER ADDRESS Ð The starting address of the memory area that contains the received data. In the

82586 mode, this is a 24-bit address (with pins A24– A31e0). In the 32-bit Seg-

mented and Linear modes this is a 32-bit address.

EL Ð Indicates that the buffer associated with this RBD is last in the FBL.

P Ð This bit indicates that the 82596 has already prefetched the RBDs and any change

in the RBD data will be ignored. This bit is valid only in the new 82596 memory

modes, and if this feature has been enabled during configure command. The

82596 Prefetches the RBDs in locked cycles; after prefetching the RBD the 82596

performs a write cycle where the P bit is set to one and the rest of the data remains

unchanged. The CPU is responsible for resetting it in all RBDs. The 82596 will not

check this bit before setting it.

SIZE Ð This 14-bit quantity indicates the size, in bytes, of the associated buffer. This quan-

tity must be an even number.

82596DX/SX

PGA PACKAGE THERMAL

SPECIFICATION

Parameter Thermal Resistance

iJC 3§C/W

iJA 24§C/W

ELECTRICAL AND TIMING

CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa

150§C

Case Temperature under Bias ÀÀÀb65§Ctoa

110§C

Supply Voltage

with Respect to VSS ÀÀÀÀÀÀÀÀÀÀÀb0.5V to a6.5V

Voltage on Other Pins ÀÀÀÀÀÀÀb0.5V to VCC a0.5V

D.C. CHARACTERISTICS

TCe0§Ctoa

85§C, VCC e5V g10% CLK2 and LE/BE have MOS levels (see VMIL,V

MIH).

All other signals have TTL levels (see VIL,V

IH,V

OL,V

OH).

Symbol Parameter Min Max Units Notes

VIL Input Low Voltage (TTL) b0.3 a0.8 V

VIH Input High Voltage (TTL) 2.0 VCC a0.3 V

VMIL Input Low Voltage (MOS) b0.3 a0.8 V

VMIH Input High Voltage (MOS) 3.7 VCC a0.3 V

VOL Output Low Voltage (TTL) 0.45 V IOL e4.0 mA

VCIL RxC, TxC Input Low Voltage b0.5 0.6 V

VCIH RxC, TxC Input High Voltage 3.3 VCC a0.5 V

VOH Output High Voltage (TTL) 2.4 V IOH e0.9mA–1 mA

ILI Input Leakage Current g15 mA0

IN sVCC

ILO Output Leakage Current g15 mA 0.45 kVOUT kVCC

CIN Capacitance of Input Buffer 10 pF FC e1 MHz

COUT Capacitance of Input/Output 12 pF FC e1 MHz

Buffer

CCLK CLK Capacitance 20 pF FC e1 MHz

ICC Power Supply 150 mA At 20 MHz

for the 82596SX

ICC Typical e90 mA

ICC Power Supply 200 mA At 25 MHz

ICC Typical e100 mA

ICC Power Supply 300 mA At 33 MHz

ICC Typical e150 mA

82596DX/SX

A.C. CHARACTERISTICS

82596DX C-STEP INPUT/OUTPUT SYSTEM TIMINGS TCe0§Ctoa

85§,V

CC e5V g10%

These timings assume the CLon all outputs is 50 pF unless otherwise specified. CLcan be 20 pF to 120 pF,

however, timings must be derated.

All timing requirements are given in nanoseconds.

Symbol Parameter 25 MHz Notes

Min Max

Operating Frequency 12.5 MHz 25 MHz CLK2/2

T1 CLK2 Period 20 40

T2 CLK2 High 4 3.7V

T3 CLK2 Low 5 0.8V

T4 CLK2 Rise Time Ð 7 0.8V to 3.7V

T5 CLK2 Fall Time Ð 7 3.7V to 0.8V

T13 CA and BREQ Setup Time 7 1, 2, 3

T14 BREQ Hold Time 3 1, 2, 3

T14a CA Hold Time 5 1, 2, 3

T26 CA and BREQ, PORT Pulse Width 4 T1 3

T25 INT Valid Delay 1 26

T6 BEx Valid Delay 3 17

T6b LOCK Valid Delay 3 21

T6c A2–A31 Valid Delay 3 18

T7 BEx, LOCK, and A2– A31 Float Delay 4 30

T8 W/R and ADS Valid Delay 3 21

T9 W/R and ADS Float Delay 4 30

T10 D0– D31 Write Data Valid Delay 3 19

T11 D0– D31 Write Data Float Delay 4 22

T27 D0– D31 CPU PORT Access Setup Time 7 2

T28 D0– D31 CPU PORT Access Hold Time 5 2

T29 PORT Setup Time 7 2

T30 PORT Hold Time 3 2

T17 RDY Setup Time 9 2

T18 RDY Hold Time 3 2

T19 D0– D31 READ Setup Time 7 2

T20 D0– D31 READ Hold Time 5 2

T12 HOLD Valid Delay 3 22

T21 HLDA Setup Time 10 1, 2

T22a HLDA Hold Time 3 1, 2

T23 RESET Setup Time 10 2

T24 RESET Hold Time 3 2

NOTE:

Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A1 or B-Step, contact

your local Intel representative.

82596DX/SX

A.C. CHARACTERISTICS (Continued)

82596DX C-STEP INPUT/OUTPUT SYSTEM TIMINGS TCe0§Ctoa

85§C, VCC e5V g5%

These timings assume the CLon all outputs is 50 pF unless otherwise specified. CLcan be 20 pF to 120 pF,

however, timings must be derated.

All timing requirements are given in nanoseconds.

Symbol Parameter 33 MHz Notes

Min Max

Operating Frequency 12.5 MHz 33 MHz CLK2/2

T1 CLK2 Period 15 40

T2 CLK2 High 4.5 3.7V

T3 CLK2 Low 4.5 0.8V

T4 CLK2 Rise Time Ð 4 3.7V to 0.8V

T5 CLK2 Fall Time Ð 4 0.8V to 3.7V

T13 CA and BREQ Setup Time 7 1, 2, 3

T14 BREQ Hold Time 3 1, 2, 3

T14a CA Hold Time 5 1, 2, 3

T26 CA and BREQ, PORT Pulse Width 4 T1 3

T25 INT Valid Delay 1 20

T6 BEx Valid Delay 3 17

T6b LOCK Valid Delay 3 16

T6c A2–A31 Valid Delay 3 18

T7 BEx, LOCK, and A2– A31 Float Delay 4 20

T8 W/R and ADS Valid Delay 3 16

T9 W/R and ADS Float Delay 4 20

T10 D0– D31 Write Data Valid Delay 3 19

T11 D0– D31 Write Data Float Delay 4 17

T27 D0– D31 CPU PORT Access Setup Time 5 2

T28 D0– D31 CPU PORT Access Hold Time 3 2

T29 PORT Setup Time 7 2

T30 PORT Hold Time 3 2

T17 RDY Setup Time 8 2

T18 RDY Hold Time 3 2

T19 D0– D31 READ Setup Time 5.5 2

T20 D0– D31 READ Hold Time 4 2

T12 HOLD Valid Delay 3 19

T21 HLDA Setup Time 8 1, 2

T22a HLDA Hold Time 3 1, 2

T23 RESET Setup Time 9 2

T24 RESET Hold Time 3 2

NOTE:

Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A1 or B-Step, contact

your local Intel representative.

82596DX/SX

A.C. CHARACTERISTICS (Continued)

82596SX C-STEP INPUT/OUTPUT SYSTEM TIMINGS TCe0§Ctoa

85§C, VCC e5V g10%

These timings assume the CLon all outputs is 50 pF unless otherwise specified. CLcan be 20 pF to 120 pF,

however, timings must be derated.

All timing requirements are given in nanoseconds.

Symbol Parameter 20 MHz Notes

Min Max

Operating Frequency 12.5 MHz 20 MHz CLK2/2

T1 CLK2 Period 25 40

T2 CLK2 High 8 at 2.0V

T3 CLK2 Low 8 at 2.0V

T4 CLK2 Rise Time Ð 8 0.8V to 3.7V

T5 CLK2 Fall Time Ð 8 3.7V to 0.8V

T13 CA and BREQ Setup Time 10 1, 2, 3

T14 BREQ Hold Time 7 1, 2, 3

T14a CA Hold Time 8 1, 2, 3

T26 CA and BREQ, PORT Pulse Width 4 T1 3

T25 INT Valid Delay 1 35

T6 BHE, BLE, LOCK, BON, and A1– A31 3 30

Valid Delay

T7 BHE, BLE, LOCK, BON, and A1– A31 4 30

Float Delay

T8 W/R and ADS Valid Delay 3 26

T9 W/R and ADS Float Delay 4 30

T10 D0– D15 Write Data Valid Delay 3 38

T11 D0– D15 Write Data Float Delay 4 27

T27 D0– D15 CPU PORT Access Setup Time 9 2

T28 D0– D15 CPU PORT Access Hold Time 6 2

T29 PORT Setup Time 10 2

T30 PORT Hold Time 7 2

T17 RDY Setup Time 12 2

T18 RDY Hold Time 4 2

T19 D0– D15 READ Setup Time 9 2

T20 D0– D15 READ Hold Time 5 2

T12 HOLD Valid Delay 3 28

T21 HLDA Setup Time 15 1, 2

T22a HLDA Hold Time 7 1, 2

T23 RESET Setup Time 12 1, 2

T24 RESET Hold Time 4 1, 2

NOTE:

Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A1 or B-Step, contact

your local Intel representative.

82596DX/SX

A.C. CHARACTERISTICS (Continued)

82596SX C-STEP INPUT/OUTPUT SYSTEM TIMINGS TCe0§Ctoa

85§C, VCC e5V g10%

These timings assume the CLon all outputs is 50 pF unless otherwise specified. CLcan be 20 pF to 120 pF,

however, timings must be derated.

All timing requirements are given in nanoseconds.

Symbol Parameter 16 MHz Notes

Min Max

Operating Frequency 12.5 MHz 16 MHz CLK2/2

T1 CLK2 Period 31 40

T2 CLK2 High 9 2.0V

T3 CLK2 Low 9 2.0V

T4 CLK2 Rise Time Ð 8 0.8V to 3.7V

T5 CLK2 Fall Time Ð 8 3.7V to 0.8V

T13 CA and BREQ Setup Time 11 1, 2, 3

T14 CA and BREQ Hold Time 8 1, 2, 3

T26 CA and BREQ, PORT Pulse Width 4 T1 3

T25 INT Valid Delay 1 40

T6 BHE, BLE, BON, and A1–A31 Valid Delay 3 36

T6b LOCKÝValid Delay 1 33

T7 BHE, BLE, LOCK, BON, and A1–A31 Float Delay 4 40

T8 W/R and ADS Valid Delay 1 33

T9 W/R and ADS Float Delay 4 35

T10 D0–D15 Write Data Valid Delay 3 40

T11 D0–D15 Write Data Float Delay 4 35

T27 D0–D15 CPU PORT Access Setup Time 9 2

T28 D0–D15 CPU PORT Access Hold Time 6 2

T29 PORT Setup Time 11 2

T30 PORT Hold Time 8 2

T17 RDY Setup Time 19 2

T18 RDY Hold Time 6 2

T19 D0–D15 READ Setup Time 9 2

T20 D0–D15 READ Hold Time 6 2

T12 HOLD Valid Delay 2 33

82596DX/SX

A.C. CHARACTERISTICS (Continued)

82596SX C-STEP INPUT/OUTPUT SYSTEM TIMINGS TCe0§Ctoa

85§C, VCC e5V g10% (Continued)

These timings assume the CLon all outputs is 50 pF unless otherwise specified. CLcan be 20 pF to 120 pF,

however, timings must be derated.

All timing requirements are given in nanoseconds.

Symbol Parameter 16 MHz Notes

Min Max

T21 HLDA Setup Time 15 1, 2

T22a HLDA Hold Time 7 1, 2

T23 RESET Setup Time 13 1, 2

T24 RESET Hold Time 4 1, 2

NOTES:

Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A1 or B-Step, contact

your local Intel representative.

1. RESET, HLDA, and CA are internally synchronized. This timing is to guarantee recognition at next clock for RESET,

HLDA, and CA.

2. All set-up, hold, and delay timings are at the maximum frequency specification Fmax, and must be derated according to

the following equation for operation at lower frequencies:

Tderated e(Fmax/Fopr) cT

where:

Tderated eSpecifies the value to derate the specification.

Fmax eMaximum operating frequency.

Fopr eActual operating frequency.

TeSpecification at maximum frequency.

This calculation only provides a rough estimate for derating the frequency. For more detailed information contact your Intel

sales office for the data sheet supplement.

3. CA is internally synchronized; if the setup and hold times are met then CA needs to be only 2 T1. BREQ and PORT are

not internally synchronized. BREQ must meet setup and hold times and need only be 2 T1 wide.

82596DX/SX

TRANSMIT/RECEIVE CLOCK PARAMETERS

Symbol Parameter 20 MHz Notes

Min Max

T36 TxC Cycle 50 1, 3

T38 TxC Rise Time 5 1

T39 TxC Fall Time 5 1

T40 TxC High Time 19 1, 3

T41 TxC Low Time 18 1, 3

T42 TxD Rise Time 10 4

T43 TxD Fall Time 10 4

T44 TxD Transition 20 2, 4

T45 TxC Low to TxD Valid 25 4, 6

T46 TxC Low to TxD Transition 25 2, 4

T47 TxC High to TxD Transition 25 2, 4

T48 TxC Low to TxD High (At End of Transition) 25 4

RTS AND CTS PARAMETERS

T49 TxC Low to RTS Low, 25 5

Time to Activate RTS

T50 CTS Low to TxC Low, CTS Setup Time 20

T51 TxC Low to CTS Invalid, CTS Hold Time 10 7

T52 TxC Low to RTS High 25 5

RECEIVE CLOCK PARAMETERS

T53 RxC Cycle 50 1, 3

T54 RxC Rise Time 5 1

T55 RxC Fall Time 5 1

T56 RxC High Time 19 1

T57 RxC Low Time 18 1

RECEIVED DATA PARAMETERS

T58 RxD Setup Time 20 6

T59 RxD Hold Time 10 6

82596DX/SX

TRANSMIT/RECEIVE CLOCK PARAMETERS (Continued)

Symbol Parameter 20 MHz Notes

Min Max

RECEIVED DATA PARAMETERS (Continued)

T60 RxD Rise Time 10

T61 RxD Fall Time 10

CRS AND CDT PARAMETERS

T62 CDT Low to TxC HIGH 20

External Collision Detect Setup Time

T63 TxC High to CDT Inactive, CDT Hold Time 10

T64 CDT Low to Jam Start 10

T65 CRS Low to TxC High, 20

Carrier Sense Setup Time

T66 TxC High to CRS Inactive, CRS Hold Time 10

T67 CRS High to Jamming Start, 12

(Internal Collision Detect)

T68 Jamming Period 11

T69 CRS High to RxC High, 30

CRS Inactive Setup Time

T70 RxC High to CRS High, 10

CRS Inactive Hold Time

INTERFRAME SPACING PARAMETERS

T71 Interframe Delay 9

EXTERNAL LOOPBACK-PIN PARAMETERS

T72 TxC Low to LPBK Low T36 4

T73 TxC Low to LPBK High T36 4

NOTES:

1. Special MOS levels, VCIL e0.9V and VCIH e3.0V.

2. Manchester only.

3. Manchester. Needs 50% duty cycle.

4. 1 TTL load a50 pF.

5. 1 TTL load a100 pF.

6. NRZ only.

7. Abnormal end of transmissionÐCTS expires before RTS.

8. Normal end to transmission.

9. Programmable value:

T71 eNIFS #T36

where: NIFS ethe IFS configuration value

(if NIFS is less than 12 then NIFS is forced to 12).

10. Programmable value:

T64 e(NCDF #T36) a

#T36

(If the collision occurs after the preamble)

where:

NCDF ethe collision detect filter configuration value, and

e12, 13, 14, or 15

11. T68 e32 #T36

12. Programmable value:

T67 e(NCSF #T36) a

#T36

where: NCSF ethe Carrier Sense Filter configuration value, and

e12, 13, 14, or 15

13. To guarantee recognition on the next clock.

82596DX/SX

82596DX/SX BUS OPERATION

The following figures show thae basic bus cycles for the 82596DX and 82596SX.

For more details refer to the

32-Bit LAN Components Manual.

290219–42

Figure 44. Basic 82596DX Bus Cycles

290219–43

Figure 45. Basic 82596SX Bus Cycles

82596DX/SX

SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS

The measurements should be done at:

#TCe0§C–85§C, VCC e5V g10%, C e50 pF unless otherwise specified.

#A.C. testing inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V for a logic ‘‘0’’.

#Timing measurements are made at 1.5V for both logic ‘‘1’’ and ‘‘0’’.

#Rise and Fall time of inputs and outputs signals are measured between 0.8V and 2.0V respectively unless

otherwise specified.

#All timings are relative to CLK2 crossing the 1.5V level.

#All A.C. parameters are valid only after 100 ms from power up.

290219–18

290219–19

Figure 46. CLK2 Timings

Two types of timing specifications are presented below:

1. Input TimingÐminimum setup and hold times.

2. Output TimingsÐoutput delays and float times from CLK2 rising edge.

Figure 45 defines how the measurements should be done:

290219–20

LEGEND:

Ts eInput Setup Time

Th eInput Hold Time

Tn eMinimum output delay or Mininum float delay

Tx eMaximum output delay or Maximum float delay

Figure 47. Drive Levels and Measurements Points for A.C. Specifications

82596DX/SX

INPUT WAVEFORMS

Ts eT13, T15, T17, T19, T21, T23, T27, T29, T31

Th eT14, T16, T18, T20, T22, T22a, T24, T28, T30, T32

290219–21

Figure 48. CA and BREQ Input Timing

290219–22

Figure 49. INT/INT Output Timing

290219–23

Figure 50. HOLD/HLDA Timings

290219–24

Figure 51. Input Setup and Hold Time

82596DX/SX

290219–25

Figure 52. Output Valid Delay Timing

290219–26

Figure 53. Output Float Delay Timing

290219–27

Figure 54. PORT Setup and Hold Time

82596DX/SX

290219–28

Figure 55. RESET Input Timing

SERIAL A.C. TIMING CHARACTERISTICS

290219–29

Figure 56. Serial Input Clock Timing

290219–30

Figure 57. Transmit Data Waveforms

82596DX/SX

290219–31

Figure 58. Transmit Data Waveforms

290219–32

Figure 59. Receive Data Waveforms (NRZ)

290219–33

Figure 60. Receive Data Waveforms (CRS)

82596DX/SX

OUTLINE DIAGRAMS

132 LEAD CERAMIC PIN GRID ARRAY PACKAGE INTEL TYPE A

290219–36

Family: Ceramic Pin Grid Array Package

Symbol Millimeters Inches

Min Max Notes Min Max Notes

A 3.56 4.57 0.140 0.180

A10.76 1.27 Solid Lid 0.030 0.050 Solid Lid

A22.67 3.43 Solid Lid 0.105 0.135 Solid Lid

A31.14 1.40 0.045 0.055

B 0.43 0.51 0.017 0.020

D 36.45 37.21 1.435 1.465

D132.89 33.15 1.295 1.305

e12.29 2.79 0.090 0.110

L 2.54 3.30 0.100 0.130

N 132 132

S11.27 2.54 0.050 0.100

ISSUE IWS 10/12/88

82596DX/SX

Intel Case Outline Drawings

Plastic Quad Flat Pack (PQFP)

0.025 Inch (0.635mm) Pitch

Symbol Description Min Max Min Max Min Max Min Max Min Max Min Max

N Leadcount 68 84 100 132 164 196

A Package Height 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170

A1 Standoff 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

D, E Terminal Dimension 0.675 0.685 0.775 0.785 0.875 0.885 1.075 1.085 1.275 1.285 1.475 1.485

D1, E1 Package Body 0.547 0.553 0.647 0.653 0.747 0.753 0.947 0.953 1.147 1.153 1.347 1.353

D2, E2 Bumper Distance 0.697 0.703 0.797 0.803 0.897 0.903 1.097 1.103 1.297 1.303 1.497 1.503

D3, E3 Lead Dimension 0.400 REF 0.500 REF 0.600 REF 0.800 REF 1.000 REF 1.200 REF

D4, E4 Foot Radius Location 0.623 0.637 0.723 0.737 0.823 0.837 1.023 1.037 1.223 1.237 1.423 1.437

L1 Foot Length 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

Issue IWS Preliminary 12/12/88 INCH

Symbol Description Min Max Min Max Min Max Min Max Min Max Min Max

N Leadcount 68 84 100 132 164 196

A Package Height 4.06 4.32 4.06 4.32 4.06 4.32 4.06 4.32 4.06 4.32 4.06 4.32

A1 Standoff 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76

D, E Terminal Dimension 17.15 17.40 19.69 19.94 22.23 22.48 27.31 27.56 32.39 32.64 37.47 37.72

D1, E1 Package Body 13.89 14.05 16.43 16.59 18.97 19.13 24.05 24.21 29.13 29.29 34.21 34.37

D2, E2 Bumper Distance 17.70 17.85 20.24 20.39 22.78 22.93 27.86 28.01 32.94 33.09 38.02 38.18

D3, E3 Lead Dimension 10.16 REF 12.70 REF 15.24 REF 20.32 REF 25.40 REF 30.48 REF

D4, E4 Foot Radius Location 15.82 16.17 18.36 18.71 21.25 21.25 25.89 26.33 31.06 31.41 36.14 36.49

L1 Foot Length 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76

Issue IWS Preliminary 12/12/88 mm

82596DX/SX

mm (inch) 290219–37

Figure 61. Principal Dimensions and Datums

mm (inch) 290219–38

Figure 62. Molded Details

mm (inch) 290219–39

Figure 63. Terminal Details

82596DX/SX

290219–40

mm (inch)

Detail J Detail L

Figure 64. Typical Lead

290219–41

mm (inch)

Figure 65. Detail M

REVISION SUMMARY

The following represents the key differences be-

tween version -005 and version -006 of the

82596CA Data Sheet.

1. A description of the 82596DX/SX C-stepping en-

hancements was added and the 82596DX/SX

B-step information was removed.

2. Recommendation to use only one type of buffer

(either Simplified or Flexible) in any given linked

list.

3. Added detailed description regarding operation of

RCVCDT counter.

4. Added New Enhanced Big Endian Mode section.

The New Enhanced Big Endian Mode applies only

to the 82596 C-stepping.

5. Added programming recommendations regarding

RU and CU Start commands. These warn against

Starting the CU while it is Active and Starting the

RU while it is Ready.

6. Emphasized that the TDR command is a static

command and should not be used in an active

network.

7. Improved 82596DX/SX C-step timings were add-

ed for all speeds.