DS2431P - Dallas Semiconductor

1 of 23 REV: 050704

Note: Some revisions of t his device may incorporate deviations from published spec ific ations known as errata. Multiple revisions of any devi ce

may be simultaneously avail abl e through various sales channels. For informati on about device errat a, cli ck here: www.maxim-ic.com/errata.

GENERAL DESCRIPTION

The DS2431 is a 1024-bit, 1-Wire® EEPROM chip

organized as four memory pages of 256 bits each.

Data is written to an 8-byte scratchpad, verified, and

then copied to the EEPROM memory. As a special

feature, the four memory pages can individually be

write protected or put in EPROM-emulation mode,

where bits can only be chang ed from a 1 to a 0 s tate.

The DS2431 communicates over the single-

conductor 1-Wire bus. The communication follows

the standard Dallas Semiconductor 1-Wire protocol.

Each device has its own unalterable and unique 64-

bit ROM registration number that is factory lasered

into the chip. The registration number is used to

address the device in a multidrop 1-Wire net

environment.

APPLICATIONS

Acces sory/PC Board Ident if ic ati on

Medical Sensor Calibration Data Storage

Analog Sensor Calibration Including IEEE-

P1451.4 Smart Sensors

Ink and Toner Print Cartridge Identification

After-Market Management of Consumables

TYPICAL OPERATING CIRCUIT

µC

I/O

DS2431

GND

RPUP

VCC

FEATURES

! 1024 Bits of EEPROM Memory Partitioned into

Four Pages of 256 Bits

! Individual Memory Pages can be Perm anentl y

Write Protected or Put in EPROM-Emulation

Mode ("Write to 0")

! Switchpoint Hysteresis and Filtering to Optimize

Performance in the Presence of Noise

! IEC 1000-4-2 Level 4 ESD Protection (8kV

Contact, 15kV Air)

! Reads and Writes Over a Wide Voltage Range of

2.8V to 5.25V from -40°C to +85°C

! Communicates to Host with a Single Digital

Signal at 15.4kbps or 111kbps Using 1-Wire

Protocol

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS2431 -40°C to 85°C TO-92

DS2431/T&R -40°C to 85°C TO-92, tape & reel

DS2431P -40°C to 85°C TSOC

DS2431P/T&R -40°C to 85°C TSOC, tape & reel

DS2431X -40°C to 85°C CSP, tape & reel

PIN CONFIGURATION

1 2 3

TO-92

TSOC, Top View

TSOC, TO-92 pinout :

Pin 1 ------------- GND

Pin 2 ------------- I/O

All other pins -- NC

CSP, approx. 68 × 68 mil

Top view, bumps not visible

A B

A1 = NC

A2 = I/O

B1 = NC

B2 = GND

DS2431

1024-Bit 1-Wire EEPROM

www.maxim-ic.com

Commands, Reg is ters , and Modes are cap ita li ze d for

clarity.

1-Wire is a registered t rademark of Dall as Semic onductor Corp.

DS2431: 1024- B it, 1-Wire EEPROM

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ABSOLUTE MAXIMUM RATINGS

I/O Voltage to GND -0.5V, +6V

I/O Sink Current 20mA

Operating Temperature Range -40°C to +85°C

Junction Temperature +150°C

Storage Temperature Range -40°C to +85°C

Soldering Temperature See IPC/JEDEC J-STD-020A

Stresses beyond t hose listed under “Absolut e Maximum Ratings” may caus e permanent damage to the device. These are s tress ratings only,

and functional operation of the device at these or any other conditi ons beyond those indicated in the operational sect ions of the specifications is

not implied. Expos ure to the absolut e maximum rating conditions for extended periods may affect device rel i abili ty .

ELECTRICAL CHARACTERISTICS

(VPUP = 2.8V to 5.25V, TA = -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I/O PIN GENERAL DATA

1-Wire Pullup Resistance RPUP (Notes 1, 2) 0.3 2.2 kΩ

Input Capacitance CIO (Notes 3, 4) 100 800 pF

Input Load Current ILI/O pin at VPUP 0.05 2.2 µA

High-to-Low Switching

Threshold VTL (Notes 4, 5, 6) 0.5 4.1 V

Input Low Voltage VIL (Notes 1, 7) 0.3 V

Low-to-High Switching

Threshold VTH (Notes 4, 5, 8) 1.0 4.9 V

Switching Hysteresis VHY (Notes 4, 5, 9) 0.22 1.70 V

Output Low Voltage VOL At 4mA (Note 10) 0.4 V

Standard speed, RPUP = 2.2kΩ5

Overdrive speed, RPUP = 2.2kΩ2

Recovery Time

(Notes 1,11) tREC Overdrive speed, directly prior to reset

pulse; RPUP = 2.2kΩ5µs

Standard speed (Note 12) 0.5 5.0

Rising-Edge Hold-off Time tREH Overdrive speed Not applicable (0) µs

Standard speed 65

Timeslot Duration (Note 1) tSLOT Overdrive speed (Note 13) 9µs

I/O PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE

Standard speed, VPUP > 4.5V 480 640

Standard speed (Note 12) 504 640

Overdrive speed, VPUP > 4.5V 48 80

Reset Low Time (Note 1) tRSTL

Overdrive speed (Note 13) 53 80

µs

Standard speed, VPUP > 4.5V 15 60

Standard speed (Note 13) 15 63

Presence Detect High

Time tPDH Overdrive speed (Note 13) 2 7µs

Standard speed, VPUP > 4.5V 1.1 3.75

Standard speed 1.1 7

Presence Detect Fall Time

(Notes 4, 14) tFPD Overdrive speed 1.1 µs

Standard speed 60 240

Overdrive speed, VPUP > 4.5V 8 24

Presence Detect Low

Time tPDL Overdrive speed (Note 13) 8 26 µs

Standard speed, VPUP > 4.5V 64 75

Standard speed 70 75

Presence Detect Sample

Time (Note 1) tMSP Overdrive speed 8.1 10 µs

DS2431: 1024- B it, 1-Wire EEPROM

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PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I/O PIN, 1-Wire WRITE Standard speed 60 120

Write-0 Low Time (Note 1) tW0L Overdrive speed (Note 13) 716

µs

Standard speed 5 15 - ε

Write-1 Low Time

(Notes 1, 15) tW1L Overdrive speed 1 2 - εµs

I/O PIN, 1-Wire READ Standard speed 5 15 - δ

Read Low Time

(Notes 1, 16) tRL Overdrive speed 1 2 - δµs

Standard speed tRL + δ15

Read Sample Time

(Notes 1, 16) tMSR Overdrive speed tRL + δ2µs

EEPROM

Programming Current IPROG (Note 17) 1 mA

Programming Time tPROG (Note 18) 12.5 ms

At 25°C 200k

Write/Erase Cycles

(Endurance) NCY At 85°C (worst case) 50k ---

Data Retention tDR At 85°C (worst case) 10 years

Note 1: System requirem ent.

Note 2: Maximum allowable pullup res is tance is a function of the number of 1-W ire devices in the system and 1-Wire recovery times. The

specifi ed val ue here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily

loaded systems , an acti ve pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.

Note 3: Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5µs

after VPUP has been applied the parasite capacitance will not affect normal communications.

Note 4: Guaranteed by design, sim ul ation onl y. Not production tested.

Note 5: VTL, VTH, and VHY are a function of the internal suppl y voltage.

Note 6: Voltage below which, during a falling edge on I/O, a logic 0 is detected.

Note 7: The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low.

Note 8: Voltage above which, during a risi ng edge on I/O, a logic 1 is detected.

Note 9: After VTH is crossed duri ng a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic '0'.

Note 10: The I-V characteristic is linear for voltages less than 1V.

Note 11: Applies t o a single DS2431 attac hed to a 1-Wire line.

Note 12: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.

Note 13: Highlight ed num bers are NOT in compliance with legacy 1-Wire product standards. S ee comparis on table bel ow.

Note 14: Interval duri ng the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is

80% of VPUP and the time at which the voltage is 20% of VPUP.

Note 15: ε represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH.

Note 16: δ represents th e time required for t he pullup circuitry to pull the voltage on I/O up from VIL to the input high threshol d of the bus

master.

Note 17: Current drawn from I/ O during the EEPROM programm ing int erval . The pullup circ uit on I/O during the programming interval

should be such that the voltage at I / O is greater than or equal to Vpup(min). If Vpup in the system is close to Vpup(min) then a

low impedance bypass of Rpup which can be activated duri ng program ming may need to be added.

Note 18: Interval begi ns tWiLMIN after the leading negative edge on IO for the last timeslot of the E/S byte for a valid Copy Scratc hpad

sequence. Interval ends once the device's self-tim ed EEPROM programming cycle is complete and the current drawn by the

device has returned from IPROG to IL.

LEGACY VALUES DS2431 VALUES

PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED

MIN MAX MIN MAX MIN MAX MIN MAX

tSLOT (incl. tREC) 61µs (undef.) 7µs (undef.) 65µs1) (undef.) 9µs (undef.)

tRSTL 480µs (undef.) 48µs 80µs 504µs 640µs 53µs 80µs

tPDH 15µs 60µs 2µs 6µs 15µs 63µs 2µs 7µs

tPDL 60µs 240µs 8µs 24µs 60µs 240µs 8µs 26µs

tW0L 60µs 120µs 6µs 16µs 60µs 120µs 7µs 16µs

1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.

PIN DESCRIPTION

NAME FUNCTION

I/O 1-Wire Bus Interface. Open drain, requires external pullup resistor.

GND Ground Reference

N.C. Not Connected

DS2431: 1024- B it, 1-Wire EEPROM

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DESCRIPTION

The DS2431 combines 1024 bits of EEPROM, an 8-byte register/control page with up to 7 user read/write bytes,

and a fully-featured 1-Wire interface in a single chip. Each DS2431 has its own 64-bit ROM registration number

that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. Data is

transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The DS2431

has an addition al mem ory area ca lled the s cratchp ad that ac ts as a buff er when writing to t he main m em ory or the

verified, a copy scratchpad command transfers the data to its final memory location. Applications of the DS2431

include accessory/PC board identification, medical sensor calibration data storage, analog sensor calibration

including IEEE-P1451.4 Smart Sensors, ink and toner print cartridge identification, and after-market management

of consumables.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of the

DS2431. The DS2431 has four main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 32-byte

pages of EE PRO M, and 4) 6 4-bit regist er pa ge. The hierar c h ical s tr uc ture of the 1- Wire protocol is s ho wn i n F ig ure

2. The bus master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3)

Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Sk ip ROM or 7) O verdrive-Matc h ROM. Upon c ompletion of

an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all

subseque nt communic ation occurs at a higher sp eed. The protoco l required for these ROM f unction com mands is

described in Figure 9. After a ROM function command is successfully executed, the memory functions become

accessible and the master may provide any one of the four memory function commands. The protocol for these

memory function commands is described in Figure 7. All data is read and written least significant bit first.

Figure 1. Block Diagram

PARASITE POWER

I/O 64-bit

Lasered ROM

1-Wire

Function Control

64-bit

Scratchpad

Data Memory

4 Pages of

256 bits each

CRC16

Generator

Memory

Function

Control Unit

64 bits

DS2431

DS2431: 1024- B it, 1-Wire EEPROM

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Figure 2. Hierarchical Structure for 1-Wire Protocol

Available

Commands:

DS2 431 Co m m a nd Level: Data Field

Affected:

1-Wire ROM Fun ction

Commands (see Figure 9)

DS2431-specific

Memory Function

Commands (see Figure 7)

Read ROM

Match ROM

Search ROM

Skip ROM

Resume

Overdrive Skip

Overdrive Match

64-bit Reg. #, RC-Flag

RC-Flag

64-bit Reg. #, RC-Flag, OD-Flag

Write Scratchpad

Read Scratchpad

Copy Scratchpad

Read Memor y

64-bit Scra tchpad, Flag s

64-bit Scratchpad

Data Memory, Register Page

64-BIT LASERED ROM

Each DS2 431 conta ins a uniqu e ROM c ode that is 6 4 bits lo ng. The f irst 8 bits are a 1-Wire family code. The next

48 bits are a unique serial number. T he last 8 bits are a CRC (C yclic Redundancy Check) of the first 56 bits. See

Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and

XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X 4 + 1. Ad ditional information abou t th e Da ll as 1-Wire

CRC is available in Application Note 27.

The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a

time is shifted in . After th e 8th bit of the fam ily code has been ent ered, then th e seria l number is entered. After the

last bit of the serial number has been entered, the shif t register c ontains the CRC value. S hifting i n the 8 bits of the

CRC returns the shift register to all 0s.

Figure 3. 64-Bit Lasered ROM

MSB LSB

8-Bit

CRC Code 48-Bit Serial Number 8-Bit Family

Code (2Dh)

MSB LSB MSB LSB MSB LSB

Figure 4. 1-Wire CRC Generator

X0X1X2X3X4X5X6X7X8

Polynomial = X8 + X5 + X4 + 1

1st

STAGE 2nd

STAGE 3rd

STAGE 4th

STAGE 6th

STAGE

5th

STAGE 7th

STAGE 8th

STAGE

INPUT DATA

DS2431: 1024- B it, 1-Wire EEPROM

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Figure 5. Memory Map

ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES

0000h to 001Fh R/(W) Data Memory Page 0

0020h to 003Fh R/(W) Data Memory Page 1

0040h to 005Fh R/(W) Data Memory Page 2

0060h to 007Fh R/(W) Data Memory Page 3

0080h1) R/(W) Protec t ion Control Byte

Page 0 55h: Write Protect P0; AAh: E PROM m ode

P0; 55h or AAh: Write Protect 80h

0081h1) R/(W) Protec t ion Control Byte

Page 1 55h: Write Protect P1; AAh: E PROM m ode

P1; 55h or AAh: Write Protect 81h

0082h1) R/(W) Protec t ion Control Byte

Page 2 55h: Write Protect P2; AAh: E PROM m ode

P2; 55h or AAh: Write Protect 82h

0083h1) R/(W) Protec t ion Control Byte

Page 3 55h: Write Protect P3; AAh: E PROM m ode

P3; 55h or AAh: Write Protect 83h

0084h1) R/(W) Copy Protection B yte 55h or AAh: Copy Protect 008 0:00 8Fh, and

any write-pr otected Pages

0085h R Factory byte. Set at

Factory. AAh:Write Protect 85h, 86h, 87h;

55h: Write Protect 85h, unprotect 86h, 87h

0086h R/(W) User Byte/Manufacturer ID

0087h R/(W) User Byte/Manufacturer ID

0088h to 008Fh N/A Reserved

1) Once progr amm ed to AAh or 55h this address becom es read-onl y. All other codes c an be stored but will n either

write-protect the address nor activate any function.

MEMORY

Data mem or y and regist ers ar e locate d in a linear address space, as s hown i n Figur e 5. T he dat a m em or y and t he

registers have unrestr ic t ed re ad ac c es s. The DS243 1 EE P RO M ar ra y co nsis ts of 18 rows of 8 b ytes each. The fir st

16 rows are divided equally into 4 memory pages (32 bytes each). These 4 pages are the primary data memory.

Each page can be individually set to open (unprotected), write protected, or EPROM mode by setting the

associated protection byte in the register row. The last two rows contain protection registers, and reserved bytes.

The register row consists of 4 protection control bytes, a copy protection byte, the factory byte, and two user

byte/manufacture ID bytes. The manufacturer ID can be a customer-supplied identification code that assists the

application software in identifying the product the DS2431 is associated with. Contact the factory to set up and

functiona lity and should not be use d.

In addition to the m ain EEPROM array, an 8-b yte volatile scratc hpad is inc luded. Writes to the EEPRO M arra y are

a two-step process. First, data is written to the scratchpad, and then copied into the main array. This allows the

user to f irst verif y the data wr itten to scr atchpad prior to cop ying into the main ar ray. The device only suppor ts full

row (8-byte) copy operations. In order for data in the scratchpad to be valid for a copy operation, the address

supplied with a Write Scratchpad must start on a row boundary, and 8 full bytes must be written into the

scratchpad.

DS2431: 1024- B it, 1-Wire EEPROM

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The protection control registers determine how incoming data on a write-scratchpad command is loaded into the

scratchpad. A protection setting of 55h (Write Protect) causes the incoming data to be ingnored and the target

address main memory data to be loaded into the scratchpad. A protection setting of AAh (EPROM Mode) causes

the logical AND of incoming data and target address main memory data to be loaded into the scratchpad. Any

other protection control register setting leaves the associated memory page open for unrestricted write access.

Protection control byte settings of 55h or AAh also write prot ect the protection control byte. The protection-control

byte setting of 55h does not block the copy. This allows write-protected data to be refreshed (i. e., reprogramm ed

with the current data) in the device.

The copy protection byte is used for a higher level of security, and should only be used after all other protection

control b ytes, user b ytes , and write- protected pages are set to their final va lue. If the co py protection byte is set to

55h or Aah, all copy attempts to the register row and user byte row are blocked. In addition, all copy attempts to

write-protected main memory pages (i. e., refresh) are blocked.

ADDRESS REGISTERS AND TRANSFER STATUS

The DS24 31 emplo ys thre e ad dr es s r egis ters : TA1, TA2, a n d E/S ( Fi gur e 6). These regis t er s are c om mon to many

other 1-W ire devices but operate slig htly differentl y wit h the DS2431. Registers T A1 and TA2 m ust be loaded with

the target address to which the data is written or from which data is read. Register E/S is a read-only transfer-

status register, used to verify data integrity with write commands. ES bits E2:E0 are loaded with the incoming

T2:T0 on a write-scratchpad command, and increment on each subsequent data byte. This is in effect a byte-

ending of fset counter withi n the 8-byte scratchpad. Bit 5 of the E/S register, c alled PF, is a lo gic 1 if t he data in the

scratc hpad is not va li d du e to a los s of power or if the m as ter sends l es s b ytes tha n n eed ed t o r eac h t he end of the

scratc hpad. For a valid write to th e scratchpa d, T2:T 0 must be 0 a nd the m aster mus t have sent 8 data b ytes. Bits

3, 4, and 6 have no function; they always read 0. The highest valued bit of the E/S register, called AA or

Authori zation Acc epted, ac ts as a flag to indicate that the d ata store d in th e sc ratchpa d has alread y been co pied t o

the target memory address. Writing data to the scratchpad clears this flag.

Figure 6. Address Registers

Bit #76543210

Target Address (TA1)T7T6T5T4T3T2T1T0

Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8

Ending Address with

Data Status (E/S)

(Read Only) AA 0 PF 0 0E2E1E0

DS2431: 1024- B it, 1-Wire EEPROM

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WRITING WITH VERIFICATION

To write data to the DS2431, the scratchpad has to be used as intermediate storage. First the master issues the

Write Scratchpad command to specify the desired target address, followed by the data to be written to the

scratchpad. Note that Copy Scratchpad commands must be performed on 8-byte boundaries, i. e., the 3 LSBs of

the target address (T 2..T 0) mus t be equal to 000b. If T2..T0 are sent with no n- zero v alu es, the copy function wil l be

blocked. Under certain conditions (see W rite Scratchpad comm and) the master will receive an inverted CRC16 of

the command, address (actual address sent) and data at the end of the Write Scratchpad command sequence.

Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the

comm unication was suc ces sful and proc eed to the Copy Scra tchpa d command. If the m aster c ould not recei ve the

CRC16, it should send the Read Scratchpad command to verify data integrity. As a preamble to the scratchpad

data, the DS2431 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF

flag is s et, dat a d id n ot arr ive corr ectly in the s cr atc hpad or th er e was a l os s of po wer s ince dat a was las t written to

the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the

scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the device did not recognize the

Write command. If everything went correctly, both flags are cleared. Now the master can continue reading and

verifying every data byte. After the master has verified the data, it can send the Copy Scratchpad command, for

example. This command must be followed exactly by the data of the three address registers, TA1, TA2, and E/S.

The master should obtain the contents of these registers by reading the scratchpad.

MEMORY FUNCTION COMMANDS

The Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory of the

DS2431. An exam ple on how to use these f unctions to write t o and read from the device is included at the end of

this document. The comm unic ation bet wee n m as ter and DS2431 t akes place e ith er at re gul ar spee d ( def au lt, O D =

0) or at Overdrive Speed (OD = 1). If not explicitly set into the Overdrive Mode, the DS2431 assumes regular

speed.

WRITE SCRATCHPAD COMMAND [0Fh]

The Write Scratchpad command applies to the data memory, and the writable addresses in the register page. In

order for the scratchpad data to be valid for copying to the array, the user must perform a Write Scratchpad

comm and of 8 bytes starting at a valid row boundar y. The W rite Scratchpad comm and accepts invalid addresses,

and partial rows, but subsequent Copy Scratchpad commands are blocked.

After issuing the W rite Scratchpad command, the master must first provide the 2-byte target address, followed by

the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T2:T0.

The ES bits E2:E0 are loaded with the starting byte offset, and increment with each susequent byte. Effectively,

E2:E0 is the byte offset of the last full byte written to the scratchpad. Only full data bytes are accepted.

When executing the Write Scratchpad command, the CRC generator inside the DS2431 (Figure 13) calculates a

CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the

master. T his CRC is generated using the CRC1 6 polynomial b y first clearing the CRC generator and then shif ting

in the command code (0FH) of the W rite Scratchpad comm and, the Target Addresses (TA1 and T A2), and all the

data bytes. Note that the CRC16 calculation is performed with the actual TA1 and TA2 and data sent by the

master . The m aster may end the W rite Scratc hpad com mand at an y time. Howev er, if th e end of the scratc hpad is

reached (E2:E0 = 111b), the master may send 16 read-time slots and receive the CRC generated by the DS2431.

If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in

mem ory, rather than the data transm itted. Similar ly, if the target address pag e is in EP ROM mode, th e scratchpad

is loaded with the bitwise logical AND of the transmitted data and data already in memory.

DS2431: 1024- B it, 1-Wire EEPROM

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Figure 7-1. Memory Function Flow Chart

0Fh

Write Scratch-

pad ?

Bus Master TX

TA1

(

T7:T0

TA 2

(

T15:T8

)

NTo Figure 7

2nd Part

From Figure 7

2nd Part

Bus Master TX Memory

Function Command

To ROM Functions

Flow Chart

(

ure 9

)

From ROM Functions

Flow Chart

(

ure 9

)

Applies onl y if the

memory area is not

protected.

If write-protected, then

the DS2431 copies the

data byte from the tar-

get address into the SP.

If in EPROM mo de,

then the DS2431 loads

the bitwise logical AND

of the transmitted byte

and the data byte from

the targeted address

into the SP.

Master

TX Reset ?

Master TX Data Byte

To Scratc h

DS2431 sets

Sets PF = 1

Clears AA = 0

Sets E2: E0 = T2:T 0

DS2431

Increments

E2:E0

Master

TX Reset ?

DS2431 TX CRC16

of Command, Address,

Data Bytes a s th e y we r e

sent by the bus master

PF = 0

E2:E0

= 7 ?

Bus Master

RX “1”s N

T2:T0

= 0 ?

DS2431: 1024- B it, 1-Wire EEPROM

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Figure 7-2. Memory Function Flow Chart (continued)

AAh

Read Scratch-

Pad ?

DS2431 sets Scratchpad

te Counter = T2:T0

Bus Master RX

TA1 (T7:T0), TA2 (T15:T8)

and E/S B

Bus Master RX

Data B

te from Scratch

Bus Master RX CRC16

of Command, Address,

E/S Byte, Data Bytes as

sent b

the DS2431

Master

TX Reset ?

Bus Master

RX “1”s N

Master

TX Reset ?

DS2431

Increments

te Counter

Byte Counter

= E2:E0 ?

From Figur e 7

1st Part

To Figure 7

1st Part

To Figure 7

3rd Part

From Figur e 7

3rd Part

DS2431: 1024- B it, 1-Wire EEPROM

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Figure 7-3. Memory Function Flow Chart (continued)

* 1-Wire idle high for power

From Figure 7

2nd Pa rt

To Figure 7

2nd Part

To Figure 7

4th Part

From Figure 7

4th Part

55h

Copy Scratch-

Pad ?

Bus Master TX

TA1 (T7:T0), TA2 (T15:T8)

and E/S B

Bus Master

RX “1”s

Master

TX Reset ?

Auth. Code

Match ?

Copy-

Protected ?

DS2431 copies Scratch-

ad Data to Address

AA = 1

DS2431 TX “0”

Master

TX Reset ?

Master

TX Reset ?

DS2431 TX “1”

Applicable to all R/W

memory locations.

T15:T0

< 0090h ?

PF = 0 ?

DS2431: 1024- B it, 1-Wire EEPROM

12 of 23

Figure 7-4. Memory Function Flow Chart (continued)

F0h

Read Memory ?

Address

< 90h ?

Bus Master TX

TA1 (T7:T0),

TA2

(

T15:T8

)

NDS2431 sets Memory

Address =

(

T15:T0

)

DS2431

Increments

Address

Counter

Bus Master

RX “1”s N

Address

< 8Fh ?

Master

TX Reset ?

Master

TX Reset ?

Bus Master RX

Data Byte from

Memor

Address

From Figure 7

3rd Part

To Figure 7

3rd Part

Bus Master

RX “1”s

Master

TX Reset ?

DS2431: 1024- B it, 1-Wire EEPROM

13 of 23

READ SCRATCHPAD COMMAND [AAh]

The Read Scratchpad com mand allows verif ying the t arget address and the integrity of the scratchpad data. After

issuing the command code, the m aster begins read ing. The f irst two b ytes are the target addr ess. T he next byte is

the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the

master originally sent. This is of particular importance if the target ad dress is within the register page or a page in

either Write Protection or EPROM modes. See the Write Scratchpad description for details. The master should

read throug h the sc ratchpad (E2:E0 – T 2:T0 + 1 bytes) , after which it wi ll rece ive t he inverte d CRC, base d o n da ta

as it was sent by the DS2431. If the master continues reading after the CRC, all data will be logic 1s.

COPY SCRATCHPAD [55h]

The Copy Scratchpad command is used to copy data from the scratchpad to writable memory sections. After

issuing the Copy Scratc hp ad c om mand, the master must provide a 3-byt e aut hor iza ti on p atter n , which s ho ul d ha ve

been obtained by an immediately preceding Read Scratchpad command. This 3-byte pattern must exactly match

the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the target

address is valid, the PF flag is not set, and the target memory is not copy-protected, the AA (Authorization

Accepted) f lag is set and the copy begins. All eight bytes of scratchpad contents are copie d to the target memory

location. The devic e ’s in tern a l da ta trans f er takes 13m s m axim um dur ing whic h th e v olt ag e on the 1-Wire bus m us t

not fall below 2.8V. A pattern of alternating 0s and 1s are transmitted after the data has been copied until the

master issues a reset pulse. If the PF flag is s et or t he ta rget m em ory is copy-prot ec ted, t he c opy will not begin an d

the AA flag will not be set.

READ MEMORY [F0h]

The Read Mem ory command is th e ge ner a l f unctio n to read data fr om the DS2431. Af ter is suin g th e c om mand, the

master must provide the 2-byte target address. After these two bytes, the master reads data beginning from the

target address and may continue until address 008Fh. If the master continues reading, the result will be logic 1s.

The device's internal TA1, TA2, E/S, and scratchpad contents are not affected by a Read Memory command.

1-Wire BUS SYSTEM

The 1-W ire bus is a s ystem that has a single b us m aster and one or mor e slaves. In a ll instances the DS24 31 is a

slave device. The bus master is t ypicall y a microcontroller. The d iscussion of this bus s ystem is broken down into

three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The

1-W ire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on

the falling edge of sync pulses from the bus master.

HARDWARE CONFIGURATION

The 1-W ire bus has only a sin gle lin e by def inition; it is impor tant that eac h devic e on the bus b e able to drive i t at

the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or tri-state

outputs. The 1-Wire port of the DS2431 is open drain with an internal circuit equivalent to that shown in Figure 8.

A multidr op bus co nsists of a 1-Wire bus with m ultiple s laves attac hed. T he DS2431 sup ports bot h a St and ard a nd

Overdrive communication speed of 15.4kbps (max) and 111kbps (max), respectively. Note that legacy 1-Wire

products support a standard communication speed of 16.3kbps and Overdrive of 142kbps. The slightly reduced

rates for the DS2431 are a result of additional recovery times, which in turn were driven by a 1-Wire physical

interface enhancement to improve noise immunity. The value of the pullup resistor primarily depends on the

network size and load conditions. The DS2431 requires a pullup resistor of 2.2kΩ (max) at any speed.

The idle state for th e 1-W ire bus is high. If f or any reason a transac tion needs to be s uspended , the bus MUST be

left in the idle st ate if the transac tion is t o resum e. If this does not occ ur and t he bus is left low for mor e than 16µs

(Overdrive speed) or more than 120µs (standard speed), one or more devices on the bus may be reset.

DS2431: 1024- B it, 1-Wire EEPROM

14 of 23

Figure 8. Hardware Configuration

Open Drain

Port Pin

RX = RECEIVE

TX = TRANSMIT 100 Ω

MOSFET

VPUP

TX TX

RXDATA

RPUP

2.2µA

Max.

BUS MASTER DS2431 1-W ire PORT

TRANSACTION SEQUENCE

The protocol for accessing the DS2431 through the 1-Wire port is as follows:

! Initialization

! ROM Function Command

! Memory Function Command

! Transaction/Data

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a

reset pulse transm itted by the bus m aster followed b y prese nce pulse( s) transm itted b y the slave(s ). The pr esence

pulse lets the bus master know that the DS2431 is on the bus and is ready to operate. For more details, see the

1-Wire Signaling section.

1-Wire ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the

DS2431 su pports. All RO M functio n comm ands are 8 bits lon g. A list of th ese com mands follo ws (r efer to the flo w

chart in Figure 9).

READ ROM [33h]

This comm and allows the bus m as ter to read the DS 243 1’s 8- bit f amily cod e, u ni que 48-bit seri al number, and 8 - bit

CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the

bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND

result). The resultant family code and 48-bit serial number result in a mismatch of the CRC.

MATCH ROM [55h]

The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific

DS2431 on a multidrop bus. Only the DS2431 that exactly matches the 64-bit ROM sequence responds to the

following memory function command. All other slaves wait for a reset pulse. This command can be used with a

single or multiple devices on the bus.

DS2431: 1024- B it, 1-Wire EEPROM

15 of 23

SEARCH ROM [F0h]

W hen a system is initia lly brought u p, the bus m aster m ight not know the num ber of devices o n the 1- W ire bus or

their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a

process of elimination to identify the registration numbers of all slave devices. For each bit of the registration

number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each

slave device participating in the search outputs the true value of its registration number bit. On the second slot,

each sla ve devic e par ticip ating in the se arc h outputs the complem ented v alue of its regis tratio n num ber bi t. On the

third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit

written b y the master stop partic ipating in th e search. If both of the read b its are zero , the m aster knows th at slave

devices exis t with both states of the b it. By cho osing whic h state to write, the bus m aster branches in the r omcode

tree. Af ter one com plete pass , the bus m aster knows the reg istration n umber of a single device. Addit ional pas ses

identif y the regis tration num bers of the rem aining d evices. Ref er to App lication N ote 187: 1-Wir e Search Algor ithm

for a detailed discussion, including an example.

SKIP ROM [CCh]

This command can save time in a single-drop bus system by allowing the bus master to access the memory

functions without pro viding the 64-bit ROM code. If more than one slave is pres ent on the bus and, for ex ample, a

Read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves

transmit simultaneously (open-drain pulldowns produce a wired-AND result).

RESUME [A5h]

To maximize the data throughput in a multidrop environment, the Resume function is available. This function

checks the status of the RC bit and, if it is set, directly transfers control to the Memory functions, similar to a Skip

ROM command. The only way to set the RC bit is t hr oug h suc c ess f ull y exec uting th e Matc h ROM, Sear ch RO M, or

Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the

Resume Command function. Accessing another device on the bus clears the RC bit, preventing two or more

devices from simultaneously responding to the Resume Command function.

OVERDRIVE SKIP ROM [3Ch]

On a single-drop bus this command can save time by allowing the bus master to access the memory functions

without providing the 64-bit ROM code. Unlike the normal Skip ROM comm and, the Overdrive Skip ROM sets th e

DS2431 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive

speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0).

When issued on a multidrop bus, this command sets all Overdrive-supporting devices into Overdrive mode. To

subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued

follo wed by a Match ROM or Search ROM comm and sequence. T his spee ds up the time f or the searc h process. If

mor e than one slave support ing Over dr ive is present on the bus a nd t he Overdri ve Sk i p RO M com mand is f oll owe d

by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain

pulldowns produce a wired-AND result).

OVERDRIVE MATCH ROM [69h]

The Overdrive Match ROM command followed b y a 64-bit ROM sequence transmitted at Overdrive Speed allows

the bus master to address a specific DS2431 on a multidrop bus and to simultaneously set it in Overdrive mode.

Only the DS2431 that exactly matches the 64-bit ROM sequence responds to the subsequent memory function

command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match

command remain in Overdrive mode. All overdrive-capable slaves return to standard speed at the next Reset Pulse

of minim um 480µs duration. T he Overdri ve Match ROM comm and can be used with a sing le or m ultipl e dev ices on

the bus.

DS2431: 1024- B it, 1-Wire EEPROM

16 of 23

Figure 9-1. ROM Functions Flow Chart

From Figure 9

2nd Part

To Memory Func tions

Flow Chart

(

ure 7

)

Master TX Bit 0

Master TX Bit 63

Master TX Bit 1

Bit 63

Match ?

RC = 0

DS2431 TX Bit 0

Master TX Bit 0

DS2431 TX Bit 1

Master TX Bit 1

DS2431 TX Bit 63

Master TX Bit 63

RC = 1

Bit 1

Match ?

Bit 0

Match ? Y

Bit 63

Match ?

RC = 0

RC = 1

Bit 1

Match ?

Bit 0

Match ? Y

RC = 0

DS2431 TX

CRC B

DS2431 TX

Serial Number

(6 Bytes)

DS2431 TX

Family C ode

(1 Byte)

RC = 0

To Figure 9

2nd Part

F0h

Search ROM

Command ?

55h

Match ROM

Command ? N

CCh

Skip ROM

Command ?

YY YY

33h

Read ROM

Command ?

To Figure 9

2nd Part

From Memory Fun ctio ns

Flow Chart

(

ure 7

)

Bus Master TX ROM

Function Command DS2431 TX

Pres en c e Puls e

Reset Pulse ? N

OD = 0

Bus Master TX

Reset Pulse From Fi

ure 9, 2nd Pa r t

DS2431: 1024- B it, 1-Wire EEPROM

17 of 23

Figure 9-2. ROM Functions Flow Chart (continued)

To Figure 9

1st Part

From Fi gure 9

1st Part

From Fi gure 9

1st Part

To Fi

ure 9, 1st Par t

A5h

Resume

Command ?

RC = 1 ?

3Ch

Overdrive

Skip ROM ?

RC = 0 ; OD = 1

Master

TX Reset ? Y

Master

TX Reset ?

Master TX Bit 0

Master TX Bit 63

Master TX Bit 1

Bit 63

Match ?

RC = 0 ; OD = 1

RC = 1

Bit 1

Match ?

Bit 0

Match ?

69h

Overdrive Match

ROM ?

OD = 0

DS2431: 1024- B it, 1-Wire EEPROM

18 of 23

1-Wire SIGNALING

The DS2431 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on

one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-Zero, Write-One, and Read-Data. Except

for the Presence pulse, the bus master initiates all falling edges. The DS2431 can communicate at two different

speeds, standard speed, and Overdrive Speed. If not explicitly set into the Overdrive mode, the DS2431

communicates at standard speed. While in Overdrive Mode the fast timing applies to all waveforms.

To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. To get

from active to id le, the vo ltage nee ds to rise from VILMAX past the threshold VTH. The t ime it takes for the voltage to

make this rise is seen in Figure 10 as 'ε' and its duration depends on the pullup resistor (RPUP) used and the

capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the DS2431 when determining a

logical level, not triggering any events.

Figure 10 sho ws the initia lization s equence requ ired to begi n any comm unication with the DS2431. A Re set Pulse

followed by a Presence Pulse indicates the DS2431 is ready to receive data, given the correct RO M and memory

function c om mand. If the bus mas ter us es sle w-r ate contr o l o n th e falling ed ge, it must pul l do wn the li ne f or tRSTL +

tF to com pens ate f or the edge. A tRSTL durati on of 480µs or lon ger exits t he O verdr ive M ode, retur ning the de vice to

standard speed. If the DS2431 is in Overdrive Mode and tRSTL is no longer than 80µs. the device remains in

Overdrive Mo de.

Figure 10. Initialization Procedure: Reset and Presence Pulse

RESISTOR MASTER DS2431

tRSTL tPDL

tRSTH

tPDH

MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”

VPUP

VIHMASTER

VTH

VTL

VILMAX

tFtREC

tMSP

After the bus mas ter has release d the lin e it goes into rece ive m ode. Now the 1- W ire bus is pulled to VPUP th rough

the pullup resistor, or in case of a DS2482-x00 or DS2480B driver, by active circuitry. W hen the threshold VTH is

cross ed, the DS2 431 wa its f or tPDH and th en tra nsm its a Presenc e Pu lse b y pullin g the l ine l ow for tPDL. T o detect a

presence pulse, the master must test the logical state of the 1-Wire line at tMSP.

The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is expired, the

DS2431 is ready for data communication. In a mixed population network, tRSTH should be extended to minimum

480µs at standard speed and 48µs at Overdrive speed to accommodate other 1-Wire devices.

Read-/Write-Time Slots

Data communication with the DS2431 takes place in time slots, which carry a single bit each. Write-time slots

transport data from bus master to slave. Read-time slots transfer data from slave to master. Figure 11 illustrates

the definitions of the write- and read-time slots.

All comm unic ation begins with the m aster pulling the dat a line low. As the volt age on t he 1-Wire line falls b elo w the

threshold VTL, t he DS2431 s tarts its internal t iming ge nerator th at determ ines whe n the data line is sam pled dur ing

a write-time slot and how long data is valid during a read-time slot.

DS2431: 1024- B it, 1-Wire EEPROM

19 of 23

Master-to-Slave

For a write-one time slot, the voltage on the data line must have crossed the VTH threshold before the write-one

low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH

threshold until the write-zero low time tW0LMIN is expired. For the most reliable communication, the voltage on the

data line s hould n ot exceed VILMAX duri ng the entir e tW0L or tW1L window. After the VTH thresho ld has been cros sed,

the DS2431 needs a recovery time tREC before it is ready for the next time slot.

Figure 11. Read/Write Timing Diagram

Write-One Time Slot

RESISTOR MASTER

VPUP

VIHMASTER

VTH

VTL

VILMAX

0V tFtSLOT

tW1L

Write-Zero Time Slot

RESISTOR MASTER

tREC

VPUP

VIHMASTER

VTH

VTL

VILMAX

0V tFtSLOT

tW0L

Read-Data Time Slot

RESISTOR MASTER DS2431

tREC

VPUP

VIHMASTER

VTH

VTL

VILMAX

Master

Sampling

Window

tFtSLOT

tRL tMSR

DS2431: 1024- B it, 1-Wire EEPROM

20 of 23

Slave-to-Master

A read-data t ime slot be gins like a writ e-on e t ime slot. The volta ge o n th e d ata li ne must rem ain b e lo w VTL until the

read low time tRL is expired. During the tRL window, when responding with a 0, the DS2431 starts pulling the data

line low; its inter nal tim ing generat or determines when this pul ldo wn ends and the volta ge starts rising again . W hen

responding with a 1, the DS2431 does not hold the data line low at all, and the voltage starts rising as soon as tRL is

over.

The s um of tRL + δ (rise tim e) on one side and the interna l timing ge nerator of the DS2431 on the other side define

the master sampling window (tMSRMIN to tMSRMAX) in which the m as ter must per f orm a read f rom the data l ine . For the

most reliable communication, tRL should be as short as permissible, and the master should read close to but no

later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees

sufficient recovery time tREC for the DS2431 to get ready for the next time slot. Note that tREC specified herein

applies only to a single DS2431 attached to a 1-Wire line. For multidevice configurations, tREC needs to be

extended to acc ommodate the addit ional 1-W ire device input capac itance. Alter natively, a n interfac e that perf orms

active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire line drivers can be

used.

IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)

In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire

driver) . 1-W ire network s, therefor e, are suscept ible to noise of various origins . Dependin g on the p hysical s ize an d

topology of the network, reflections from end points and branch points can add up, or cancel each other to som e

extent. Suc h ref lectio ns are visi ble as g litc hes or ringi ng on t he 1-Wire communica tion line. Noise c oupled on to t he

1-W ire line from external sourc es can als o res ult in s igna l gl itchi ng. A g li tc h d uring th e r isin g e dge of a tim e s lot can

cause a slave devic e to lose s ynchronizati on with the m ast er and, co nsequent ly, res ult i n a sear ch ROM c omm and

coming to a dead end or cause a device-specific function command to abort. For better performance in network

applicat ions, the DS 2431 uses a ne w 1-Wire front end, which m akes it les s sens itive to no ise an d als o reduc es th e

magnitude of noise injected by the slave device itself.

The 1-Wire front end of the DS2431 differs from traditional slave devices in four characteristics.

1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line

impedance than a digitally switched transistor, converting the high-frequency ringing known from traditional

devices into a smoother low-bandwidth transition. The slew-rate control is specified by the parameter tFPD,

which has different values for standard and Overdrive speed.

2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot.

This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed.

3) There is a hysteresis at the low-to-high switching threshold VTH. If a neg at iv e g litc h c ros s es VTH but do es not go

below VTH - VHY, it will not be recognized (Figure 12, Case A). The hysteresis is effective at any 1-Wire speed.

4) There is a tim e wind ow sp ecif ied b y the risin g edge ho ld-off tim e tREH durin g which g litches are ig nor ed, e ven if

they extend below VTH - VHY threshold (Figure 12, Case B, tGL < tREH). Deep voltage droops or glitches that

appear l ate after c rossing the VTH thr eshold and extend b eyond the tREH window cannot be filtered out and are

taken as the beginning of a new time slot (Figure 12, Case C, tGL ≥ tREH).

Only devices that have the parameters tFPD, VHY, and tREH specified in their electrical characteristics use the

improved 1-Wire front end.

Figure 12. Noise Suppression Scheme

VPUP

VTH

VHY

tREH

tGL

tREH

tGL

Case A Case CCase B

DS2431: 1024- B it, 1-Wire EEPROM

21 of 23

CRC GENERATION

With the DS2431 there are two different types of CRCs. One CRC is an 8-bit type and is stored in the most

significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit

ROM and c om pare it to th e val ue store d with in the D S2431 to deter m ine if the ROM data has bee n r eceive d er ror-

free. The equivalent polynomial function of this CRC is X8 + X5 + X4 + 1. This 8-bit CRC is received in the true

(noninverted) form. It is computed at the factory and lasered into the ROM.

The other CRC is a 16- bit type , generat ed accor ding to the standardi zed CRC 16-polynom ial f unction x16 + x 15 + x2

+ 1. This CRC is used for fast verification of a data transfer when writing to or reading from the scratchpad. In

contrast to the 8-bit CRC, the 16-bit CRC is always comm unicated in the inverte d f orm . A CRC gen erator insi de t he

DS2431 chip (Figure 13) calculates a new 16-bit CRC, as shown in the command flow chart (Figure 7). The bus

master compares the CRC value read f rom the devic e to the one it calculates from the data, and decides wheth er

to continue with an operation or to reread the portion of the data with the CRC error.

W ith the Write Sc ratchpad c om mand, the CRC is gen erate d by first clear ing the CRC gen erator and the n shifting in

the command code, the Target Addresses TA1 and TA2, and all the data bytes as they were sent by the bus

master. The DS2431 transmits this CRC only i f E2:E0 = 111b.

W ith the Read Scratchpad command, the CRC is gen erate d by first clearing t he CRC g ener ator a nd then shifting in

the Com m and code, the T arget A ddress es T A1 and T A2, the E/S b yte, and the s cratchp ad data as the y were se nt

by the DS2431. The DS2431 transmits this CRC only if the reading continues through the end of the scratchpad.

For more information on generating CRC values, refer to Application Note 27.

Figure 13. CRC-16 Hardware Desc ription and Polynomial

Pol

nomi al = X16 + X15 + X2 + 1

X0X1X2X3X4X5X6X7

X8X9X10 X11 X12 X13 X14 X15 X16

1st

STAGE 2nd

STAGE 3rd

STAGE 4th

STAGE 6th

STAGE

5th

STAGE 7th

STAGE 8th

STAGE

9th

STAGE 10th

STAGE 11th

STAGE 12th

STAGE 13th

STAGE 14th

STAGE 15th

STAGE 16th

STAGE

INPUT DATA

CRC

OUTPUT

COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—COLOR CODES

Master to slave Slave to master Programming

DS2431: 1024- B it, 1-Wire EEPROM

22 of 23

COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—LEGEND

SYMBOL DESCRIPTION

RST 1-Wire Reset Pulse generated by master.

PD 1-Wire Presence Pulse generated by slave.

Select Command and data to satisfy the ROM function protocol.

WS Command "Write Scratchpad".

RS Command "Read Scratchpad".

CPS Command "Copy Scratchpad".

RM Command "Read Memory".

TA Target Address TA1, TA2.

TA-E/S Target Address TA1, TA2 with E/S byte.

<8 – T2:T0 bytes> Transfer of as many bytes as needed to reach the end of the scratchpad for a given

target address .

<data to EOM> Transfer of as many data bytes as are needed to reach the end of the memory.

CRC16\ Transfer of an inverted CRC16.

FF loop Indefinite loop where the master reads FF bytes.

AA loop Indefinite loop where the master reads AA bytes.

Programming Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.

WRITE SCRATCHP AD (CANNOT F AIL)

RST PD Select WS TA <8 – T2:T0 bytes> CRC16\ FF loop

READ SCRATCHP AD (CANNOT F AIL)

RST PD Select RS TA-E/S <8 – T2:T0 bytes> CRC16\ FF loop

COPY SCRATCHPAD (SUCCESS)

RST PD Select CPS TA-E/S Programming AA loop

COPY SCRATCHPAD (INVALID ADDRESS OR PF = 1 OR COPY PROTECTED)

RST PD Select CPS TA-E/S FF loop

READ MEMORY (SUCCESS)

RST PD Select RM TA <data to EOM> FF loop

READ MEMORY (INVALID ADDRESS)

RST PD Select RM TA FF loop

DS2431: 1024- B it, 1-Wire EEPROM

23 of 23

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied

in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the

right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

MAXIM i s a registered tradem ark of Maxim Integrated Products, Inc. DALLAS is a registered trademark of Dallas Semiconductor Corporation.

MEMORY FUNCTION EXAMPLE

Write to the first 8 bytes of memory page 1. Read the entire memory.

With only a single DS2431 connected to the bus master, the communication looks like this:

MASTER MODE DATA (LSB FIRST) COMMENTS

TX (Reset) Reset pulse

RX (Presenc e) Presence puls e

TX CCh Issue “Skip ROM” command

TX 0Fh Issue “Write scratchpad” command

TX 20h TA1, beginning offset=20h

TX 00h TA2, address=0020h

TX <8 data bytes> Write 8 bytes of data to scratchpad

RX <2 bytes CRC16\> Read CRC to check for data integrity

TX (Reset) Reset pulse

RX (Presenc e) Presence puls e

TX CCh Issue “Skip ROM” command

TX AAh Issue “Read scratchpad” command

RX 20h Read TA1, beginning offset=20h

RX 00h Read TA2, address=0020h

RX 07h Read E/S, ending offset=111b, AA, PF = 0

RX <8 data bytes> Read scratchpad data and verify

RX <2 bytes CRC16\> Read CRC to check for data integrity

TX (Reset) Reset pulse

RX (Presenc e) Presence puls e

TX CCh Issue “Skip ROM” command

TX 55h Issue “copy scratchpad” command

TX 20h TA1

TX 00h TA2 (AUTHORIZATION CODE)

TX 07h E/S

---- <1-Wire idle high> Wait 13 ms for the copy function to complete

RX AAh Read copy status, AAh = success

TX (Reset) Reset pulse

RX (Presenc e) Presence puls e

TX CCh Issue “Skip ROM” command

TX F0h Issue “Read Memory” command

TX 00h TA1, beginning offset=00h

TX 00h TA2, address=0000h

RX <144 data bytes> Read the entire m em ory

TX (Reset) Reset pulse

RX (Presenc e) Presence puls e

PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline inform at i on, go to