1
FEATURES
DESCRIPTION
APPLICATIONS
S5 PGOOD
VREF
0.9 V
10 mA
VTT
0.9 V
2 A
TPS51116RGE
20 19
18
17
VBST DRVH LL DRVL
V5FILT
VLDOIN
VTTGND
VTTSNS
7 8
VTT
CS_GND
9 10
VDDQSET
CS
VDDQSNS
16
15
14
13PGOOD
1211
S5S3
GND
MODE
VTTREF
COMP
NC NC
V5IN
PGND
22 2124 23
1
2
3
4
5
6
C1
5V_IN
VDDQ
1.8 V
10 A
VIN
M1
M2
S3
L1
IRF7832
IRF7821
C4
C3
Ceramic
2y10 µF
Ceramic
0.033 µF
Ceramic
0.1 µF
1 µH
C6
SP−CAP
2y150 µF
C5
Ceramic
2y10 µF
C2
Ceramic
1 µF
C7
Ceramic
1 µF
R2
100 kΩ
R1
5.1 kΩ
R3
5.1 Ω
UDG−04153
TPS51116
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................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
COMPLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTIONSYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE
2
•Synchronous Buck Controller (VDDQ)– Wide-Input Voltage Range: 3.0-V to 28-V
The TPS51116 provides a complete power supply forDDR/SSTL-2, DDR2/SSTL-18, and DDR3 memory– D −CAP™ Mode with 100-ns Load Step
systems. It integrates a synchronous buck controllerResponse
with a 3-A sink/source tracking linear regulator and– Current Mode Option Supports Ceramic
buffered low noise reference. The TPS51116 offersOutput Capacitors
the lowest total solution cost in systems where spaceis at a premium. The TPS51116 synchronous– Supports Soft-Off in S4/S5 States
controller runs fixed 400kHz pseudo-constant– Current Sensing from R
DS(on)
or Resistor
frequency PWM with an adaptive on-time control that– 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
can be configured in D-CAP™ Mode for ease of use1.5-V (DDR3) or Output Range 0.75-V to
and fastest transient response or in current mode to3.0-V
support ceramic output capacitors. The 3-Asink/source LDO maintains fast transient response– Equipped with Powergood, Overvoltage
only requiring 20- µF (2 × 10 µF) of ceramic outputProtection and Undervoltage Protection
capacitance. In addition, the LDO supply input is•3-A LDO (VTT), Buffered Reference (VREF)
available externally to significantly reduce the total– Capable to Sink and Source 3 A
power losses. The TPS51116 supports all of thesleep state controls placing VTT at high-Z in S3– LDO Input Available to Optimize Power
(suspend to RAM) and discharging VDDQ, VTT andLosses
VTTREF (soft-off) in S4/S5 (suspend to disk).– Requires only 20- µF Ceramic Output
TPS51116 has all of the protection features includingCapacitor
thermal shutdown and is offered in both a 20-pinHTSSOP PowerPAD™ package and 24-pin 4 ״QFN.– Buffered Low Noise 10-mA VREF Output– Accuracy 20 mV for both VREF and VTT– Supports High-Z in S3 and Soft-Off in S4/S5
•DDR/DDR2/DDR3/LPDDR3 Memory Power– Thermal Shutdown
Supplies
•SSTL-2 SSTL-18 and HSTL Termination
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
MINIMUMORDERABLE PART OUTPUTT
A
PACKAGE PINS ORDERNUMBER SUPPLY
QUANTITY
TPS51116PWP Tube 70PLASTIC HTSSOP
TPS51116PWPR 20 Tape-and-reel 2000PowerPAD (PWP)
TPS51116PWPRG4 Tape-and-reel 2000TPS51116RGE Tube 90-40 ° C to 85 ° C
LargePLASTIC QUAD FLAT TPS51116RGER 300024 tape-and-reelPACK (QFN)
SmallTPS51116RGET 250tape-and-reel
(1) All packaging options have Cu NIPDAU lead/ball finish.
over operating free-air temperature range unless otherwise noted
TPS51116 UNITS
VBST -0.3 to 36VBST wrt LL -0.3 to 6V
IN
Input voltage range VCS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET,
-0.3 to 6V5FILT
PGND, VTTGND, CS_GND -0.3 to 0.3DRVH -1.0 to 36V
OUT
Output voltage range LL -1.0 to 30 VCOMP, DRVL, PGOOD, VTT, VTTREF -0.3 to 6T
A
Operating ambient temperature range -40 to 85
° CT
stg
Storage temperature -55 to 150
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltagevalues are with respect to the network ground terminal unless otherwise noted.
DERATING FACTOR ABOVE T
A
=T
A
< 25 ° C POWER RATING T
A
= 85 ° C POWER RATINGPACKAGE 25 ° C(W) (W)(mW/ ° C)
20-pin PWP 2.53 25.3 1.0124-pin RGE 2.20 22.0 0.88
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RECOMMENDED OPERATING CONDITIONS
TPS51116
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................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
MIN MAX UNIT
Supply voltage, V5IN, V5FILT 4.75 5.25 VVBST, DRVH -0.1 34LL -0.6 28VLDOIN, VTT, VTTSNS, VDDQSNS -0.1 3.6Voltage range VVTTREF -0.1 1.8PGND, VTTGND, CS_GND -0.1 0.1S3, S5, MODE, VDDQSET, CS, COMP, PGOOD,
-0.1 5.25DRVLOperating free-air temperature, T
A
-40 85 ° C
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ELECTRICAL CHARACTERISTICS
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
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over operating free-air temperature range, V
V5IN
= 5 V
(1)
, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
T
A
= 25 ° C, No load, V
S3
= V
S5
= 5 V,I
V5IN1
Supply current 1, V5IN
(1)
0.8 2 mACOMP connected to capacitorT
A
= 25 ° C, No load, V
S3
= 0 V, V
S5
= 5 V,I
V5IN2
Supply current 2, V5IN
(1)
300 600COMP connected to capacitorT
A
= 25 ° C, No load, V
S3
= 0 V, V
S5
= 5 V,I
V5IN3
Supply current 3, V5IN
(1)
240 500V
COMP
= 5 V
µAI
V5INSDN
Shutdown current, V5IN
(1)
T
A
= 25 ° C, No load, V
S3
= V
S5
= 0 V 0.1 1.0I
VLDOIN1
Supply current 1, VLDOIN T
A
= 25 ° C, No load, V
S3
= V
S5
= 5 V 1 10I
VLDOIN2
Supply current 2, VLDOIN T
A
= 25 ° C, No load, V
S3
= 5 V, V
S5
= 0 V, 0.1 10I
VLDOINSDN
Standby current, VLDOIN T
A
= 25 ° C, No load, V
S3
= V
S5
= 0 V 0.1 1.0
VTTREF OUTPUT
V
VTTREF
Output voltage, VTTREF V
VDDQSNS
/2 V-10 mA < I
VTTREF
< 10 mA, V
VDDQSNS
= 2.5 V,
-20 20Tolerance to V
VDDQSNS
/2-10 mA < I
VTTREF
< 10 mA, V
VDDQSNS
= 1.8 V,
-18 18Tolerance to V
VDDQSNS
/2V
VTTREFTOL
Output voltage tolerance mV-10 mA < I
VTTREF
< 10 mA, V
VDDQSNS
= 1.5 V,
-15 15Tolerance to V
VDDQSNS
/2-10 mA < I
VTTREF
< 10 mA, V
VDDQSNS
= 1.2 V,
– 12 12Tolerance to V
VDDQSNS
/2V
VTTREFSRC
Source current V
VDDQSNS
= 2.5 V, V
VTTREF
= 0 V -20 -40 -80
mAV
VTTREFSNK
Sink current V
VDDQSNS
= 2.5 V, V
VTTREF
= 2.5 V 20 40 80
VDDQ OUTPUT
T
A
= 25 ° C, V
VDDQSET
= 0 V, No load 2.465 2.500 2.5350 ° C ≤T
A
≤85 ° C, V
VDDQSET
= 0 V, No load
(2)
2.457 2.500 2.543-40 ° C ≤T
A
≤85 ° C, V
VDDQSET
= 0 V, No load
(2)
2.440 2.500 2.550T
A
= 25 ° C, V
VDDQSET
= 5 V, No load
(2)
1.776 1.800 1.824V
VDDQ
Output voltage, VDDQ V0 ° C ≤T
A
≤85 ° C, V
VDDQSET
= 5V, No load
(2)
1.769 1.800 1.831-40 ° C ≤T
A
≤85 ° C, V
VDDQSET
= 5V, No load
(2)
1.764 1.800 1.836-40 ° C ≤T
A
≤85 ° C, Adjustable mode, No
0.75 3.0load
(2)
T
A
= 25 ° C, Adjustable mode 742.5 750.0 757.5 mVV
VDDQSET
VDDQSET regulation voltage 0 ° C ≤T
A
≤85 ° C, Adjustable mode 740.2 750.0 759.8-40 ° C ≤T
A
≤85 ° C, Adjustable mode 738.0 750.0 762.0V
VDDQSET
= 0 V 215 k Ω
R
VDDQSNS
Input impedance, VDDQSNS V
VDDQSET
= 5 V 180Adjustable mode 460V
VDDQSET
= 0.78 V, COMP = Open -0.04I
VDDQSET
Input current, VDDQSET µAV
VDDQSET
= 0.78 V, COMP = 5 V -0.06V
S3
= V
S5
= 0 V, V
VDDQSNS
= 0.5 V,I
VDDQDisch
Discharge current, VDDQ 10 40 mAV
MODE
= 0 VV
S3
= V
S5
= 0 V, V
VDDQSNS
= 0.5 V,I
VLDOINDisch
Discharge current, VLDOIN 700 mAV
MODE
= 0.5 V
(1) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.(2) Specified by design.
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................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
ELECTRICAL CHARACTERISTICS (continued)over operating free-air temperature range, V
V5IN
= 5 V , VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VTT OUTPUT
V
S3
= V
S5
= 5 V, V
VLDOIN
= V
VDDQSNS
= 2.5 V 1.25V
VTTSNS
Output voltage, VTT V
S3
= V
S5
= 5 V, V
VLDOIN
= V
VDDQSNS
= 1.8 V 0.9 VV
S3
= V
S5
= 5 V, V
VLDOIN
= V
VDDQSNS
= 1.5 V 0.75V
VDDQSNS
= V
VLDOIN
= 2.5 V, V
S3
= V
S5
= 5 V,
-20 20I
VTT
= 0 AVTT output voltage tolerance V
VDDQSNS
= V
VLDOIN
= 2.5 V, V
S3
= V
S5
= 5 V,V
VTTTOL25
-30 30 mVto VTTREF |I
VTT
| < 1.5 AV
VDDQSNS
= V
VLDOIN
= 2.5 V, V
S3
= V
S5
= 5 V,
-40 40|I
VTT
| < 3 AV
VDDQSNS
= V
VLDOIN
= 1.8 V, V
S3
= V
S5
= 5 V,
-20 20I
VTT
= 0 AVTT output voltage tolerance V
VDDQSNS
= V
VLDOIN
= 1.8 V, V
S3
= V
S5
= 5 V,V
VTTTOL18
-30 30 mVto VTTREF |I
VTT
| < 1 AV
VDDQSNS
= V
VLDOIN
= 1.8 V, V
S3
= V
S5
= 5 V,
-40 40|I
VTT
| < 2 AV
VDDQSNS
= V
VLDOIN
= 1.5 V, V
S3
= V
S5
= 5 V,
-20 20I
VTT
= 0 AVTT output voltage tolerance V
VDDQSNS
= V
VLDOIN
= 1.5 V, V
S3
= V
S5
= 5 V,V
VTTTOL15
-30 30 mVto VTTREF |I
VTT
| < 1 AV
VDDQSNS
= V
VLDOIN
= 1.5 V, V
S3
= V
S5
= 5 V,
-40 40|I
VTT
| < 2 AV
VDDQSNS
= V
VLDOIN
= 1.2 V, V
S3
= V
S5
= 5 V,
-20 20I
VTT
= 0 AVTT output voltage tolerance V
VDDQSNS
= V
VLDOIN
= 1.2 V, V
S3
= V
S5
= 5 V,V
VTTTOL12
-30 30 mVto VTTREF |I
VTT
| < 1 AV
VDDQSNS
= V
VLDOIN
= 1.2 V, V
S3
= V
S5
= 5 V,
-40 40|I
VTT
| < 1.5 AV
VLDOIN
= V
VDDQSNS
= 2.5 V, V
VTT
= V
VTTSNS
=
3.0 3.8 6.01.19 V, PGOOD = HII
VTTTOCLSRC
Source current limit, VTT
V
VLDOIN
= V
VDDQSNS
= 2.5 V, V
VTT
= 0 V 1.5 2.2 3.0
AV
VLDOIN
= V
VDDQSNS
= 2.5 V, V
VTT
= V
VTTSNS
=
3.0 3.6 6.01.31 V, PGOOD = HII
VTTTOCLSNK
Sink current limit, VTT
V
VLDOIN
= V
VDDQSNS
= 2.5 V, V
VTT
= V
VDDQ
1.5 2.2 3.0I
VTTLK
Leakage current, VTT V
S3
= 0 V, V
S5
= 5 V, V
VTT
= V
VDDQSNS
/2 -10 10I
VTTBIAS
Input bias current, VTTSNS V
S3
= 5 V, V
VTTSNS
= V
VDDQSNS
/2 -1 -0.1 1 µAI
VTTSNSLK
Leakage current, VTTSNS V
S3
= 0 V, V
S5
= 5 V, V
VTT
= V
VDDQSNS
/2 -1 1T
A
= 25 ° C, V
S3
= V
S5
= V
VDDQSNS
= 0 V,I
VTTDisch
Discharge current, VTT 10 17 mAV
VTT
= 0.5 V
TRANSCONDUCTANCE AMPLIFIER
gm Gain T
A
= 25 ° C 240 300 360 µSCOMP maximum sink V
S3
= 0 V, V
S5
= 5 V, V
VDDQSET
= 0 V,I
COMPSNK
13current V
VDDQSNS
= 2.7 V, V
COMP
= 1.28 V
µACOMP maximum source V
S3
= 0 V, V
S5
= 5 V, V
VDDQSET
= 0 V,I
COMPSRC
-13current V
VDDQSNS
= 2.3 V, V
COMP
= 1.28 VV
S3
= 0 V, V
S5
= 5 V, V
VDDQSET
= 0 V,V
COMPHI
COMP high clamp voltage 1.31 1.34 1.37V
VDDQSNS
= 2.3 V, V
CS
= 0 V
VV
S3
= 0 V, V
S5
= 5 V, V
VDDQSET
= 0 V,V
COMPLO
COMP low clamp voltage 1.18 1.21 1.24V
VDDQSNS
= 2.7 V, V
CS
= 0 V
Copyright © 2004 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
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SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
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ELECTRICAL CHARACTERISTICS (continued)over operating free-air temperature range, V
V5IN
= 5 V , VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DUTY CONTROL
T
ON
Operating on-time V
IN
= 12 V, V
VDDQSET
= 0 V 520T
ON0
Startup on-time V
IN
= 12 V, V
VDDQSNS
= 0 V 125
nsT
ON(min)
Minimum on-time T
A
= 25 ° C
(3)
100T
OFF(min)
Minimum off-time T
A
= 25 ° C
(3)
350
ZERO CURRENT COMPARATOR
Zero current comparatorV
ZC
-6 0 6 mVoffset
OUTPUT DRIVERS
Source, I
DRVH
= -100 mA 3 6R
DRVH
DRVH resistance
Sink, I
DRVH
= 100 mA 0.9 3
ΩSource, I
DRVL
= -100 mA 3 6R
DRVL
DRVL resistance
Sink, I
DRVL
= 100 mA 0.9 3LL-low to DRVL-on
(3)
10T
D
Dead time nsDRVL-off to DRVH-on
(3)
20
INTERNAL BST DIODE
V
FBST
Forward voltage V
V5IN-VBST
, I
F
= 10 mA, T
A
= 25 ° C 0.7 0.8 0.9 VV
VBST
= 34 V, V
LL
= 28 V, V
VDDQ
= 2.6 V,I
VBSTLK
VBST leakage current 0.1 1.0 µAT
A
= 25 ° C
PROTECTIONS
V
PGND-CS
, PGOOD = HI, V
CS
< 0.5 V 50 60 70V
OCL
Current limit threshold mVV
PGND-CS
, PGOOD = LO, V
CS
< 0.5 V 20 30 40T
A
= 25 ° C, V
CS
> 4.5 V, PGOOD = HI 9 10 11I
TRIP
Current sense sink current µAT
A
= 25 ° C, V
CS
> 4.5 V, PGOOD = LO 4 5 6TRIP current temperature R
DS(on)
sense scheme, On the basisTC
ITRIP
4500 ppm/ ° Ccoefficient of T
A
= 25 ° C
(3)
Overcurrent protection (V
V5IN-CS
- V
PGND-LL
), V
V5IN-CS
= 60 mV,V
OCL(off)
-5 0 5COMP offset V
CS
> 4.5 V
(3)
mVCurrent limit threshold settingV
R(trip)
V
V5IN-CS
(3) (4)
30 150range
POWERGOOD COMPARATOR
PG in from lower 92.5% 95.0% 97.5%V
TVDDQPG
VDDQ powergood threshold PG in from higher 102.5% 105.0% 107.5%PG hysteresis 5%I
PG(max)
PGOOD sink current V
VTT
= 0 V, V
PGOOD
= 0.5 V 2.5 7.5 mAT
PG(del)
PGOOD delay time Delay for PG in 80 130 200 µs
(3) Specified by design.(4) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.
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................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
ELECTRICAL CHARACTERISTICS (continued)over operating free-air temperature range, V
V5IN
= 5 V , VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD
Wake up 3.7 4.0 4.3V5IN UVLO thresholdV
UVV5IN
voltage
Hysteresis 0.2 0.3 0.4No discharge 4.7V
THMODE
MODE threshold
Non-tracking discharge 0.12.5 V output 0.08 0.15 0.25 VV
THVDDQSET
VDDQSET threshold voltage
1.8 V output 3.5 4.0 4.5V
IH
High-level input voltage S3, S5 2.2V
IL
Low-level input voltage S3, S5 0.3V
IHYST
Hysteresis voltage S3, S5 0.2V
INLEAK
Logic input leakage current S3, S5, MODE -1 1
µAV
INVDDQSET
Input leakage/ bias current VDDQSET -1 1
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
OVP detect 110% 115% 120%VDDQ OVP trip thresholdV
OVP
voltage
Hysteresis 5%VDDQ OVP propagationT
OVPDEL
1.5 µsdelay
(5)
UVP detect 70%V
UVP
Output UVP trip threshold
Hysteresis 10%Output UVP propagationT
UVPDEL
32delay
(5)
cycleT
UVPEN
Output UVP enable delay
(5)
1007
THERMAL SHUTDOWN
Shutdown temperature 160T
SDN
Thermal SDN threshold
(5)
° CHysteresis 10
(5) Specified by design.
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DEVICE INFORMATION
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
NO. I/O DESCRIPTIONNAME
PWP RGE
Output of the transconductance amplifier for phase compensation. Connect to V5IN to disableCOMP 8 6 I/O
gm amplifier and use D-CAP™ mode.Current sense comparator input (-) for resistor current sense scheme. Or overcurrent tripCS 15 16 I/O voltage setting input for R
DS(on)
current sense scheme if connected to V5IN (PWP), V5FILT(RGE) through the voltage setting resistor.DRVH 19 21 O Switching (top) MOSFET gate drive output.DRVL 17 19 O Rectifying (bottom) MOSFET gate drive output.GND 5 3 - Signal ground. Connect to minus terminal of the VTT LDO output capacitor.CS_GND - 17 Current sense comparator input (+) and ground for powergood circuit.Switching (top) MOSFET gate driver return. Current sense comparator input (-) for R
DS(on)LL 18 20 I/O
current sense.MODE 6 4 I Discharge mode setting pin. See VDDQ and VTT Discharge Control section.NC - 7,12 No connect.
Ground for rectifying (bottom) MOSFET gate driver (PWP, RGE). Also current sensePGND 16 18 -
comparator input(+) and ground for powergood circuit (PWP).Powergood signal open drain output, In HIGH state when VDDQ output voltage is within thePGOOD 13 13 O
target range.S3 11 10 I S3 signal input.S5 12 11 I S5 signal input.V5IN 14 15 I 5-V power supply input for internal circuits (PWP) and MOSFET gate drivers (PWP, RGE).Filtered 5-V power supply input for internal circuits. Connect R-C network from V5IN toV5FILT - 14 I
V5FILT.VBST 20 22 I/O Switching (top) MOSFET driver bootstrap voltage input.VDDQSET 10 9 I VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section.VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. DischargeVDDQSNS 9 8 I/O current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input forVDDQ output if VDDQSET pin is connected to V5IN or GND.VLDOIN 1 23 I Power supply for the VTT LDO.VTT 2 24 O Power output for the VTT LDO.VTTGND 3 1 - Power ground output for the VTT LDO.VTTREF 7 5 O VTTREF buffered reference output.Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO outputVTTSNS 4 2 I
capacitor.
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1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VLDOIN
VTT
VTTGND
VTTSNS
GND
MODE
VTTREF
COMP
VDDQSNS
VDDQSET
VBST
DRVH
LL
DRVL
PGND
CS
V5IN
PGOOD
S5
S3
PWP PACKAGE
(TOP VIEW)
NC
VDDQSNS
VDDQSET
S3
S5
NC
7
8
9
10
11
12
RGE PACKAGE
(BOTTOM VIEW)
24
23
22
21
20
19
VTT
VLDOIN
VBST
DRVH
LL
DRVL
123456
18 17 16 15 14 13
VTTGND
VTTSNS
GND
MODE
VTTREF
COMP
PGND
CS_GND
CS
V5IN
V5FILT
PGOOD
TPS51116
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TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
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FUNCTIONAL BLOCK DIAGRAM (PWP)
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TPS51116
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................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
FUNCTIONAL BLOCK DIAGRAM (RGE)
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DETAILED DESCRIPTION
VDDQ SMPS, Dual PWM Operation Modes
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
www.ti.com
The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pinHTSSOP package or a 24-pin QFN package. Each of these rails generates VDDQ, VTTREF and VTT thatrequired with DDR/DDR2/DDR3 memory systems. The switch mode power supply (SMPS) portion employsexternal N-channel MOSFETs to support high current for DDR/DDR2/DDR3 memory ’ s VDD/VDDQ. The presetoutput voltage is selectable from 2.5 V or 1.8 V. User defined output voltage is also possible and can beadjustable from 0.75 V to 3 V. Input voltage range of the SMPS is 3 V to 28 V. The SMPS runs an adaptiveon-time PWM operation at high-load condition and automatically reduces frequency to keep excellent efficiencydown to several mA. Current sensing scheme uses either R
DS(on)
of the external rectifying MOSFET for alow-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying MOSFET for moreaccurate current limit. The output of the switcher is sensed by VDDQSNS pin to generate one-half VDDQ for the10-mA buffered reference (VTTREF) and the VTT active termination supply. The VTT LDO can source and sinkup to 3-A peak current with only 20- µF (two 10- µF in parallel) ceramic output capacitors. VTTREF tracks VDDQ/2within 1% of VDDQ. VTT output tracks VTTREF within 20 mV at no load condition while 40 mV at full load. TheLDO input can be separated from VDDQ and optionally connected to a lower voltage by using VLDOIN pin. Thishelps reducing power dissipation in sourcing phase. TheTPS51116 is fully compatible to JEDEC DDR/DDR2specifications at S3/S5 sleep state (see Table 2 ). The part has two options of output discharge function whenboth VTT and VDDQ are disabled. The tracking discharge mode discharges VDDQ and VTT outputs through theinternal LDO transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-trackingdischarge mode discharges outputs using internal discharge MOSFETs which are connected to VDDQSNS andVTT. The current capability of these discharge FETs are limited and discharge occurs more slowly than thetracking discharge. These discharge functions can be disabled by selecting non-discharge mode.
The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller.It supports two control schemes which are a current mode and a proprietary D-CAP™ mode. D-CAP™ modeuses internal compensation circuit and is suitable for low external component count configuration with anappropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using externalcompensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such asceramic or specialty polymer capacitors.
These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN,TPS51116 works in the D-CAP™ mode, otherwise it works in the current mode. VDDQ output voltage ismonitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is theoutput of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected toVDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section).
At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFETis turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by V
IN
andV
OUT
to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control (seePWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when feedbackinformation indicates insufficient output voltage and inductor current information indicates below the overcurrentlimit. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom orthe rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. The rectifyingMOSFET is turned off when inductor current information detects zero level. This enables seamless transition tothe reduced frequency operation at light load condition so that high efficiency is kept over broad range of loadcurrent.
In the current mode control scheme, the transconductance amplifier generates a target current levelcorresponding to the voltage difference between the feedback point and the internal 750 mV reference. Duringthe OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, andwhen the inductor current signal comes lower than the target current level, the comparator provides SET signalto initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to supportvarious types of output MOSFETs and capacitors. In the D-CAP™ mode, the transconductance amplifier isdisabled and the PWM comparator compares the feedback point voltage and the internal 750 mV referenceduring the OFF state. When the feedback point comes lower than the reference voltage, the comparator providesSET signal to initiate the next ON state.
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VDDQ SMPS, Light Load Condition
IOUT(LL) +1
2 L f (VIN *VOUT) VOUT
VIN
(1)
Low-Side Driver
High-Side Driver
Current Sensing Scheme
TPS51116
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................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. Thisreduction of frequency is achieved smoothly and without increase of V
OUT
ripple or load regulation. Detailoperation is described as follows. As the output current decreases from heavy load condition, the inductor currentis also reduced and eventually comes to the point that its valley touches zero current, which is the boundarybetween continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off whenthis zero inductor current is detected. As the load current further decreased, the converter runs in discontinuousconduction mode and it takes longer and longer to discharge the output capacitor to the level that requires nextON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output currentincrease from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductorcurrent reaches to the continuous conduction. The transition load point to the light load operation I
OUT(LL)
(i.e. thethreshold between continuous and discontinuous conduction mode) can be calculated in Equation 1 :
where
•fis the PWM switching frequency (400 kHz)
Switching frequency versus output current in the light load condition is a function of L, f, V
IN
and V
OUT
, but itdecreases almost proportional to the output current from the I
OUT(LL)
given above. For example, it is 40 kHz atI
OUT(LL)
/10 and 4 kHz at I
OUT(LL)
/100.
The low-side driver is designed to drive high-current, low-R
DS(on)
, N-channel MOSFET(s). The drive capability isrepresented by its internal resistance, which are 3 Ω for V5IN to DRVL and 0.9 Ωfor DRVL to PGND. Adead-time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, andbottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from V5IN supply. The instantaneous drivecurrent is supplied by an input capacitor connected between V5IN and GND. The average drive current is equalto the gate charge at V
GS
= 5 V times switching frequency. This gate drive current as well as the high-side gatedrive current times 5 V makes the driving power which needs to be dissipated from TPS51116 package.
The high-side driver is designed to drive high-current, low-R
DS(on)
N-channel MOSFET(s). When configured as afloating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by thegate charge at V
GS
= 5V times switching frequency. The instantaneous drive current is supplied by the flyingcapacitor between VBST and LL pins. The drive capability is represented by its internal resistance, which are 3 Ω for VBST to DRVH and 0.9 Ωfor DRVH to LL.
In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistorsensing and MOSFET R
DS(on)
sensing. For resistor sensing scheme, an appropriate current sensing resistorshould be connected between the source terminal of the bottom MOSFET and PGND. CS pin is connected to theMOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS pin.For R
DS(on)
sensing scheme, CS pin should be connected to V5IN (PWP), or V5FILT (RGE) through the tripvoltage setting resistor, R
TRIP
. In this scheme, CS terminal sinks 10- µA I
TRIP
current and the trip level is set to thevoltage across the R
TRIP
. The inductor current is monitored by the voltage between PGND pin and LL pin so thatLL pin should be connected to the drain terminal of the bottom MOSFET. I
TRIP
has 4500ppm/ ° C temperatureslope to compensate the temperature dependency of the R
DS(on)
. In either scheme, PGND is used as the positivecurrent sensing node so that PGND should be connected to the proper current sensing device, i.e. the senseresistor or the source terminal of the bottom MOSFET.
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PWM Frequency and Adaptive On-Time Control
VDDQ Output Voltage Selection
VTT Linear Regulator and VTTREF
Outputs Management by S3, S5 Control
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
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TPS51116 employs adaptive on-time control scheme and does not have a dedicated oscillator on board.However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and outputvoltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage andproportional to the output voltage so that the duty ratio is kept as V
OUT
/V
IN
technically with the same cycle time.Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin duringthe ON state. This helps pin count reduction to make the part compact without sacrificing its performance. Inorder to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the outputbecomes 750 mV or larger.
TPS51116 can be used for both of DDR (V
VDDQ
= 2.5 V) and DDR2 (V
VDDQ
= 1.8 V) power supply and adjustableoutput voltage (0.75 V < V
VDDQ
< 3 V) by connecting VDDQSET pin as shown in Table 1 . Use adjustable outputvoltage scheme for DDR3 application.
Table 1. VDDQSET and Output Voltages
VDDQSET VDDQ (V) VTTREF and VTT NOTE
GND 2.5 V
VDDQSNS
/2 DDRV5IN 1.8 V
VDDQSNS
/2 DDR2FB Resistors 1.5 V
VDDQSNS
/2 DDR3R
UP
= R
DOWN
=75 k Ω
FB Resistors Adjustable V
VDDQSNS
/2 0.75 V < V
VDDQ
< 3 V
(1)
TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinkingcurrent up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramiccapacitors are enough to keep tracking the VTTREF within 40 mV at all conditions including fast load transient.To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, shouldbe connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stableoperation, total capacitance of the VTT output terminal can be equal to or greater than 20 µF. It is recommendedto attach two 10- µF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the outputcapacitor is greater than 2 m Ω, insert an RC filter between the output and the VTTSNS input to achieve loopstability. The RC filter time constant should be almost the same or slightly lower than the time constant made bythe output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulatoralso has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033- µF ceramic capacitor forstable operation.
In the DDR/DDR2/DDR3 memory applications, it is important to keep VDDQ always higher than VTT/VTTREFincluding both start-up and shutdown. TPS51116 provides this management by simply connecting both S3 andS5 terminals to the sleep-mode signals such as SLP_S3 and SLP_S5 in the notebook PC system. All of VDDQ,VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ andVTTREF voltages are kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT outputis floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the threeoutputs are disabled. Outputs are discharged to ground according to the discharge mode selected by MODE pin(see VDDQ and VTT Discharge Control section). Each state code represents as follow; S0 = full ON, S3 =suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 2 )
Table 2. S3 and S5 Control
STATE S3 S5 VDDQ VTTREF VTT
S0 HI HI On On OnS3 LO HI On On Off (Hi-Z)S4/S5 LO LO Off (Discharge) Off (Discharge) Off (Discharge)
(1) V
VDDQ
≥1.2 V when used as VLDOIN.
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Product Folder Link(s): TPS51116
Soft-Start and Powergood
VOCL
VVDDQ
VPGOOD
VS5
80%87% 100%
85 µs45 µsUDG−04066
TVDDQSS +2 CVDDQ VVDDQ 0.8
IVDDQOCP )85 ms
(2)
TVTTSS +CVTT VVTT
IVTTOCL
(3)
TPS51116
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................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
The soft start function of the SMPS is achieved by ramping up reference voltage and two-stage current clamp. Atthe starting point, the reference voltage is set to 650 mV (87% of its target value) and the overcurrent thresholdis set half of the nominal value. When UVP comparator detects VDDQ become greater than 80% of the target,the reference voltage is raised toward 750 mV using internal 4-bit DAC. This takes approximately 85 µs. Theovercurrent threshold is released to nominal value at the end of this period. The powergood signal waits another45 µs after the reference voltage reaches 750 mV and the VDDQ voltage becomes good (above 95% of thetarget voltage), then turns off powergood open-drain MOSFET.
The soft-start function of the VTT LDO is achieved by current clamp. The current limit threshold is also changedin two stages using an internal powergood signal dedicated for LDO. During VTT is below the powergoodthreshold, the current limit level is cut into 60% (2.2 A).This allows the output capacitors to be charged with lowand constant current that gives linear ramp up of the output. When the output comes up to the good state, theovercurrent limit level is released to normal value (3.8 A). TPS51116 has an independent counter for eachoutput, but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT powergoodexternally. See Figure 1 .
Figure 1. VDDQ Soft-Start and Powergood Timing
Soft-start duration, T
VDDQSS
, T
VTTSS
are functions of output capacitances.
where I
VDDQOCP
is the current limit value for VDDQ switcher calculated by Equation 5 .
where, I
VTTOCL
= 2.2 A (typ). In each of the two previous calculations, no load current during start-up areassumed. Note that both switchers and the LDO do not start up with full load condition.
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VDDQ and VTT Discharge Control
Current Protection for VDDQ
VTRIP (mV) +RTRIP (kW) 10 (mA)
(4)
IOCP +VTRIP
RDS(on) )IRIPPLE
2+VTRIP
RDS(on) )1
2 L f ǒVIN *VOUTǓ VOUT
VIN
(5)
Current Protection for VTT
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
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TPS51116 discharges VDDQ, VTTREF and VTT outputs during S3 and S5 are both low. There are two differentdischarge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3 .
Table 3. Discharge Selection
MODE DISCHARGE MODE
V5IN No dischargeVDDQ Tracking dischargeGND Non-tracking discharge
When in tracking-discharge mode, TPS51116 discharges outputs through the internal VTT regulator transistorsand VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows viaVLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO canhandle up to 3 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned offand the operation mode is changed to the non-tracking-discharge mode.
When in non-tracking-discharge mode, TPS51116 discharges outputs using internal MOSFETs which areconnected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly.Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In case of no discharge mode,TPS51116 does not discharge output charge at all.
The SMPS has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF stateand the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. Thetrip level and current sense scheme are determined by CS pin connection (see Current Sensing Schemesection). For resistor sensing scheme, the trip level, V
TRIP
, is fixed value of 60 mV.
For R
DS(on)
sensing scheme, CS terminal sinks 10 µA and the trip level is set to the voltage across this R
TRIPresistor.
As the comparison is done during the OFF state, V
TRIP
sets valley level of the inductor current. Thus, the loadcurrent at overcurrent threshold, I
OCP
, can be calculated as shown in Equation 5 .
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the outputvoltage tends to fall down. If the output voltage becomes less than Powergood level, the V
TRIP
is cut into half andthe output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold andshutdown.
The LDO has an internally fixed constant overcurrent limiting of 3.8 A while operating at normal condition. Thistrip point is reduced to 2.2 A before the output voltage comes within 5% of the target voltage or goes outside of10% of the target voltage.
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Overvoltage and Undervoltage Protection for VDDQ
V5IN (PWP), V5FILT (RGE) Undervoltage Lockout (UVLO) Protection
V5IN (PWP), V5FILT (RGE) Input Capacitor
Thermal Shutdown
TPS51116
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................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET isconnected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. Ifan external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself.When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goeshigh and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON.
Also, TPS51116 monitors VDDQSNS voltage directly and if it becomes greater than 4 V TPS51116 turns off thetop MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVPcomparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116latches OFF both top and bottom MOSFETs. This function is enabled after 1007 cycles of SMPS operation toensure startup.
TPS51116 has 5-V supply undervoltage lockout protection (UVLO). When the V5IN (PWP) voltage or V5FILT(RGE) voltage is lower than UVLO threshold voltage, SMPS, VTTLDO and VTTREF are shut off. This is anon-latch protection.
Add a ceramic capacitor with a value between 1.0 µF and 4.7 µF placed close to the V5IN (PWP) pin or V5FILT(RGE) pin to stabilize 5 V from any parasitic impedance from the supply.
TPS51116 monitors the temperature of itself. If the temperature exceeds the threshold value, 160 ° C (typ),SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection and the operation is resumed when thedevice is cooled down by about 10 ° C.
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APPLICATION INFORMATION
Loop Compensation and External Parts Selection
Current Mode Operation
H(s) +H1(s) H2(s) H3(s)
(6)
H1(s) +R2
(R2 )R1)
(7)
H2(s) + * gm ROǒ1)s CC RCǓ
ǒ1)s CC ROǓ ǒ1)s CC2 RCǓ
(8)
H3(s) +(1 )s CO ESR)
ǒ1)s CO RLǓ RL
RS
(9)
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
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A buck converter using TPS51116 current mode operation can be partitioned into three portions, a voltagedivider, an error amplifier and a switching modulator. By linearizing the switching modulator, we can derive thetransfer function of the whole system. Since current mode scheme directly controls the inductor current, themodulator can be linearized as shown in Figure 2 .
Figure 2. Linearizing the Modulator
Here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signalmodel. As a result, a modulated current source including the power inductor can be modeled as a current sourcewith its transconductance of 1/R
S
and the output capacitor represent the modulator portion. This simplified modelis applicable in the frequency space up to approximately a half of the switching frequency. One note is, althoughthe inductance has no influence to small signal model, it has influence to the large signal model as it limits slewrate of the current source. This means the buck converter ’ s load transient response, one of the large signalbehaviors, can be improved by using smaller inductance without affecting the loop stability.
Total open loop transfer function of the whole system is given by Equation 6 .
Assuming RL>>ESR, R
O
>>R
C
and C
C
>>C
C2
, each transfer function of the three blocks is shown starting withEquation 7 .
There are three poles and two zeros in H(s). Each pole and zero is given by the following five equations.
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wP1 +1
ǒCC ROǓ
(10)
wP2 +1
ǒCO RLǓ
(11)
wP3 +1
ǒCC2 RCǓ
(12)
wZ1 +1
ǒCC RCǓ
(13)
wZ2 +1
ǒCO ESRǓ
(14)
f0+1
2p R1
R1 )R2 gm
CO RC
RS+1
2p 0.75
VOUT gm
CO RC
RS
(15)
L+1
IIND(ripple) f ǒVIN(max) *VOUTǓ VOUT
VIN(max) +2
IOUT(max) f ǒVIN(max) *VOUTǓ VOUT
VIN(max)
(16)
IIND(peak) +VTRIP
RDS(on) )1
L f ǒVIN(max) *VOUTǓ VOUT
VIN(max)
(17)
RCv2p f0 VOUT
0.75 CO
gm RS
(18)
RC+2.8 VOUT CO[mF] RS[mW]
(19)
TPS51116
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................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f
0
. However, the f
0
should bekept under 1/3 of the switching frequency to avoid effect of switching circuit delay. The f
0
is given by Equation 15 .
Based on small signal analysis above, the external components can be selected by following manner.1. Choose the inductor. The inductance value should be determined to give the ripple current ofapproximately 1/4 to 1/2 of maximum output current.
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peakinductor current before saturation. The peak inductor current can be estimated as shown in Equation 17 .
2. Choose rectifying (bottom) MOSFET. When R
DS(on)
sensing scheme is selected, the rectifying MOSFET ’ son-resistance is used as this R
S
so that lower R
DS(on)
does not always promise better performance. In orderto clearly detect inductor current, minimum R
S
recommended is to give 15 mV or larger ripple voltage withthe inductor ripple current. This promises smooth transition from CCM to DCM or vice versa. Upper side ofthe R
DS(on)
is of course restricted by the efficiency requirement, and usually this resistance affects efficiencymore at high-load conditions. When using external resistor current sensing, there is no restriction for lowR
DS(on)
. However, the current sensing resistance R
S
itself affects the efficiency3. Choose output capacitor(s). In cases of organic semiconductor capacitors (OS-CON) or specialty polymercapacitors (SP-CAP), ESR to achieve required ripple value at stable state or transient load conditionsdetermines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. Thepeak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable state, or ESRtimes the load current step for a fast transient load response. In case of ceramic capacitor(s), usually ESR issmall enough to meet ripple requirement. On the other hand, transient undershoot and overshoot driven byoutput capacitance becomes the key factor to determine the capacitor(s).4. Determine f
0
and calculate R
C
using Equation 18 . Note that higher R
C
shows faster transient response incost of unstableness. If the transient response is not enough even with high R
C
value, try increasing the output capacitance. Recommended f
0
is f
OSC
/4. Then R
C
can be derived by Equation 19 .
5. Calculate C
C2
. Purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. In case
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wz2 +1
ǒCO ESRǓ+wp3 +1
ǒCC2 RCǓ
(20)
CC2 +ǒCO ESRǓ
RC
(21)
fz1 +1
2p CC RC+f0
10
(22)
R1 +VOUT *0.75
0.75 R2
(23)
D-CAP™ Mode Operation
f0+1
2p ESR COvfSW
3
(24)
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
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of ceramic capacitor(s) is used, no need for C
C2
.
6. Calculate C
C
.The purpose of C
C
is to cut DC component to obtain high DC feedback gain. However, as itcauses phase delay, another zero to cancel this effect at f
0
frequency is need. This zero, ωz1, is determinedby Cc and Rc. Recommended ωz1 is 10 times lower to the f
0
frequency.
7. When using adjustable mode, determine the value of R1 and R2. .
A buck converter system using D-CAP™ Mode can be simplified as below.
Figure 3. Linearizing the Modulator
The VDDQSNS voltage is compare with internal reference voltage after divider resistors. The PWM comparatordetermines the timing to turn on top MOSFET. The gain and speed of the comparator is high enough to keep thevoltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output voltagemay have line regulation due to ripple amplitude that slightly increases as the input voltage increase.
For the loop stability, the 0-dB frequency, f
0
, defined below need to be lower than 1/3 of the switching frequency.
As f
0
is determined solely by the output capacitor ’ s characteristics, loop stability of D-CAP™ mode is determinedby the capacitor ’ s chemistry. For example, specialty polymer capacitors (SP-CAP) have C
O
in the order ofseveral 100 µF and ESR in range of 10 m Ω. These makes f
0
in the order of 100 kHz or less and the loop is thenstable. However, ceramic capacitors have f
0
at more than 700 kHz, which is not suitable for this operationalmode.
Although D-CAP™ mode provides many advantages such as ease-of-use, minimum external componentsconfiguration and extremely short response time, due to not employing an error amplifier in the loop, sufficientamount of feedback signal needs to be provided by external circuit to reduce jitter level.
The required signal level is approximately 15 mV at comparing point. This gives V
RIPPLE
= (V
OUT
/0.75) x 15 (mV)at the output node. The output capacitor ’ s ESR should meet this requirement.
20 Submit Documentation Feedback Copyright © 2004 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51116
ESR +VOUT 0.015
IRIPPLE 0.75 [VOUT
IOUT(max) 60 [mW]
(25)
Thermal Design
WDSRC +ǒVVLDOIN *VVTTǓ IVTT
(26)
WDSNK +VVTT IVTT
(27)
WPKG +TJ(max) *TA(max)
qJA
(28)
TPS51116
www.ti.com
................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
The external components selection is much simple in D-CAP™ mode.1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in theCurrent Mode Operation section.2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) arerecommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown inEquation 25 .
Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source andsink directions generate power dissipation from the part. In the source phase, potential difference betweenVLDOIN and VTT times VTT current becomes the power dissipation, W
DSRC
.
In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can bedecreased.
For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, W
DSNK
,is calculated by Equation 27 :
Since this device does not sink AND source the current at the same time and I
VTT
varies rapidly with time, actualpower dissipation need to be considered for thermal design is an average of above value. Another powerconsumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5INsupports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOINsupply can be estimated as 1.5 mA or less at normal operational conditions.
These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to thepackage is calculated by Equation 28 ,
where
•T
J(max)
is 125 ° C•T
A(max)
is the maximum ambient temperature in the system• θ
JA
is the thermal resistance from the silicon junction to the ambient
Copyright © 2004 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS51116
Layout Considerations
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
www.ti.com
This thermal resistance strongly depends on the board layout. TPS51116 is assembled in a thermally enhancedPowerPAD™ package that has exposed die pad underneath the body. For improved thermal performance, thisdie pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heatsink/spread. The typical thermal resistance, 39.6 ° C/W, is achieved based on a 6.5 mm × 3.4 mm thermal landwith eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number.Further information about PowerPAD™ and its recommended board layout is described in (SLMA002). Thisdocument is available at http:\\www.ti.com.
Certain points must be considered before designing a layout using the TPS51116.•PCB trace defined as LL node, which connects to source of switching MOSFET, drain of rectifying MOSFETand high-voltage side of the inductor, should be as short and wide as possible.•Consider adding a small snubber circuit, consists of 3 Ωand 1 nF, between LL and PGND in case ahigh-frequency surge is observed on the LL voltage waveform.•All sensitive analog traces such as VDDQSNS, VTTSNS and CS should placed away from high-voltageswitching nodes such as LL, DRVL or DRVH nodes to avoid coupling.•VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used forVLDOIN, an input bypass capacitor should be placed to the pin as close as possible with short and wideconnection.
•The output capacitor for VTT should be placed close to the pin with short and wide connection in order toavoid additional ESR and/or ESL of the trace.•VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from thehigh current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed tosense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin andthe output capacitor(s).•Consider adding LPF at VTTSNS in case ESR of the VTT output capacitor(s) is larger than 2 m Ω.•VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the referencevoltage of VTTREF. Avoid any noise generative lines.•Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoidingcommon impedance to the high current path of the VTT source/sink current.•GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GNDto negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoidadditional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point.•Connect CS_GND (RGE) to source of rectifying MOSFET using Kevin connection. Avoid common trace forhigh-current paths such as the MOSFET to the output capacitors or the PGND to the MOSFET trace. In caseof using external current sense resistor, apply the same care and connect it to the positive side (ground side)of the resistor.•PGND is the return path for rectifying MOSFET gate drive. Use 0.65 mm (25mil) or wider trace. Connect tosource of rectifying MOSFET with shortest possible path.•Place a V5FILT filter capacitor (RGE) close to the TPS51116, within 12 mm (0.5 inches) if possible.•The trace from the CS pin should avoid high-voltage switching nodes such as those for LL, VBST, DRVH,DRVL or PGOOD.•In order to effectively remove heat from the package, prepare thermal land and solder to the package ’ sthermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.Numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side groundplane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land underneath thepackage.
22 Submit Documentation Feedback Copyright © 2004 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51116
TPS51116
www.ti.com
................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
Figure 4. D-CAP™ Mode, PWP Package
Figure 5. D-CAP™ Mode, RGE Package
Table 4. D-CAP™ Mode Schematic Components
SYMBOL SPECIFICATION MANUFACTURER PART NUMBER
R1 5.1 k Ω-R2 100 k Ω-R3 75 k Ω-R4 (100 × V
VDDQ
– 75) k Ω-R5 5.1 Ω
M1 30 V, 13 m ΩInternational Rectifier IRF7821M2 30 V, 5 m ΩInternational Rectifier IRF7832
Copyright © 2004 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS51116
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
www.ti.com
Figure 6. Current Mode, PWP Package
Figure 7. Current Mode, RGE Package
Table 5. Current Mode Schematic Components
SYMBOL SPECIFICATION MANUFACTURER PART NUMBERR1 6 m Ω, 1% Vishay WSL-2521 0.006R2 100 k Ω- -R5 5.1 Ω
M0 30 V, 13 m ΩInternational Rectifier IRF7821M1 30 V, 5 m ΩInternational Rectifier IRF7832
24 Submit Documentation Feedback Copyright © 2004 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51116
TYPICAL CHARACTERISTICS
TJ − Junction Temperature − °C
IV5IN1 − V5IN Shutdown Current − µA
0−50 0 50 100 150
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
−50
2.0
00
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
50 100 150
TJ − Junction Temperature − °C
IV5IN1 − V5IN Supply Current − mA
IVTT − VTT Current − A
IV5IN − V5IN Supply Current − mA
−2
3
0−1 0 1 2
1
2
7
4
5
6
10
8
9DDR2
VVTT = 0.9 V
TJ − Junction Temperature − °C
IVLDOIN − VLDOIN Supply Current − µA
0−50 0 50 100 150
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
TPS51116
www.ti.com
................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
All data in the following graphs are measured from the PWP packaged device.
V5IN SUPPLY CURRENT V5IN SHUTDOWN CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 8. Figure 9.
V5IN SUPPLY CURRENT VLDOIN SUPPLY CURRENTvs vsLOAD CURRENT TEMPERATURE
Figure 10. Figure 11.
Copyright © 2004 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS51116
TJ − Junction Temperature − °C
IDISCH − VDDQ Discharge Current − mA
30
40
50
70
80
60
20
10−50 0 50 100 150
TJ − Junction Temperature − °C
ITRIP − CS Current − µA
2
0−50 0 50 100 150
6
8
4
10
14
16
12 PGOOD = HI
PGOOD = LO
TJ − Junction Temperature − °C
IDISCH − VTT Discharge Current − mA
15
10
25
20
30
−50 0 50 100 150
TJ − Junction Temperature − °C
VTRIP − OVP/UVP Trip Threshold − %
60−50 0 50 100 150
80
120
100
140
VUVP
VOVP
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CS CURRENT VDDQ DISCHARGE CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 12. Figure 13.
VTT DISCHARGE CURRENT OVERVOLTAGE AND UNDERVOLTAGE THRESHOLDvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 14. Figure 15.
26 Submit Documentation Feedback Copyright © 2004 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51116
VIN − Input Voltage − V
fSW − Switching Frequency − kHz
DDR2
4
390
370 8 12 16 20 24 28
380
420
400
410
430 D-CAP Mode
IVDDQ = 7 A
DDR
0
02 4 6 8 10
100
150
50
300
400
450
350
250
200
IVDDQ − VDDQ Output Current − A
fSW − Switching Frequency − kHz
DDR2
D−CAP Mode
VIN = 12 V
DDR
0 2
1.785
1.795
1.800
1.790
1.815
1.820
1.810
1.805
1.780 4 6 8 10
IVDDQ − VDDQ Output Current − A
VVDDQ − VDDQ Output Voltage − V
D−CAP Mode
VIN = 12 V
4 8 12 16 20 24 30
1.785
1.795
1.800
1.790
1.815
1.820
1.810
1.805
1.780
VIN − Input Voltage − V
VVDDQ − VDDQ Output Voltage − V
D−CAP Mode
IVDDQ = 0 A
IVDDQ = 10 A
TPS51116
www.ti.com
................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY SWITCHING FREQUENCYvs vsINPUT VOLTAGE OUTPUT CURRENT
Figure 16. Figure 17.
VDDQ OUTPUT VOLTAGE VDDQ OUTPUT VOLTAGEvs vsOUTPUT CURRENT (DDR) INPUT VOLTAGE (DDR2)
Figure 18. Figure 19.
Copyright © 2004 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS51116
IVTT − VTT Output Current − A
VVTT − VTT Output Voltage − V
−5
1.22
1.20 −4 −3 −2 −1 0 1 2 3 4 5
1.21
1.25
1.23
1.24
1.28
1.26
1.27
1.29
1.30
VVLDOIN = 2.5 V
VVLDOIN = 1.8 V
IVTT − VTT Output Current − A
VVTT − VTT Output Voltage − V
−3
0.88
0.86 −2 −1 0 1 2 3
0.87
0.91
0.89
0.90
0.94
0.92
0.93
VVLDOIN = 1.5 V
VVLDOIN = 1.2 V
VVLDOIN = 1.8 V
−10
1.245
1.244 −5 0 5 10
1.246
1.247
1.248
1.249
1.250
1.251
1.252
IVTTREF − VTTREF Current − mA
VVTTREF − VTTREF Voltage − V
DDR
IVTTREF − VTTREF Current − mA
VVTTREF − VTTREF Voltage − V
−10 −5 0 5 10
0.897
0.896
0.898
0.899
0.900
0.901
0.902
0.903
0.904 DDR2
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VTT OUTPUT VOLTAGE VTT OUTPUT VOLTAGEvs vsOUTPUT CURRENT (DDR) OUTPUT CURRENT (DDR2)
Figure 20. Figure 21.
VTTREF OUTPUT VOLTAGE VTTREF OUTPUT VOLTAGEvs vsOUTPUT CURRENT (DDR) OUTPUT CURRENT (DDR2)
Figure 22. Figure 23.
28 Submit Documentation Feedback Copyright © 2004 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51116
-10
0.735
-5 0 510
IVTTREF - VTTREF Current - mA
0.74
0.745
0.75
0.755
0.76
0.765
IVTT - VTT Output Voltage - V
DDR3
-3
0.73
0.71
-2
0.74
0.72
0.77
0.75
0.78
0.76
0.79
VVLDOIN = 1.5 V
-1 0
IVTT - VTT Output Current - A
1 2 3
IVTT - VTT Output Voltage - V
0.001
60
50 0.01 0.1 1 10
80
70
100
90
VVDDQ = 1.8 V VIN = 8 V
VIN = 20 V
VIN = 12 V
IVDDQ − VDDQ Current − A
Efficiency − %
0.001
60
50 0.01 0.1 1 10
80
70
100
90
IVDDQ − VDDQ Current − A
Efficiency − %
VVDDQ = 2.5 V VIN = 8 V
VIN = 20 V
VIN = 12 V
TPS51116
www.ti.com
................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
TYPICAL CHARACTERISTICS (continued)
VTTREF OUTPUT VOLTAGE VTT OUTPUT VOLTAGEvs vsOUTPUT CURRENT (DDR3) OUTPUT CURRENT (DDR3)
Figure 24. Figure 25.
VDDQ EFFICIENCY (DDR) VDDQ EFFICIENCY (DDR2)vs vsVDDQ CURRENT VDDQ CURRENT
Figure 26. Figure 27.
Copyright © 2004 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): TPS51116
t − T ime − 2 µs/div
VVDDQ (50 mV/div)
IVDDQ (2 A/div)
VVTTREF (10 mV/div)
VVTT (10 mV/div)
t − T ime − 20 µs/div
VVDDQ (50 mV/div)
IVDDQ (5 A/div)
IIND (5 A/div)
t − T ime − 100 µs/div
VDDQ
VTTREF
PGOOD
S5
IVDDQ = IVTTREF = 0 A
t − T ime − 20 µs/div
VVDDQ (50 mV/div)
VVTT (20 mV/div)
VVTTREF
(20 mV/div)
IVTT
(2 A/div)
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 28. Ripple Waveforms - Heavy Load Condition Figure 29. VDDQ Load Transient Response
Figure 30. VTT Load Transient Response Figure 31. VDDQ, VTT, and VTTREF Start-Up Waveforms
30 Submit Documentation Feedback Copyright © 2004 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51116
t − T ime − 1 ms/div
VDDQ
VTTREF
VTT
S5
IVDDQ = IVTT = IVTTREF = 0 A
t − T ime − 200 µs/div
VDDQ
VTTREF
VTT
S5
IVDDQ = IVTT = IVTTREF = 0 A
100
−40
−80 1 k 100 k 1 M
−60
20
−20
0
80
40
60
−90
45
−45
0
180
90
135
−180
−135
f − Frequency − Hz
Gain − dB
Phase − 5
Phase
Gain
IVDDQ = 7 A
10 k
Gain − dB
Phase − 5
10 k
−40
−80 100 k 1 M 10 M
−60
20
−20
0
80
40
60
−90
45
−45
0
180
90
135
−180
−135
Phase
Gain
f − Frequency − Hz
IVTT = −1 A
TPS51116
www.ti.com
................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009
TYPICAL CHARACTERISTICS (continued)
Figure 32. Soft-Start Waveforms Tracking Discharge Figure 33. Soft-Stop Waveforms Non-Tracking Discharge
VDDQ BODE PLOT (CURRENT MODE) VTT BODE PLOT, SOURCE (DDR2)GAIN AND PHASE GAIN AND PHASEvs vsFREQUENCY FREQUENCY
Figure 34. Figure 35.
Copyright © 2004 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): TPS51116
10 k
−40
−80 100 k 1 M 10 M
−60
20
−20
0
80
40
60
−90
45
−45
0
180
90
135
−180
−135
f − Frequency − Hz
Gain − dB
Phase
Gain
IVTT = 1 A
Phase − °
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VTT BODE PLOT, SINK (DDR2)GAIN AND PHASE
vsFREQUENCY
Figure 36.
32 Submit Documentation Feedback Copyright © 2004 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51116
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS51116PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS51116PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS51116PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS51116PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS51116RGER ACTIVE VQFN RGE 24 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS51116RGERG4 ACTIVE VQFN RGE 24 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS51116RGET ACTIVE VQFN RGE 24 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS51116RGETG4 ACTIVE VQFN RGE 24 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Jul-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS51116PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS51116RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS51116RGET VQFN RGE 24 250 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q2
TPS51116RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51116PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS51116RGER VQFN RGE 24 3000 367.0 367.0 35.0
TPS51116RGET VQFN RGE 24 250 195.0 200.0 45.0
TPS51116RGET VQFN RGE 24 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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