March 2008 Rev 2 1/37
37
VND5E160AJ-E
Double channel high side driver with analog current sense
for automotive applications
Features
■General
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
european directive
– Very low current sense leakage
■Diagnostic functions
– Proportional load current sense
– High current sense precision for wide
currents range
– Current sense disable
– Off state openload detection
– Output short to VCC detection
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
■Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Over-temperature shutdown with
autorestart (thermal shutdown)
– Reverse battery protected (see Application
schematic)
– Electrostatic discharge protection
Application
■All types of resistive, inductive and capacitive
loads
■Suitable as LED driver
Description
The VND5E160AJ-E is a single channel high-side
driver manufactured in the ST proprietary
VIPower M0-5 technology and housed in the tiny
PowerSSO-12 package. The VND5E160AJ-E is
designed to drive 12V automotive grounded loads
delivering protection, diagnostics and easy 3V
and 5V CMOS compatible interface with any
microcontroller.
The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, over-temperature shut-off with
auto-restart and over-voltage active clamp. A
dedicated analog current sense pin is associated
with every output channel in order to provide
Ehnanced diagnostic functions including fast
detection of overload and short-circuit to ground
through power limitation indication, over-
temperature indication, short-circuit to Vcc
diagnosis and ON & OFF state open load
detection. The current sensing and diagnostic
feedback of the whole device can be disabled by
pulling the CS_DIS pin high to allow sharing of
the external sense resistor with other similar
devices.
Max transient supply voltage VCC 41 V
Operating voltage range VCC 4.5 to 28V
Max On-state resistance (per ch.) RON 160 mΩ
Current limitation (typ.) ILIMH 10 A
Off state supply current IS2 µA(1)
1. Typical value with all loads connected.
PowerSSO-12
www.st.com
Contents VND5E160AJ-E
2/37
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24
3.1.1 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 24
3.1.2 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 25
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1 Short to VCC and OFF state open load detection . . . . . . . . . . . . . . . . . 27
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28
4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VND5E160AJ-E List of tables
3/37
List of tables
Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Current sense (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Openload detection (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
List of figures VND5E160AJ-E
4/37
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Openload Off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Iout/ Isense vs. Iout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. OFF-State Open Load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. TJ evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. On state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 28. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 29. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 33. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 34. Maximum turn-Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 28
Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 29
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 30
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 30
Figure 39. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 40. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
VND5E160AJ-E Block diagram and pin description
5/37
1 Block diagram and pin description
Figure 1. Block diagram
Table 1. Pin function
Name Function
VCC Battery connection.
OUTPUTnPower output.
GND Ground connection. Must be reverse battery protected by an external
diode/resistor network.
INPUTn
Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state.
CURRENT SENSEnAnalog current sense pin, delivers a current proportional to the load current.
CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
VCC
CH 1
C ontrol & Diagnostic 1
LOGIC
DRIVER
VON
L imi tatio n
Current
Limitation
Power
Clamp
OFF State
Open load
Over
temp.
Undervoltage
VSENSEH
Current
Sense
CH 2
OVERLOAD PROTECTION
(A C TIVE P O W E R LIMITA TION)
IN 1
IN 2
CS1
CS2
CS_
DIS
GND
OUT2
OUT1
Signal Clamp
CONTROL & DIAGNOSTIC
C hannels 2
Block diagram and pin description VND5E160AJ-E
6/37
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Current sense N.C. Output Input CS_DIS
Floating Not allowed X X X X
To ground Through 1kΩ
resistor XThrough 22kΩ
resistor
Through 10kΩ
resistor
Through 10kΩ
resistor
PowerSSO-12
TAB = V
cc
N.C.
OUTPUT2
OUTPUT1
OUTPUT1
N.C.
OUTPUT2
12
11
10
9
8
7
1
2
3
4
5
6
CS_DIS
GND
INPUT1
CURRENT SENSE1
INPUT2
CURRENT SENSE2
VND5E160AJ-E Electrical specifications
7/37
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: VFn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
I
S
I
GND
V
CC
V
CC
V
SENSE2
OUTPUT1
I
OUT1
CURRENT I
SENSE1
INPUT1
I
IN1
V
IN2
V
OUT2
GND
CS_DIS
I
CSD
V
CSD
INPUT2
I
IN2
V
IN1
SENSE1
OUTPUT2
I
OUT2
CURRENT I
SENSE2
SENSE2
V
SENSE1
V
OUT1
V
Fn
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
-VCC Reverse DC supply voltage 0.3 V
- IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse DC output current 6 A
IIN DC input current -1 to 10 mA
ICSD DC current sense disable input current -1 to 10 mA
-ICSENSE DC reverse CS pin current 200 mA
VCSENSE Current sense maximum voltage VCC-41
+VCC
V
V
Electrical specifications VND5E160AJ-E
8/37
2.2 Thermal data
Symbol Parameter Value Unit
EMAX
Maximum switching energy (single pulse)
(L=12mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )34 mJ
VESD
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
- INPUT
- CURRENT SENSE
- CS_DIS
- OUTPUT
- VCC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C
Table 3. Absolute maximum ratings (continued)
Table 4. Thermal data
Symbol Parameter Max. value Unit
Rthj-case Thermal resistance junction-case (With one channel ON) 8 °C/W
Rthj-amb Thermal resistance junction-ambient See Figure 36 °C/W
VND5E160AJ-E Electrical specifications
9/37
2.3 Electrical characteristics
Values specified in this section are for 8V<VCC<28V; -40°C<Tj<150°C, unless otherwise
stated.
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 4.5 13 28 V
VUSD Undervoltage shutdown 3.5 4.5 V
VUSDhyst
Undervoltage shutdown
hysteresis 0.5 V
RON On state resistance (1)
1. For each channel.
IOUT= 1A; Tj= 25°C
IOUT= 1A; Tj= 150°C
IOUT= 1A; VCC= 5V; Tj= 25°C
160
320
210
mΩ
mΩ
mΩ
Vclamp Clamp voltage IS= 20 mA 41 46 52 V
ISSupply current
Off State; VCC= 13V; Tj= 25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V; IOUT=0A
2(2)
3
2. PowerMOS leakage included.
5(2)
6
µA
mA
IL(off1)
Off state output
current (1)
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
0
0
0.01 3
5µA
VF
Output - VCC diode
voltage (1) -IOUT= 0.6A; Tj=150°C 0.7 V
Table 6. Switching (VCC=13V, Tj=25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn- On delay time RL= 13Ω (see Figure 6.)10 µs
td(off) Turn- Off delay time RL= 13Ω (see Figure 6.)15 µs
(dVOUT/dt)on
Turn- On voltage
slope RL= 13Ω See
Figure 26. V/µs
(dVOUT/dt)off
Turn- Off voltage
slope RL= 13Ω See
Figure 28. V/µs
WON
Switching energy
losses during twon RL= 13Ω (see Figure 6.)0.03 mJ
WOFF
Switching energy
losses during twoff RL= 13Ω (see Figure 6.)0.02 mJ
Electrical specifications VND5E160AJ-E
10/37
Table 7. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level voltage 0.9 V
IIL Low level input current VIN= 0.9V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN= 2.1V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
VICL Input clamp voltage IIN= 1mA
IIN= -1mA
5.5
-0.7
7V
V
VCSDL CS_DIS low level voltage 0.9 V
ICSDL Low level CS_DIS current VCSD= 0.9V 1 µA
VCSDH CS_DIS high level voltage 2.1 V
ICSDH High level CS_DIS current VCSD= 2.1V 10 µA
VCSD(hyst) CS_DIS hysteresis voltage 0.25 V
VCSCL CS_DIS clamp voltage ICSD= 1mA
ICSD= -1mA
5.5
-0.7
7V
V
Table 8. Protections and diagnostics (1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
IlimH DC short circuit current VCC= 13V
5V<VCC<28V
71014
14
A
A
IlimL
Short circuit current
during thermal cycling
VCC= 13V;
TR<Tj<TTSD
2.5 A
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature TRS + 1 TRS + 5 °C
TRS Thermal reset of STATUS 135 °C
THYST
Thermal hysteresis
(TTSD-TR)7°C
VDEMAG
Turn-Off output voltage
clamp IOUT= 1A; VIN= 0; L= 20mH VCC-41 VCC-46 VCC-52 V
VON
Output voltage drop
limitation
IOUT= 0.03A;
Tj= -40°C...150°C
(see Figure 8.)
25 mV
VND5E160AJ-E Electrical specifications
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Table 9. Current sense (8V<VCC<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K0IOUT/ISENSE
IOUT= 0.025A; VSENSE= 0.5V; VCSD=0V;
Tj= -40°C...150°C 270 520 730
K1IOUT/ISENSE
IOUT= 0.35A; VSENSE=0.5V; VCSD=0V;
Tj= -40°C...150°C
IOUT=0.35A; VSENSE=0.5V; VCSD=0V;
Tj= 25°C...150°C
345
370
470
470
610
540
dK1/K1(1) Current sense ratio
drift
IOUT= 0.35A; VSENSE= 0.5V;
VCSD=0V;
TJ= -40 °C to 150 °C
-13 13 %
K2IOUT/ISENSE
IOUT= 0.5A; VSENSE= 4V; VCSD= 0V;
Tj= -40°C...150°C
IOUT= 0.5A; VSENSE= 4V; VCSD= 0V;
Tj= 25°C...150°C
370
390
460
460
550
510
dK2/K2(1) Current sense ratio
drift
IOUT= 0.5 A; VSENSE= 4 V;
VCSD= 0V;
TJ= -40 °C to 150 °C
-8 8 %
K3IOUT/ISENSE
IOUT= 1.5A; VSENSE=4V; VCSD=0V;
Tj= -40°C...150°C
IOUT=1.5A; VSENSE=4V; VCSD=0V;
Tj= 25°C...150°C
400
410
430
430
470
460
dK3/K3(1) Current sense ratio
drift
IOUT= 1.5 A; VSENSE= 4 V;
VCSD=0V;
TJ= -40 °C to 150 °C
-4 4 %
ISENSE0
Analog sense
leakage current
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj=-40°C...150°C
VCSD=0V; VIN=5V; Tj=-40°C...150°C
IOUT=0.6A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj= -40°C...150°C
0
0
0
1
2
1
µA
µA
µA
IOL
Openload ON state
current detection
threshold
VIN = 5V, 8V<VCC<18V
ISENSE= 5 µA 15mA
VSENSE
Max analog
senseoutput
voltage
IOUT=1.5A; VCSD=0V; 5 V
VSENSEH(2)
Analog sense
output voltage in
fault condition
VCC=13V; RSENSE= 3.9KΩ; 8V
ISENSEH(2)
Analog sense
output current in
fault condition
VCC=13V; VSENSE= 5V; 9 mA
Electrical specifications VND5E160AJ-E
12/37
tDSENSE1H
Delay response
time from falling
edge of CS_DIS
pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=90% of ISENSE max
(see Figure 4.)
40 100 µs
tDSENSE1L
Delay response
time from rising
edge of CS_DIS
pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=10% of ISENSE max
(see Figure 4.)
520µs
tDSENSE2H
Delay response
time from rising
edge of INPUT pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=90% of ISENSE max
(see Figure 4.)
30 150 µs
∆tDSEN
SE
2H
Delay response
time between rising
edge of output
current and rising
edge of current
sense
VSENSE <4V,
ISENSE =90% of I
SENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX= 1.5A (see Figure 7)
110 µs
tDSENSE2L
Delay response
time from falling
edge of INPUT pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=10% of ISENSE max
(see Figure 4.)
80 250 µs
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open load OFF state detection.
Table 10. Openload detection (8V<VCC<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VOL
Openload Off state
voltage detection
threshold
VIN = 0 V 2 See
Figure 5 4V
tDSTKON
Output short circuit to
VCC detection delay at
turn Off
See Figure 5 180 1200 µs
IL(off2)r
Off state output current
at VOUT = 4V
VIN=0V; VSENSE=0V
VOUT rising from 0V to 4V -120 0 µA
IL(off2)f
Off state output current
at VOUT = 2V
VIN=0V; VSENSE=VSENSEH
VOUT falling from VCC to 2V -50 90 µA
td_vol
Delay response from
output rising edge to
VSENSE rising edge in
open-load
VOUT= 4 V; VIN= 0V
VSENSE= 90% of VSENSEH
20 µs
Table 9. Current sense (8V<VCC<18V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VND5E160AJ-E Electrical specifications
13/37
Figure 4. Current sense delay characteristics
Figure 5. Openload Off-state delay timing
Figure 6. Switching characteristics
SENSE CURRENT
INPUT
LOAD CURRENT
CS_DIS
tDSENSE2H tDSENSE2L
tDSENSE1L tDSENSE1H
VIN
VCS
tDSTKON
OUTPUT STUCK TO VCC
VOUT > VOL
VSENSEH
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10% t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
t
Won
t
Woff
Electrical specifications VND5E160AJ-E
14/37
Figure 7. Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
Figure 8. Output voltage drop limitation
V
IN
I
OUT
I
SENSE
I
OUTMAX
I
SENSEMAX
90% I
SENSEMAX
90% I
OUTMAX
∆
t
DSENSE2H
t
t
t
Von
Iout
Vcc-Vout
Tj=150
o
CTj=25
o
C
Tj=-40
o
C
Von/Ron(T)
VND5E160AJ-E Electrical specifications
15/37
Figure 9. Iout/ Isense vs. Iout
Figure 10. Maximum current sense ratio drift vs load current
Note: Parameter guaranteed by design; it is not tested.
200
250
300
350
400
450
500
550
600
650
700
0,35 0,58 0,81 1,04 1,27 1,5
max Tj = -40 °C to 150 °C
max Tj = 25 °C to 150 °C
min Tj = 25 °C to 150 °C
min Tj = -40 °C to 150 °C
typical value
Iout / Isense
IOUT (A)
-15
-10
-5
0
5
10
15
0,35 0,58 0,81 1,04 1,27 1,5
IOUT (A)
dk/k(%)
Electrical specifications VND5E160AJ-E
16/37
Table 11. Truth table
Conditions Input Output Sense (VCSD=0V)(1)
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Normal operation L
H
L
H
0
Nominal
Overtemperature L
H
L
L
0
VSENSEH
Undervoltage L
H
L
L
0
0
Overload
H
H
X
(no power limitation)
Cycling
(power limitation)
Nominal
VSENSEH
Short circuit to GND
(Power limitation)
L
H
L
L
0
VSENSEH
Open load OFF State
(with external pull up) LHV
SENSEH
Short circuit to VCC
(external pull up
disconnected)
L
H
H
H
VSENSEH
< Nominal
Negative output voltage
clamp LL0
VND5E160AJ-E Electrical specifications
17/37
Table 12. Electrical transient requirements
ISO 7637-2:
2004(E)
Test pulse
Test levels(1)
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
Number of
pulses or
test times
Burst cycle/pulse
repetition time Delays and
Impedance
III IV Min. Max.
1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω
2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω
3a -100V -150V 1h 90ms 100ms 0.1µs, 50Ω
3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω
4 -6V -7V 1 pulse 100ms, 0.01Ω
5b(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
+65V +87V 1 pulse 400ms, 2Ω
ISO 7637-2:
2004E
Test pulse
Test level results
III VI
1C C
2a C C
3a C C
3b C C
4C C
5b(2) CC
Class Contents
C All functions of the device performed as designed after exposure to disturbance.
EOne or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Electrical specifications VND5E160AJ-E
18/37
2.4 Waveforms
Figure 11. Normal operation
Figure 12. Overload or Short to GND
IOUT
VSENSE
VCS_DIS
INPUT
Nominal load Nominal load
Normal operation
Power Limitation
ILimH >
ILimL >
IOUT
VSENSE
VCS_DIS
INPUT
Thermal cycling
Overload or Short to GND
VND5E160AJ-E Electrical specifications
19/37
Figure 13. Intermittent Overload
Figure 14. OFF-State Open Load with external circuitry
IOUT
VSENSE
VCS_DIS
INPUT
ILimH >Nominal load
Intermittent Overload
ILimL >
Overload
VSENSEH>
INPUT
OFF-State Open Load
with external circuitry
VOL
IOUT
VSENSE
VCS_DIS
VOUT
VOUT > VOL
tDSTK(on)
VSENSEH >
Electrical specifications VND5E160AJ-E
20/37
Figure 15. Short to VCC
Figure 16. TJ evolution in Overload or Short to GND
tDSTK(on)
VOUT > VOL
Resistive
Short to VCC
Hard
Short to VCC
Short to VCC
IOUT
VCS_DIS
VOUT
VOL
tDSTK(on)
TTSD
TR
TJ evolution in
Overload or Short to GND
ILimH >
< ILimL
TJ_START
THYST
Power Limitation
Self-limitation of fast thermal transients
INPUT
IOUT
TJ
VND5E160AJ-E Electrical specifications
21/37
2.5 Electrical characteristics curves
Figure 17. Off state output current Figure 18. High level input current
Figure 19. Input clamp voltage Figure 20. Input low level
Figure 21. Input high level Figure 22. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
Iloff (nA)
Off State
Vcc=13V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
5
Iih (µA)
Vin=2.1V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
5
5,2
5,4
5,6
5,8
6
6,2
6,4
6,6
6,8
7
Vicl (V)
lin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
Vil (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
Vihyst (V)
Electrical specifications VND5E160AJ-E
22/37
Figure 23. On state resistance vs. Tcase Figure 24. On state resistance vs. VCC
Figure 25. Undervoltage shutdown Figure 26. Turn-On voltage slope
Figure 27. ILIMH vs. Tcase Figure 28. Turn-Off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
50
100
150
200
250
300
Ron (mOhm)
Iout= 1A
Vcc=13V
0 5 10 15 20 25 30 35 40
Vcc (V)
50
100
150
200
250
300
Ron (mOhm)
Tc=-40°C
Tc=25°C
Tc=125°C
Tc=150°C
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
2
4
6
8
10
12
14
16
Vusd (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
800
900
1000
(dVout/dt )On (V/ms)
Vcc=13V
RI=13 Ohm
-50 -25 0 25 50 75 100 125 150
Tc (°C)
0
5
10
15
20
Ilimh (A)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
500
600
700
800
900
1000
1100
1200
1300
1400
(dVout/dt )Off (V/ms)
Vcc=13V
RI= 13 Ohm
VND5E160AJ-E Electrical specifications
23/37
Figure 29. CS_DIS high level voltage Figure 30. CS_DIS clamp voltage
Figure 31. CS_DIS low level voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vcsdh (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
9
10
Vcsdcl(V)
Iin = 1 mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
Vcsdl (V)
Application information VND5E160AJ-E
24/37
3 Application information
Figure 32. Application schematic
Note: Channel 2 has the same internal circuit as channel 1.
3.1 GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1 Solution 1 : resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600mV / (IS(on)max)
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum On-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are On in the case of several
high side drivers sharing the same RGND.
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
Μ
CU
+5V
V
GND
CS_DIS
INPUT
R
prot
R
prot
CURRENT SENSE
R
SENSE
R
prot
C
EXT
VND5E160AJ-E Application information
25/37
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2 Solution 2 : diode (DGND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ
Recommended values: Rprot =10kΩ, CEXT=10nF.
Application information VND5E160AJ-E
26/37
3.4 Current sense and diagnostic
The current sense pin performs a double function (see Figure 33: Current sense and
diagnostic):
●Current mirror of the load current in normal operation, delivering a current
proportional to the load one according to a know ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5V
minimum (see parameter VSENSE in Table 9: Current sense (8V<VCC<18V)). The
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8V<VCC<18V)).
●Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a
maximum current ISENSEH in case of the following fault conditions (refer to Tr u t h t a bl e ):
– Power limitation activation
– Over-temperature
–Short to V
CC in OFF state
– Open load in OFF state with additional external components.
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.
Figure 33. Current sense and diagnostic
Main MOSn
41V
OUTn
ILoff2r
RSENSE
RPROT
To uC ADC
RPD
RPU
VPU
Pwr_Lim
VSENSE
PU_CMD
Overtemperature
OL OFF
+
-
VOL
CURRENT
SENSEn
IOUT/KX
ISENSEH
VBAT
ILoff2f
VSENSEH
Load
INPUTn
VCC
GND
CS_DIS
VND5E160AJ-E Application information
27/37
3.4.1 Short to VCC and OFF state open load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off state. Small or no current is delivered by the current sense
during the on state depending on the nature of the short circuit.
OFF state open load with external circuitry
Detection of an open load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module stand-by mode in order to avoid the
overall stand-by current consumption to increase in normal conditions, i.e. when load is
connected.
An external pull down resistor RPD connected between output and GND is mandatory to
avoid misdetection in case of floating outputs in off state (see Figure 33: Current sense and
diagnostic).
RPD must be selected in order to ensure VOUT < VOLmin unless pulled up by the external
circuitry:
RPD ≤ 22 KΩ is recommended.
For proper open load detection in off state, the external pull-up resistor must be selected
according to the following formula:
For the values of VOLmin ,VOLmax, IL(off2)r and IL(off2)f see Table 10: Openload detection
(8V<VCC<18V).
VVIRV OLfoffLPD
OFFupPull
OUT 2
min)2(
_=<⋅=
−
VV
RR
IRRVR
VOL
PDPU
roffLPDPUPUPD
ONupPull
OUT 4
max
)2(
_=>
+
⋅⋅
−
⋅
=
−
Application information VND5E160AJ-E
28/37
3.5 Maximum demagnetization energy (VCC = 13.5V)
Figure 34. Maximum turn-Off current versus inductance (for each channel)
Note: Values are generated with RL=0 Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
0,1
1
10
100
0,1 1 10 100L (mH)
I (A)
Demagnetization Demagnetization Demagnetization
t
VIN, IL
C:
T
jstart
= 125°C repetitive pulse
A:
T
jstart
= 150°C single pulse
B: T
jstart
= 100°C repetitive pulse
A
B
C
VND5E160AJ-E Package and PC board thermal data
29/37
4 Package and PC board thermal data
4.1 PowerSSO-12 thermal data
Figure 35. PowerSSO-12 PC board
Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 36.
R
thj-amb
vs. PCB copper area in open box free air condition (one channel ON)
40
45
50
55
60
65
70
0246810
RTHj_amb(°C/W)
PCB Cu heatsink area (cm^2)
Package and PC board thermal data VND5E160AJ-E
30/37
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel ON)
Equation 1: pulse calculation formula
where δ = tP/T
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 (a)
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
1
10
100
0,001 0,01 0,1 1 10 100 1000
Time (s)
ZTH (°C/W)
Footprint
8 cm2
2 cm2
ZTHδRTH δZTHtp 1δ–()+⋅=
VND5E160AJ-E Package and PC board thermal data
31/37
Table 13. Thermal parameters
Area/island (cm2)Footprint28
R1= R7 (°C/W) 1.2
R2= R8 (°C/W) 6
R3 (°C/W) 3
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1= C7 (W.s/°C) 0.0008
C2= C8 (W.s/°C) 0.0016
C3 (W.s/°C) 0.0166
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
Package and packing information VND5E160AJ-E
32/37
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2 Package mechanical data
Figure 39. PowerSSO-12 package dimensions
VND5E160AJ-E Package and packing information
33/37
Table 14. PowerSSO-12 mechanical data
Symbol
Millimeters
Min. Typ. Max.
A 1.250 1.620
A1 0.000 0.100
A2 1.100 1.650
B 0.230 0.410
C 0.190 0.250
D 4.800 5.000
E 3.800 4.000
e0.800
H 5.800 6.200
h 0.250 0.500
L 0.400 1.270
k0° 8°
X 2.200 2.800
Y 2.900 3.500
ddd 0.100
Package and packing information VND5E160AJ-E
34/37
5.3 Packing information
Figure 40. PowerSSO-12 tube shipment (no suffix)
Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A1.85
B6.75
C (± 0.1) 0.6
A
C
B
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
saled with cover tape.
User direction of feed
VND5E160AJ-E Order codes
35/37
6 Order codes
Table 15. Device summary
Package Order codes
Tube Tape and reel
PowerSSO-12 VND5E160AJ-E VND5E160AJTR-E
Revision history VND5E160AJ-E
36/37
7 Revision history
Table 16. Document revision history
Date Revision Changes
13-Sep-2004 1 Initial release.
14-Mar-2008 2
Document reformatted and restructured.
Updated Figure 2: Configuration diagram (top view) : pins 7-12 left
unconnected (N.C) .
Updated Table 9: Current sense (8V<VCC<18V):
– added k, dk/k, tDSENSE1H, tDSENSE1L, tDSENSE2H, ∆tDSENSE2H,
tDSENSE2L values
Updated Table 10: Openload detection (8V<VCC<18V):
– added IL(off2)r, IL(off2)f and td_vol parameters
Added Figure 7: Delay response time between rising edge of ouput
current and rising edge of current sense (CS enabled).
Added Figure 9: Iout/ Isense vs. Iout.
Added Figure 10: Maximum current sense ratio drift vs load current.
Table 12: Electrical transient requirements : updated test level values
III and IV for test pulse 5b and notes.
Added Section 2.4: Waveforms.
Added Section 2.5: Electrical characteristics curves.
Updated Section 3: Application information:
– added Section 3.4: Current sense and diagnostic
Updated Section 4.1: PowerSSO-12 thermal data:
– changed Figure 36: Rthj-amb vs. PCB copper area in open box
free air condition (one channel ON).
– added Figure 37: PowerSSO-12 thermal impedance junction
ambient single pulse (one channel ON).
–Figure 38: Thermal fitting model of a double channel HSD in
PowerSSO-12 : added note.
– updated Table 13: Thermal parameters:
R3 value changed from 7 to 3 °C/W.
R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W.
C3 value changed from 0.05 to 0.0166 W.s/°C.
VND5E160AJ-E
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