MAX16993AGJG/VY+T - Maxim Integrated

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

General Description

The MAX16993 power-management integrated circuit

(PMIC) is a 2.1MHz, multichannel, DC-DC convert-

er designed for automotive applications. The device

integrates three supplies in a small footprint. The device

includes one high-voltage step-down controller (OUT1)

designed to run directly from a car battery and two low-

voltage step-down converters (OUT2/OUT3) cascaded

from OUT1. Under no-load conditions, the MAX16993

consumes only 30µA of quiescent current, making it ideal

for automotive applications.

The high-voltage synchronous step-down DC-DC

controller (OUT1) operates from a voltage up to 36V

continuous and is protected from load-dump transients up

to 42V. There is a pin-selectable frequency option of either

2.1MHz or a factory-set frequency for 1.05MHz, 525kHz,

420kHz, or 350kHz. The low-voltage, synchronous step-

down DC-DC converters run directly from OUT1 and can

supply output currents up to 3A.

The device provides a spread-spectrum enable input

(SSEN) to provide quick improvement in electromagnetic

interference when needed. There is also a SYNC

input for providing an input to synchronize to

an external clock source (see the Selector Guide).

The device includes overtemperature shutdown and

overcurrent limiting. The device also includes indi-

vidual RESET_ outputs and individual enable inputs.

The individual RESET_ outputs provide voltage

monitoring for all output channels.

The MAX16993 is available in a 32-pin TQFN/side-

wettable QFND-EP package and is specified for operation

over the -40°C to +125°C automotive temperature range.

Applications

● Automotive

● Industrial

Benets and Features

● High-Efficiency Voltage DC-DC Controller Saves

Power

• 3.5V to 36V Operating Supply Voltage

• Output Voltage: Pin Selectable, Fixed, or

Resistor-Divider Adjustable

• 350kHz to 2.1MHz Operation

• 30μAQuiescentCurrentwithDC-DC

Controller Enabled

● Dual 2.1MHz DC-DC Converters with Integrated

FETs Save Space

• OUT2 and OUT3 are Cascaded from OUT1,

Improving Efficiency

• 3A Integrated FETs

• 0.8V to 3.95V Output Voltage

• Fixed or Resistor-Divider-Adjustable Output Voltage

• 180° Out-of-Phase Operation

• Robust for the Automotive Environment

● Current-Mode Architecture with Forced-PWM and

Skip Modes of Operation

• Frequency Synchronization Input/Output Reduces

System Noise

• Individual Enable Inputs and RESET_ Outputs

• Overtemperature and Short-Circuit Protection

• AECQ-100Qualied

• 32-Pin TQFN-EP (5mm x 5mm x 0.75mm) and

Side-Wettable QFND-EP (5mm x 5mm x 0.8mm)

• -40°C to +125°C Operating Temperature Range

19-6684; Rev 14; 12/16

Ordering Information and Selector Guide appear at end of

data sheet.

EVALUATION KIT AVAILABLE

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

www.maximintegrated.com Maxim Integrated

│

Electrical Characteristics

(VSUP = 14V, VPV1 = VBIAS, VPV2 = VPV3 = VOUT1; TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at

TA = +25°C under normal conditions, unless otherwise noted.) (Note 3)

Note 1: Self-protected against transient voltages exceeding these limits for ≤ 50ns under normal operation and loads up to the

maximum rated output current.

Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Thermal Characteristics (Note 2)

Side-Wettable QFND

Junction-to-AmbientThermalResistance(θJA) ......... 37°C/W

 Junction-to-CaseThermalResistance(θJC) ............ 2.8°C/W

TQFN

Junction-to-AmbientThermalResistance(θJA) ......... 29°C/W

 Junction-to-CaseThermalResistance(θJC) ............ 1.7°C/W

VSUP, EN1 to GND ...............................................-0.3V to +45V

PV_ to GND..........................................................-0.3V to +6.0V

PV2 to GND, PV2 to PGND2 ...............................-0.3V to +6.0V

PV3 to GND, PV3 to PGND3 ...............................-0.3V to +6.0V

PGND2–PGND3 to GND......................................-0.3V to +0.3V

LX1 to GND ...............................................-6.0V to VSUP + 6.0V

BST1 to LX1 (Note 1) ........................................... -0.3V to +6.0V

DH1 to LX1 (Note 1)..................................-0.3V to BST1 + 0.3V

BIAS to GND ........................................................-0.3V to +6.0V

DL1 to GND (Note 1)...................................-0.3V to PV1 + 0.3V

LX2 to PGND2.............................................-0.3V to PV2 + 0.3V

LX3 to PGND3.............................................-0.3V to PV3 + 0.3V

OUT1, CS1, OUT2, OUT3 to GND ......................-0.3V to +6.0V

SYNC to GND .............................................-0.3V to PV_ + 0.3V

FB1, EN2, EN3 to GND........................................-0.3V to +6.0V

RESET_, ERR to GND .........................................-0.3V to +6.0V

CS1 to OUT1 ........................................................ -0.3V to +0.3V

CSEL1, SSEN to GND .........................................-0.3V to +6.0V

COMP1 to GND... ..........................................-0.3V to PV + 0.3V

LX2, LX3 Output Short-Circuit Duration .................... Continuous

Continuous Power Dissipation (TA = +70ºC)

Side-Wettable QFND (derate 27mW/ºC above +70ºC)......2160mW

TQFN (derate 34.5mW/ºC above +70ºC)...............2758.6mW

Operating Temperature Range ..........................-40ºC to +125°C

Junction Temperature ...................................................... +150°C

Storage Temperature Range .............................-65ºC to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) ....................................... +260°C

Absolute Maximum Ratings

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage Startup

Threshold

VSUP,STARTUP

VSUP rising 4.25 4.5 4.75 V

Supply Voltage Range VSUP Normal operation, after Buck 1 startup 3.5 36 V

Supply Current ISUP

VEN1 = VEN2 = VEN3 = 0V 4 15 µA

VEN1 = 5V, VEN2 = VEN3 = 0V (no load) 20 40

Oscillator Frequency fSW 2.0 2.1 2.2 MHz

SYNC Input Frequency

Range 1.7 2.4 MHz

Spread-Spectrum Range VSSEN = VGND 0%

VSSEN = VBIAS +6

BIAS Regulator Voltage VBIAS 6V≤VSUP≤42V,noswitchover 4.6 5.0 5.4 V

PV_ POR VBIAS falling 2.5 2.7 2.9 V

Hysteresis 0.45

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

www.maximintegrated.com Maxim Integrated

│

Electrical Characteristics (continued)

(VSUP = 14V, VPV1 = VBIAS, VPV2 = VPV3 = VOUT1; TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at

TA = +25°C under normal conditions, unless otherwise noted.) (Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OUT1: HIGH-VOLTAGE SYNCHRONOUS STEP-DOWN DC-DC CONTROLLER

OUT1 Switching Frequency fSW1

Internally generated

(see the Selector

Guide)

VCSEL1 = VGND 2100

kHz

VCSEL1 = VBIAS

(factory option) 1050

VCSEL1 = VBIAS

(factory option) 525

VCSEL1 = VBIAS

(factory option) 420

VCSEL1 = VBIAS

(factory option) 350

Voltage VOUT1

Fixed option

(see the Selector

Guide)

VFB1 = VGND 3.3

VFB1 = VBIAS

(factory option) 5.0

VFB1 = VBIAS

(factory option) 3.15

FB1 Regulation Voltage Adjustable option (see the Selector Guide) 0.985 1.0 1.019 V

ErrorAmplier

Transconductance gMEA 300 700 1200 µS

Voltage Accuracy VOUT1 5.5V≤VSUP≤18V,0<VLIM1<75mV,

PWM mode -2.0 +2.5 %

DC Load Regulation PWM mode 0.02 %/A

DC Line Regulation PWM mode 0.03 %/V

OUT1 Discharge Resistance VEN1 = VGND or VSUP 100 200 Ω

High-Side Output Drive

Resistance

VDH1 rising, IDH1 = 100mA 2 4 Ω

VDH1 falling, IDH1 = 100mA 1 4

Low-Side Output Drive

Resistance

VDL1 rising, IDL1 = 100mA 2.5 5 Ω

VDL1 falling, IDL1 = 100mA 1.5 3

Output Current-Limit

Threshold VLIM1 CSI – OUT1 100 120 150 mV

Skip Current Threshold ISKIP CS1 – OUT1, no load 10 35 60 mV

Soft-Start Ramp Time 4 ms

LX_ Leakage Current VLX1 = VSUP 0.01 µA

Duty-Cycle Range PWM mode 97.2 %

Minimum On-Time 60 75 ns

OUT1 OV Threshold 107 110 113 %

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

www.maximintegrated.com Maxim Integrated

│

Electrical Characteristics (continued)

(VSUP = 14V, VPV1 = VBIAS, VPV2 = VPV3 = VOUT1; TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at

TA = +25°C under normal conditions, unless otherwise noted.) (Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OUT2 AND OUT3: LOW-VOLTAGE SYNCHRONOUS STEP-DOWN DC-DC CONVERTERS

Supply Voltage Range VSUP 2.7 5.5 V

Supply Current IPV_ VEN_ = 5V, no load 0.1 5 µA

Skip Mode Peak Current 0.2 x ILMAX mA

Voltage Accuracy VOUT 0A≤ILOAD≤IMAX, PWM mode -3.0 +3.0 %

Feedback-Voltage Accuracy Adjustable mode, IOUT2 = 0mA 0.806 0.815 0.824 V

Load Regulation

0A≤ILOAD≤IMAX (PWM mode) -1.5 -1.0

0A≤ILOAD≤IMAX (PWM mode, low gain,

see the Selector Guide)

-2.5 -1.7

LX_ On-Resistance High ILX_ = -800mA 70 110 mΩ

LX_ On-Resistance Low ILX_ = 800mA 50 90 mΩ

Current-Limit Threshold ILMAX

IMAX = 3.0A option (see the Selector Guide)

5.0 5.6 A

IMAX = 1.5A option (see the Selector Guide)

2.5 3.0

LX_ Rise/Fall Time PV2 = PV3 = 3.3V, IOUT_ = 2A 4 ns

Soft-Start Ramp Time 2.5 ms

LX_ Leakage Current 0.01 µA

Duty-Cycle Range PWM mode 15 100 %

LX_ Discharge Resistance 22 48 Ω

RESET_

Reset Threshold Rising (relative to nominal output voltage) 92 95 98 %

Falling (relative to nominal output voltage) 90 92 95

OUT1 Active Timeout Period

See the Selector Guide

(16,384 clocks) 7.8

See the Selector Guide

(8192 clocks) 3.9

See the Selector Guide

(4096 clocks) 1.9

See the Selector Guide

(256 clocks) 0.1

OUT2, OUT3 Active

Timeout Period

See the Selector Guide

(16,384 clocks) 7.8

See the Selector Guide

(8192 clocks) 3.9

See the Selector Guide

(4096 clocks) 1.9

See the Selector Guide

(256 clocks) 0.1

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

www.maximintegrated.com Maxim Integrated

│

Electrical Characteristics (continued)

(VSUP = 14V, VPV1 = VBIAS, VPV2 = VPV3 = VOUT1; TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at

TA = +25°C under normal conditions, unless otherwise noted.) (Note 3)

Note 3: All units are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Low Level ISINK = 3mA 0.1 0.2 V

Propagation Time OUT1, 5% below threshold 5 10 20 µs

OUT2/OUT3, 5% below threshold 2 4 8 µs

ERR

Output Low Level ISINK = 3mA 0.1 0.2 V

THERMAL OVERLOAD

Thermal-Warning

Temperature +150 °C

Thermal-Shutdown

Temperature +170 °C

Thermal-Shutdown

Hysteresis 15 °C

ENABLE INPUTS (EN_)

Input High VEN_ rising 1.6 1.8 2.0 V

Hysteresis 0.2 V

EN Input Current VEN_ = 5V 0.5 1.0 2.0 µA

SYNCHRONIZATION I/O (SYNC)

Input High SYNC input option

(see the Selector Guide)1.8 V

Input Low SYNC input option

(see the Selector Guide)0.8 V

Input Current SYNC input option (see the Selector

Guide); VSYNC = 5V 50 80 µA

Pulldown Resistance 100 kΩ

LOGIC INPUTS (CSEL1, SSEN)

Input High 1.4 V

Input Low 0.5 V

Input Current TA = +25°C 2 µA

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

Maxim Integrated

│

www.maximintegrated.com

Typical Operating Characteristics

(VSUP = 14V, TA = +25°C, unless otherwise noted)

BUCK 2 LOAD REGULATION (PWM MODE)

MAX16993 toc09

IOUT2 (A)

VOUT2 (V)

1.41.20.8 1.00.4 0.60.2

3.09

3.10

3.11

3.12

3.13

3.14

3.15

3.16

3.17

3.18

3.19

3.08

0 1.6

TA = +125ºC

TA = +25ºC

TA = -40ºC

VPV2 = 5.0V, IMAX = 1.5A, VOUT2 = 3.15V

BUCK 2 EFFICIENCY

MAX16993 toc08

IOUT3 (A)

EFFICIENCY (%)

1.00E-021.00E-04

100

1.00E-06 1.00E+00

SKIP MODE

PWM MODE

fSW = 2.1MHz,

VSUP = 14V,

VPV2 = 5.0V,

VOUT2 = 3.15V

VOUT1 vs. TEMPERATURE

MAX16993 toc07

TEMPERATURE (ºC)

VOUT1 (V)

100500

4.985

4.990

4.995

5.000

5.005

5.010

5.015

5.020

5.025

5.030

4.980

-50 150

IOUT1 = 3.75A

BUCK 1 LINE REGULATION (SKIP MODE)

MAX16993 toc06

VSUP (V)

VOUT1 (% NOMINAL)

35305 10 15 20 25

99.7

99.9

100.1

100.3

100.5

100.7

100.9

99.5

0 40

VOUT1 = 3.3V

BUCK 1 LINE REGULATION (SKIP MODE)

MAX16993 toc05

VSUP (V)

VOUT1 (% NOMINAL)

353020 2510 155

99.2

99.4

99.6

99.8

100.0

100.2

100.4

100.6

100.8

101.0

99.0

0 40

VOUT1 = 5.0V

BUCK 1 LINE REGULATION (PWM MODE)

MAX16993 toc04

VSUP (V)

VOUT1 (% NOMINAL)

353020 2510 155

99.6

99.7

99.8

99.9

100.0

100.1

100.2

100.3

100.4

100.5

99.5

0 40

VOUT1 = 5.0V

TA = +125ºC

TA = +25ºC

TA = -40ºC

BUCK 1 LOAD REGULATION (SKIP)

MAX16993 toc03

IOUT1 (A)

VOUT1 (V)

54321

4.92

4.94

4.96

4.98

5.00

5.02

5.04

5.06

5.08

5.10

4.90

0 6

TA = +125ºC

TA = +25ºC

TA = -40ºC

BUCK 1 LOAD REGULATION (PWM)

MAX16993 toc02

IOUT1 (A)

VOUT1 (V)

541 2 3

4.995

5.000

5.005

5.010

5.015

5.020

5.025

5.030

4.990

0 6

TA = +125ºC

TA = +25ºC

TA = -40ºC

BUCK 1 EFFICIENCY

MAX16993 toc01

IOUT1 (A)

EFFICIENCY (%)

1.00E-021.00E-04

100

1.00E-06 1.00E+00

SKIP MODE

PWM MODE

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

Maxim Integrated

│

www.maximintegrated.com

Typical Operating Characteristics (continued)

(VSUP = 14V, TA = +25°C, unless otherwise noted)

VOUT3 vs. TEMPERATURE

MAX16993 toc17

TEMPERATURE (ºC)

VOUT3 (V)

100500

1.785

1.790

1.795

1.800

1.805

1.810

1.780

-50 150

IOUT3 = 1.125A

BUCK 3 LINE REGULATION (PWM MODE)

MAX16993 toc16

VPV3 (V)

VOUT3 (% NOMINAL)

5.34.84.33.8

99.6

99.7

99.8

99.9

100.0

100.1

100.2

100.3

100.4

100.5

99.5

3.3

VOUT3 = 1.8V

TA = -40ºC

TA = +125ºC

TA = +25ºC

BUCK 3 LOAD REGULATION (PWM MODE)

MAX16993 toc15

IOUT3 (A)

VOUT3 (V)

3.02.50.5 1.0 1.5 2.0

1.216

1.218

1.220

1.222

1.224

1.226

1.228

1.230

1.214

0 3.5

VPV3 = 5.0V

IMAX = 3A

VOUT3 = 1.2V

BUCK 3 LOAD REGULATION (PWM MODE)

VOUT3 (V)

1.78

1.79

1.80

1.81

1.82

1.83

MAX16993 toc14

IOUT3 (A)

1.41.21.00.80.60.40.2

1.77

0 1.6

TA = +125ºC

TA = +25ºC

TA = -40ºC

VPV3 = 5.0V, IMAX = 1.5A, VOUT3 = 1.8V

BUCK 3 EFFICIENCY

MAX16993 toc13

IOUT3 (A)

EFFICIENCY (%)

1.00E-021.00E-04

100

1.00E-06 1.00E+00

SKIP MODE

PWM MODE

fSW = 2.1MHz,

VSUP = 14V,

VPV3 = 5.0V,

VOUT3 = 1.8V

VOUT2 vs. TEMPERATURE

MAX16993 toc12

TEMPERATURE (ºC)

VOUT2 (V)

100500

3.105

3.110

3.115

3.120

3.125

3.130

3.135

3.140

3.145

3.150

3.100

-50 150

IOUT2 = 1.125A

BUCK 2 LINE REGULATION (PWM MODE)

MAX16993 toc11

VPV2 (V)

VOUT2 (% NOMINAL)

5.24.74.23.73.2

99.2

99.4

99.6

99.8

100.0

100.2

100.4

100.6

100.8

101.0

99.0

2.7 5.7

VOUT2 = 3.15V

TA = -40ºC

TA = +125ºC

TA = +25ºC

BUCK 2 LOAD REGULATION (PWM MODE)

MAX16993 toc10

IOUT2 (A)

VOUT2 (V)

3.02.52.01.51.00.5

3.315

3.320

3.325

3.330

3.335

3.340

3.345

3.310

0 3.5

VPV2 = 5.0V

IMAX = 3A

VOUT2 = 3.3V

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

Maxim Integrated

│

www.maximintegrated.com

Typical Operating Characteristics (continued)

(VSUP = 14V, TA = +25°C, unless otherwise noted)

SPECTRAL ENERGY DENSITY

MAX16993 toc24

FREQUENCY (MHz)

OUTPUT SPECTRUM (dBµV)

2.252.202.152.102.052.001.95

-10

1.90 2.30

SS DISABLED

SS ENABLED

SHUTDOWN CURRENT

vs. SUPPLY VOLTAGE

MAX16993 toc23

VSUP (V)

SHUTDOWN CURRENT (µA)

353020 2510 155

0 40

TA = +125ºC

TA = +25ºC

TA = -40ºC

VEN1 = VEN2 = VEN3 = VGND

MEASURED AT VSUP

fSW vs. TEMPERATURE

MAX16993 toc22

TEMPERATURE (ºC)

SWITCHING FREQUENCY (% NOMINAL)

100500

100

101

102

103

-50 150

fSW = 2.1MHz

LOAD TRANSIENT RESPONSE (PWM MODE)

MAX16993 toc21

200µs/div

VOUT1

IOUT1

100mV/div

1A/div

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX16993 toc20

VSUP (V)

SUPPLY CURRENT (µA)

3530252015105

0 40

TA = +125ºC

TA = +25ºC

TA = -40ºC

VOUT1 = 5.0V, SKIP MODE

ONLY BUCK CONTROLLER ENABLED

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX16993 toc19

VSUP (V)

SUPPLY CURRENT (µA)

3530252015105

100

120

0 40

TA = +125ºC

TA = +25ºC

TA = -40ºC

VFB = VGND

SKIP MODE

ALL THREE BUCKS ENABLED

MEASURED AT VSUP

STARTUP SEQUENCE

(VEN2 = VEN3 = VOUT1)

MAX16993 toc18

2ms/div

VEN1

VOUT1

VRESET1

VOUT2

VRESET2

VOUT3

VRESET3

5V/div

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

www.maximintegrated.com Maxim Integrated

│

Pin Description

Pin Conguration

PIN NAME FUNCTION

1 PV1 Supply Input for Buck 1 Low-Side Gate Drive. Connect a ceramic bypass capacitor of at least 0.1µF from PV1

to GND.

2 DL1 Low-Side Gate-Drive Output for Buck 1. DL1 output voltage swings from VGND to VPV1.

3 GND Power Ground for Buck 1

4 LX1 Inductor Connection for Buck 1. Connect LX1 to the switched side of the inductor. LX1 serves as the lower

supply rail for the DH1 high-side gate drive.

5 DH1 High-Side Gate-Drive Output for Buck 1. DH1 output voltage swings from VLX1 to VBST1.

6 BST1

Bootstrap Capacitor Connection for High-Side Gate Drive of Buck 1. Connect a high-voltage diode between

BIAS and BST1. Connect a ceramic capacitor between BST1 and LX1. See the High-Side Gate-Drive Supply

(BST1) section.

7 VSUP Supply Input. Bypass VSUP with a minimum 0.1µF capacitor as close as possible to the device.

8 EN1 High-Voltage Tolerant, Active-High Digital Enable Input for Buck 1. Driving EN1 high enables Buck 1.

9 BIAS

5V Internal Linear Regulator Output. Bypass BIAS to GND with a low-ESR ceramic capacitor of

2.2µF minimum value. BIAS provides the power to the internal circuitry. See the Linear Regulator (BIAS)

section.

10 PV AnalogSupply.ConnectPVtoBIASthrougha10Ωresistorandconnecta1µFceramiccapacitorfromPVto

ground.

11 FB1

FeedbackInputforBuck1.Forthexedoutput-voltageoption,connectFB1toBIASforthefactory-trimmed

(3.0Vto3.75Vor4.6Vto5.35V)xedoutput.ConnectFB1toGNDforthe3.3Vxedoutput.Fortheresistor-

divider adjustable output-voltage option, connect FB1 to a resistive divider between OUT1 and GND to adjust

the output voltage between 3.0V and 5.5V. In adjustable mode, FB1 regulates to 1.0V (typ). See the OUT1

Adjustable Output-Voltage Option section.

MAX16993

TQFN/SIDE-WETTABLE QFND

TOP VIEW

DL1

LX1

DH1

BST1

VSUP

PV1

PV2

PGND2

PGND3

RESET2

LX3

PV3

RESET1

4567

2324 22 20 19 18

GND

COMP1

EP = GND

EN2

OUT1

CS1

FB1

GND LX2

31 10

ERR PV

32 9

SYNC BIAS

SSEN

26 15 EN3

CSEL1

25 16 OUT3

EN1 RESET3

OUT2

MAX16993 Step-Down Controller with

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Pin Description (continued)

PIN NAME FUNCTION

12 CS1 Positive Current-Sense Input for Buck 1. Connect CS1 to the positive terminal of the current-sense resistor.

See the Current-Limit/Short-Circuit Protection and Current-Sense Measurement sections.

13 OUT1

Output Sense and Negative Current-Sense Input for Buck 1. The buck uses OUT1 to sense the output

voltage. Connect OUT1 to the negative terminal of the current-sense resistor.

See the Current-Limit/Short-Circuit Protection and Current-Sense Measurement sections.

14 EN2 Active-High Digital Enable Input for Buck 2. Driving EN2 high enables Buck 2.

15 EN3 Active-High Digital Enable Input for Buck 3. Driving EN3 high enables Buck 3.

16 OUT3

Buck Converter 3 Voltage-Sense Input. Connect OUT3 to the output of Buck 3. Connect OUT3 to an external

feedback divider when setting DC-DC3 voltage externally. See the OUT2/OUT3 Adjustable Output-Voltage

Option section.

17 RESET3

Open-Drain Buck 3 Reset Output. RESET3remainslowforaxedtimeaftertheoutputofBuck3has

reached its regulation level (see the Selector Guide). To obtain a logic signal, pull up RESET3 with an

external resistor connected to a positive voltage lower than 5V.

18 PV3 Buck 3 Voltage Input. Connect a 2.2µF or larger ceramic capacitor from PV3 to PGND3. Connect PV3 to OUT1.

19 LX3 Buck 3 Switching Node. LX3 is high impedance when the device is off.

20 PGND3 Power Ground for Buck 3

21 PGND2 Power Ground for Buck 2

22 LX2 Buck 2 Switching Node. LX2 is high impedance when the device is off.

23 PV2 Buck 2 Voltage Input. Connect a 2.2µF or larger ceramic capacitor from PV2 to PGND2. Connect PV2 to OUT1.

24 RESET2

Open-DrainBuck2ResetOutput.ThisoutputremainslowforaxedtimeaftertheoutputofBuck2has

reached its regulation level (see the Selector Guide). To obtain a logic signal, pull up RESET2 with an

external resistor connected to a positive voltage lower than 5V.

25 OUT2

Buck Converter 2 Voltage-Sense Input. Connect OUT2 to the output of Buck 2. Connect OUT2 to an external

feedback divider when setting DC-DC2 voltage externally. See the OUT2/OUT3 Adjustable Output-Voltage

Option section.

26 CSEL1 Buck 1 Clock Select. Connect CSEL1 to GND for 2.1MHz operation. Connect CSEL1 to BIAS for an OTP-

programmable divide-down operation. See the Selector Guide for the fSW1 divide ratio.

27 SSEN Spread-Spectrum Enable. Connect SSEN to GND for standard oscillator operation. Connect SSEN to BIAS to

enable the spread-spectrum oscillator.

28 RESET1

Open-Drain Buck 1 Reset Output. RESET1remainslowforaxedtimeaftertheoutputofBuck1has

reached its regulation level (see the Selector Guide). To obtain a logic signal, pull up RESET1 with an

external resistor connected to a positive voltage lower than 5V.

29 GND Analog Ground

30 COMP1 Compensation for Buck 1. See the Compensation Network section.

31 ERR Open-Drain Error-Status Output. ERR signals a thermal-warning/shutdown condition. To obtain a logic signal,

pull up ERR with an external resistor connected to a positive voltage lower than 5V.

32 SYNC

Synchronization Input. SYNC allows the device to synchronize to other supplies. Connect SYNC to GND or

leave unconnected to enable skip-mode operation under light loads. Connect SYNC to BIAS or an external

clocktoenablexed-frequencyforced-PWM-modeoperation.

— EP

Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not remove

the requirement for proper ground connections to PGND2–PGND3 and GND. The exposed pad is attached

with epoxy to the substrate of the die, making it an excellent path to remove heat from the IC.

MAX16993 Step-Down Controller with

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Typical Operating Circuit

VOUT1

VBATP

LINEAR

REGULATOR

MAX16993

STEP-DOWN

CONTROLLER

OUT1

STEP-DOWN

PWM

OUT3

0.8V TO 3.95V

1.5A TO 3.0A

BIAS

DH1

PV1

BIAS

PV3

LX3 VOUT3

VOUT1

PGND3

OUT3

PV2

LX2 VOUT2

VOUT1

PGND2

OUT2

LX1

GND

CS1

OUT1

FB1

PWM EN

PWM

POR

GENERATION

AND

CONTROL

COMP1

RESET1

DL1

GND

BST1

VSUP

RESET2

RESET3

EN1

EN2

EN3

ERR

SSEN

CSEL1

SYNC

STEP-DOWN

PWM

OUT2

0.8V TO 3.95V

1.5A TO 3.0A

MAX16993 Step-Down Controller with

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Detailed Description

The MAX16993 power-management integrated circuit

(PMIC) is a 2.1MHz, multichannel, DC-DC converter

designed for automotive applications. The device includes

one high-voltage step-down controller (OUT1) designed

to run directly from a car battery and two low-voltage step-

down converters (OUT2/OUT3) cascaded from OUT1.

The 2.1MHz, high-voltage buck controller operates with

a 3.5V to 36V input voltage range and is protected from

load-dump transients up to 42V. The high-frequency

operation eliminates AM band interference and reduces

the solution footprint. It can provide an output voltage

between 3.0V and 5.5V set at the factory or with external

resistors. Each device has two frequency options that

are pin selectable: 2.1MHz or a lower frequency based

on factory setting. Available factory-set frequencies are

1.05MHz, 525kHz, 420kHz, or 350kHz. Under no-load

conditions, the device consumes only 30µA of quiescent

current with OUT1 enabled.

The dual buck converters can deliver 1.5A or 3.0A of

load current per output. They operate directly from OUT1

and provide 0.8V to 3.95V output voltage range. Factory

trimmed output voltages achieve ±3% output error over

load, line, and temperature without using expensive

±0.1% resistors. In addition, adjustable output-voltage

versions can be set to any desired values between 0.8V

and 3.6V using an external resistive divider. On-board

low RDS(ON) switches help minimize efficiency losses

at heavy loads and reduce critical/parasitic inductance,

making the layout a much simpler task with respect to

discrete solutions. Following a simple layout and footprint

ensures first-pass success in new designs (see the PCB

Layout Guidelines section).

The device features a SYNC input (see the Synchronization

(SYNC) section and the Selector Guide). An optional

spread-spectrum frequency modulation minimizes radi-

ated electromagnetic emissions due to the switching

frequency, and a factory-programmable synchronization

I/O (SYNC) allows better noise immunity. Additional fea-

tures include a 4ms fixed soft-start for OUT1 and 2.5ms

for OUT2/OUT3, individual RESET_ outputs, overcurrent,

and overtemperature protections. See the Selector Guide

for the available options.

Enable Inputs (EN_)

All three regulators have their own enable input. When

EN1 exceeds the EN1 high threshold, the internal

linear regulator is switched on. When VSUP exceeds the

VSUP,STARTUP threshold, Buck 1 is enabled and OUT1

starts to ramp up with a 4ms soft-start. Once the Buck 1

soft-start is complete, Buck 2 and Buck 3 can be enabled.

When either Buck 2 or Buck 3 is enabled, the correspond-

ing output ramps up with a 2.5ms soft-start. When an

enable input is pulled low, the converter is switched off

and the corresponding OUT_ and RESET_ are driven

low. If EN1 is low, all regulators are disabled.

Reset Outputs (RESET_)

The device features individual open-drain RESET_ out-

puts for each buck output that asserts when the buck

output voltage drops 6% below the regulated voltage.

RESET_ remains asserted for a fixed timeout period after

the buck output rises up to its regulated voltage. The

fixed timeout period is programmable between 0.1ms and

7.4ms (see the Selector Guide). To obtain a logic signal,

pull up RESET_ with an external resistor connected to a

positive voltage lower than 5V.

Linear Regulator (BIAS)

The device features a 5V internal linear regulator (BIAS).

Connect BIAS to PV, which acts as a supply for internal

circuitry. Also connect BIAS to PV1, which acts as a

supply for the low-side gate driver of Buck 1. Bypass BIAS

as close as possible to the device with a 2.2µF or larger

ceramic capacitor. BIAS can provide up to 100mA (max),

but is not designed to supply external loads. After OUT1

completes soft-start, BIAS LDO is turned off and the BIAS

pin is shorted to the OUT1 pin internally to power the

internal circuits (e.g., if OUT1 is set to 3.3V, BIAS transi-

tions from 5V to 3.3V after soft-start).

Internal Oscillator

Buck 1 Clock Select (CSEL1)

The device offers a Buck 1 clock-select input. Connect

CSEL1 to GND for 2.1MHz operation. Connect CSEL1 to

BIAS to divide down the Buck 1 clock frequency by 2, 4, 5,

or 6 (see the Selector Guide). Buck 2 and Buck 3 switch

at 2.1MHz (typ) and are not controlled by CSEL1.

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Spread-Spectrum Enable (SSEN)

The device features a spread-spectrum enable (SSEN)

input that can quickly enable spread-spectrum operation

to reduce radiated emissions. Connect SSEN to BIAS to

enable the spread-spectrum oscillator. Connect SSEN

to GND for standard oscillator operation. When spread

spectrum is enabled, the internal oscillator frequency

is varied between fSW and (fSW + 6%). The change in

frequency has a sawtooth shape and a frequency of 4kHz

(see Figure 1). This function does not apply to externally

applied oscillation frequency. See the Selector Guide for

available options.

Synchronization (SYNC)

SYNC is factory-programmable I/O. See the Selector

Guide for available options. When SYNC is configured as

an input, a logic-high on SYNC enables fixed-frequency,

forced-PWM mode. Apply an external clock on the SYNC

input to synchronize the internal oscillator to an external

clock. The SYNC input accepts signal frequencies in the

rangeof1.7MHz<fSYNC<2.4MHz.Theexternalclock

should have a duty cycle of 50%. A logic-low at the SYNC

input enables the device to enter a low-power skip mode

under light-load conditions.

Common Protection Features

Undervoltage Lockout

The device offers an undervoltage-lockout feature.

Undervoltage detection is performed on the PV input. If

VSUP decreases to the point where Buck 1 is in drop-

out, PV begins to decrease. If PV falls below the UVLO

threshold (2.7V, typ), all three converters switch off and

the RESET_ outputs assert low. Once the device has

been switched off, VSUP must exceed the VSUP,STARTUP

threshold before Buck 1 turns back on.

Output Overvoltage Protection

The device features overvoltage protection on the buck

converter outputs. If the FB1 input exceeds the output

overvoltage threshold, a discharge current is switched on

at OUT1 and RESET1 asserts low.

Figure 1. Effect of Spread Spectrum on Internal Oscillator

fSW + 6%

fSW

tt + 250µs t + 500µs t + 750µs

INTERNAL OSCILLATOR

FREQUENCY

TIME

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Soft-Start

The device includes a 4ms fixed soft-start time on OUT1

and 2.5ms fixed soft-start time on OUT2/OUT3. Soft-start

time limits startup inrush current by forcing the output

voltage to ramp up towards its regulation point. If OUT1

is prebiased above 1.25V, all three buck converters do

not start up until the prebias has been removed. Once the

prebias has been removed, OUT1 self-discharges to GND

and then goes into soft-start.

Thermal Warning and Overtemperature

Protection

The device features an open-drain, thermal-warning

indicator (ERR). ERR asserts low when the junction

temperature exceeds +150°C (typ). The hysteresis on

the thermal warning is 15°C (typ). For a logic signal,

connect a pullup resistor from ERR to a supply less than

or equal to 5V. When the junction temperature exceeds

+170°C (typ), an internal thermal sensor shuts down the

buck converters, allowing the device to cool. The thermal

sensor turns the device on again after the junction

temperature cools by 15°C (typ).

Buck 1 (OUT1)

Buck controller 1 uses a PWM current-mode control

scheme. An internal transconductance amplifier estab-

lishes an integrated error voltage. The heart of the PWM

controller is an open-loop comparator that compares the

integrated voltage-feedback signal against the amplified

current-sense signal plus the slope-compensation ramp,

which are summed into the main PWM comparator to

preserve inner-loop stability and eliminate inductor stair-

casing. At each rising edge of the internal clock, the high-

side MOSFET turns on until the PWM comparator trips or

the maximum duty cycle is reached, or the peak current

limit is reached. During this on-time, current ramps up

through the inductor, storing energy in a magnetic field

and sourcing current to the output. The current-mode

feedback system regulates the peak inductor current as a

function of the output-voltage error signal. The circuit acts

as a switch-mode transconductance amplifier and pushes

the output LC filter pole normally found in a voltage-mode

PWM to a higher frequency.

During the second half of the cycle, the high-side

MOSFET turns off and the low-side MOSFET turns on.

The inductor releases the stored energy as the current

ramps down, providing current to the output. The out-

put capacitor stores charge when the inductor current

exceeds the required load current and discharges when

the inductor current is lower, smoothing the voltage

across the load. Under soft-overload conditions, when the

peak inductor current exceeds the selected current limit

(see the Current-Limit/Short-Circuit Protection section),

the high-side MOSFET is turned off immediately and the

low-side MOSFET is turned on and remains on to let the

inductor current ramp down until the next clock cycle.

PWM/Skip Modes

The device features a synchronization input that puts all

the buck regulators either in skip mode or forced-PWM

mode of operation (see the Synchronization (SYNC)

section). In the PWM mode of operation, the regulator

switches at a constant frequency with variable on-time.

In the skip mode of operation, the regulator’s switching

frequency is load dependent until the output load reaches

a certain threshold. At higher load current, the switch-

ing frequency does not change and the operating mode

is similar to the PWM mode. Skip mode helps improve

efficiency in light-load applications by allowing the regula-

tor to turn on the high-side switch only when the output

voltage falls below a set threshold. As such, the regulator

does not switch MOSFETs on and off as often as is the

case in the PWM mode. Consequently, the gate charge

and switching losses are much lower in skip mode.

Minimum On-Time and Duty Cycle

The high-side gate driver for Buck 1 has a minimum on-

time of 75ns (max). This helps ensure no skipped pulses

when operating the device in PWM mode at 2.1MHz with

supply voltage up to 18V and output voltage down to

3.3V. Pulse skipping can occur if the on-time falls below

the minimum allowed (see the Electrical Characteristics).

Current-Limit/Short-Circuit Protection

OUT1 offers a current-limit feature that protects Buck 1

against short-circuit and overload conditions on the buck

controller. Buck 1 offers a current-limit sense input (CS1).

Place a sense resistor in the path of the channel 1 current

flow. Connect CS1 to the high side of the sense resistor

and OUT1 to the low side of the sense resistor. Current-

limit protection activates once the voltage across the

sense resistor increases above the 120mV (typ) current-

limit threshold. In the event of a short-circuit or overload

condition, the high-side MOSFET remains on until the

inductor current reaches the current-limit threshold. The

converter then turns on the low-side MOSFET and the

inductor current ramps down. The converter allows the

high-side MOSFET to turn on only when the voltage

across the current-sense resistor ramps down to below

120mV (typ). This cycle repeats until the short or overload

condition is removed.

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Current-Sense Measurement

For the best current-sense accuracy and overcurrent pro-

tection, use a 1% tolerance current-sense resistor between

the inductor and output, as shown in Figure 2. This con-

figuration constantly monitors the inductor current, allow-

ing accurate current-limit protection. Use low-inductance

current-sense resistors for accurate measurement.

High-Side Gate-Drive Supply (BST1)

The high-side MOSFET is turned on by closing an inter-

nal switch between BST1 and DH1 and transferring the

bootstrap capacitor’s (at BST1) charge to the gate of the

high-side MOSFET. This charge refreshes when the high-

side MOSFET turns off and the LX1 voltage drops down

to ground potential, taking the negative terminal of the

capacitor to the same potential. At this time, the bootstrap

diode recharges the positive terminal of the bootstrap

capacitor. The selected n-channel high-side MOSFET

determines the appropriate boost capacitance values

(CBST1 in the Typical Operating Circuit) according to the

following equation:

BST 1

=∆

where QG is the total gate charge of the high-side

MOSFET and ΔVBST1 is the voltage variation allowed

on the high-side MOSFET driver after turn-on. Choose

ΔVBST1 such that the available gate-drive voltage is not

significantlydegraded(e.g.,ΔVBST1 = 100mV to 300mV)

when determining CBST1. Use a Schottky diode when

efficiency is most important, as this maximizes the gate-

drive voltage. If the quiescent current at high temperature

is important, it may be necessary to use a low-leakage

switching diode.

The boost capacitor should be a low-ESR ceramic

capacitor. A minimum value of 100nF works in most

cases. A minimum value of 470nF is recommended when

using a Schottky diode.

Dropout

When OUT1 input voltage is lower than the desired output

voltage, the converter is in dropout mode. Buck 1 continu-

ously draws current from the bootstrap capacitor when the

high-side switch is on. Therefore, the bootstrap capacitor

needs to be refreshed periodically. When in dropout, the

Buck 1 high-side gate drive shuts off every 8µs, at which

point the low-side gate drive turns on for 120ns.

Buck 2 and Buck 3 (OUT2 and OUT3)

Buck converters 2 and 3 are high-efficiency, low-

voltage converters with integrated FETs. They use a

PWM current-mode control scheme that is operated at

2.1MHz to optimize component size and efficiency, while

eliminating AM band interference. The buck converters

can be configured to deliver 1.5A or 3.0A per channel.

They operate directly from OUT1 and have either fixed

or resistor-programmable (see the Selector Guide) output

voltages that range from 0.8V to 3.95V. Buck 2 and Buck 3

feature low on-resistance internal FETs that contribute to

high efficiency and smaller system cost and board space.

Integration of the p-channel high-side FET enables both

channels to operate with 100% duty cycle when the input

voltage falls to near the output voltage. They feature a

programmable active timeout period (see the Selector

Guide) that adds a fixed delay before the corresponding

RESET_ can go high.

FPWM/Skip Modes

The MAX16993 features an input (SYNC) that puts the

converter either in skip mode or forced PWM (FPWM)

mode of operation. See the Internal Oscillator section.

In FPWM mode, the converter switches at a constant

frequency with variable on-time. In skip mode, the con-

verter’s switching frequency is load-dependent until the

output load reaches a certain threshold. At higher load

current, the switching frequency does not change and the

operating mode is similar to the FPWM mode.

Figure 2. Current-Sense Configuration

DH1

OUTPUT SERIES RESISITOR SENSING

LX1

GND

CS1

OUT1

DL1 N

L1 RCS

VSUP

CIN

COUT

MAX16993

MAX16993 Step-Down Controller with

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Skip mode helps improve efficiency in light-load appli-

cations by allowing the converters to turn on the high-

side switch only when the output voltage falls below a

set threshold. As such, the converter does not switch

MOSFETs on and off as often as is the case in the FPWM

mode. Consequently, the gate charge and switching

losses are much lower in skip mode.

Current-Limit/Short-Circuit Protection

Buck converters 2 and 3 feature current limit that protects

the device against short-circuit and overload conditions at

their outputs. The current limit value is dependent on the

version selected, 1.5A or 3.0A maximum DC current. See

the Selector Guide for the current limit value of the chosen

option and the Electrical Characteristics table for the cor-

responding current limit. In the event of a short-circuit or

overload condition at an output, the high-side MOSFET

remains on until the inductor current reaches the high-

side MOSFET’s current-limit threshold. The converter

then turns on the low-side MOSFET and the inductor cur-

rent ramps down.

The converter allows the low-side MOSFET to turn off

only when the inductor current ramps down to the low-

side MOSFET’s current threshold. This cycle repeats until

the short or overload condition is removed.

Applications Information

OUT1 Adjustable Output-Voltage Option

The device’s adjustable output-voltage version (see

the Selector Guide for details) allows the customer to

set OUT1 voltage between 3.0V and 5.5V. Connect a

resistive divider from OUT1 to FB1 to GND to set the

output voltage (Figure 3). Select R2 (FB1 to GND resistor)

lessthanorequalto100kΩ.CalculateR1(VOUT1 to FB1

resistor) with the following equation:

OUT 1

FB 1

RR 1





= −











where VFB1 = 1.0V (see the Electrical Characteristics).

The external feedback resistive divider must be frequency

compensated for proper operation. Place a capacitor

across R1 in the resistive divider network. Use the follow-

ing equation to determine the value of the capacitor:

if R2/R1 > 1, C1 = C(R2/R1)

else, C1 = C, where C = 10pF.

For fixed output options, connect FB1 to BIAS for the

factory-programmed, fixed output voltage. Connect FB1

to GND for a fixed 3.3V output voltage.

OUT1 Current-Sense Resistor Selection

Choose the current-sense resistor based on the maximum

inductor current ripple (KINDMAX) and minimum current-limit

threshold across current-sense resistor (VLIM1MIN = 0.1V).

The formula for calculating the current-sense resistor is:

LIM1MIN

MAX

INDMAX

OUTMAX

Rcs K

I (1 )

×+

where IOUTMAX is the maximum load current for Buck 1

and KINDMAX is the maximum inductor current ripple.

The maximum inductor current ripple is a function of the

inductor chosen, as well as the operating conditions, and

is typically chosen between 0.3 and 0.4:

[ ] [ ]

SUP OUT

INDMAX

OUTMAX SW 1

(V V ) D

KI f MHz L µH

−×

=××

where D is the duty cycle. Below is a numerical exam-

ple to calculate the current-sense resistor in Figure 2.

The maximum inductor current ripple is chosen at the

maximum supply voltage (36V) to be 0.4:

MAX

INDMAX

OUTMAX

0.1

Rcs K

0.1 0.0166

0.4

512



×+





= = Ω



×+





OUT1 Inductor Selection

Three key inductor parameters must be specified for

operation with the device: inductance value (L), inductor

saturation current (ISAT), and DC resistance (RDCR). Use

Figure 3. Adjustable OUT1 Voltage Configuration

VOUT1

OUT1

MAX16993

FB1

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Table 1. Inductor Values vs. (VSUPMAX, VOUT1)

the following formulas to determine the minimum inductor

value:

( )

OUT 1

SUPMAX OUT 1 SUPMAX

MIN 1

SW 1 OUTMAX INDMAX

L [ H ] 1.3

fI K





−×









= ×











××





where fSW1 is the operating frequency and 1.3 is a

coefficient that accounts for inductance initial precision.

or:

=××

××

OUT1

MIN 2 CS

V_CS SW1

L [ H ] 1.3 R

0.8 V

2.1 10

where AV_CS is current-sense amplifier gain (8V/V, typ).

For proper operation, the chosen inductor value must be

greater than or equal to LMIN1 and LMIN2. The maximum

inductor value recommended is twice the chosen value

from the above formulas.

Table 1 lists some of the inductor values for 5A output

current and several switching frequencies and output

voltages.

Buck 1 Input Capacitor

The device is designed to operate with a single 0.1µF

capacitor on the VSUP input and a single 0.1µF capacitor on

the PV1 input. Place these capacitors as close as possible to

their corresponding inputs to ensure the best EMI and jitter

performance.

OUT1 Output Capacitor

The primary purpose of the OUT1 output capacitor is

to reduce the change in VOUT1 during load transient

conditions. The minimum capacitor depends on the output

voltage, maximum current, and load regulation accuracy.

Use the following formula to determine the minimum out-

put capacitor for Buck 1:

OUT1(MAX)

OUT OUT1

CO OUT1

OUT1

2f V

≥∆

π× × ×

where fCO is the crossover frequency set by RC and CC,

andΔVOUT1 is the allowable change in voltage during a

load transient condition.

For proper functionality, ceramic capacitors must be

used. Make sure that the self-resonance of the ceramic

capacitors is above 1MHz to avoid instability.

Buck 1 MOSFET Selection

Buck 1 drives two external logic-level n-channel MOSFETs

as the circuit switch elements. The key selection param-

eters to choose these MOSFETs are:

● On-resistance (RDS(ON))

● Maximum drain-to-source voltage (VDS(MAX))

● Minimum threshold voltage (VTH(MIN))

● Total gate charge (QG)

● Reverse transfer capacitance (CRSS)

● Power dissipation

Both n-channel MOSFETs must be logic-level types with

guaranteed on-resistance specifications at VGS = 4.5V

when VOUT1 is set to 5V or VGS = 3V when VOUT1 is set

to 3.3V. The conduction losses at minimum input voltage

should not exceed MOSFET package thermal limits or

violate the overall thermal budget. Also, ensure that the

conduction losses plus switching losses at the maximum

input voltage do not exceed package ratings or violate the

overall thermal budget. In particular, check that the dV/dt

caused by DH1 turning on does not pull up the DL1 gate

through its drain-to-gate capacitance. This is the most

frequent cause of cross-conduction problems.

Gate-charge losses are dissipated by the driver and do

not heat the MOSFET. Therefore, the power dissipation

in the device due to drive losses must be checked. Both

MOSFETs must be selected so that their total gate charge

VSUPMAX to VOUT1 (V) VSUPMAX = 36V, VOUT1 = 5V VSUPMAX = 36V, VOUT1 = 3.3V

fSW1 (MHz) 2.1 1.05 0.525 0.420 0.350 2.1 1.05 0.525 0.420 0.350

INDUCTOR (µH), ILOAD = 5A 1.5 3.3 5.6 6.8 8.2 1.0 2.2 4.7 4.7 6.8

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

www.maximintegrated.com Maxim Integrated

│

is low enough; therefore, PV1/ VOUT1 can power both

drivers without overheating the device:

PDRIVE = VOUT1 x (QGTOTH + QGTOTL) x fSW1

where QGTOTL is the low-side MOSFET total gate charge

and QGTOTH is the high-side MOSFET total gate charge.

Select MOSFETs with a QG_ total of less than 10nC. The

selected MOSFET must have an input capacitance (CISS)

less than 900pF (typ) to prevent possible damage to the

device.

The n-channel MOSFETs must deliver the average

current to the load and the peak current during switching.

Dual MOSFETs in a single package can be an economical

solution. To reduce switching noise for smaller MOSFETs,

use a series resistor in the DH1 path and additional gate

capacitance. Contact the factory for guidance using gate

resistors.

Compensation Network

The device uses a current-mode-control scheme that

regulates the output voltage by forcing the required

current through the external inductor, so the controller

uses the voltage drop across the DC resistance of the

inductor or the alternate series current-sense resistor

to measure the inductor current. Current-mode control

eliminates the double pole in the feedback loop caused

by the inductor and output capacitor, resulting in a smaller

phase shift and requiring less elaborate error-amplifier

compensation than voltage-mode control. A single series

resistor (RC) and capacitor (CC) is all that is required

to have a stable, high-bandwidth loop in applications

where ceramic capacitors are used for output filtering

(see Figure 4). For other types of capacitors, due to the

higher capacitance and ESR, the frequency of the zero

created by the capacitance and ESR is lower than the

desired closed-loop crossover frequency. To stabilize a

nonceramic output capacitor loop, add another compen-

sation capacitor (CF) from COMP1 to GND to cancel this

ESR zero.

The basic regulator loop is modeled as a power modu-

lator, output feedback divider, and an error amplifier

(see Figure 4). The power modulator has a DC gain set by

gmc x RLOAD, with a pole and zero pair set by RLOAD, the

output capacitor (COUT), and its ESR. The loop response

is set by the following equation:

GAINMOD(dc) = gmc x RLOAD

where RLOAD = VOUT/ILOUT(MAX) in Ω and gmc =

1/(AV_CS x RDC) in S. AV_CS is the voltage gain of the

current-sense amplifier and is typically 8V/V. RDC is the

DC resistance of the inductor or the current-sense resistor

inΩ.

In a current-mode step-down converter, the output capaci-

tor and the load resistance introduce a pole at the follow-

ing frequency:

pMOD

OUT LOAD

f2C R

=π× ×

The unity-gain frequency of the power stage is set by

COUT and gmc:

UGAINpMOD

OUT

f2C

=π×

The output capacitor and its ESR also introduce a zero at:

zMOD

OUT

f2 ESR C

=π× ×

When COUT is composed of “n” identical capacitors in

parallel, the resulting COUT = n x COUT(EACH), and ESR

= ESR(EACH)/n. Note that the capacitor zero for a parallel

combination of like-value capacitors is the same as for an

individual capacitor.

The feedback voltage-divider has a gain of GAINFB =

VFB/VOUT, where VFB is 1V (typ).

The transconductance error amplifier has a DC gain

of GAINEA(DC) = gm,EA x ROUT,EA, where gm,EA is

the error amplifier transconductance, which is 660µS

(typ), and ROUT,EA is the output resistance of the error

amplifier,whichis30MΩ(typ).

A dominant pole (fdpEA) is set by the compensation capac-

itor (CC) and the amplifier output resistance (ROUT,EA). A

zero (fZEA) is set by the compensation resistor (RC) and

the compensation capacitor (CC). There is an optional

pole (fPEA) set by CF and RC to cancel the output

Figure 4. Compensation Network

RESR

30MΩ

COMP_

COUT R2

CS_

OUT_

FB_

VREF

CURRENT-MODE

POWER MODULATION

gmc = 1/(AVCS x RDC)

ERROR

AMP

gMEA = 660µS

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

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│

capacitor ESR zero if it occurs near the crossover

frequency (fC, where the loop gain equals 1 (0dB)).

Thus:

dpEA

C OUT, EA C

zEA

pEA

f2 C (R R )

f2C R

=π× × +

=π× ×

The loop-gain crossover frequency (fC) should be set

below 1/5 of the switching frequency and much higher

than the power-modulator pole (fpMOD). Select a value

for fCO in the range:

<< ≤ SW

pMOD CO

At the crossover frequency, the total loop gain must be

equal to 1.

Thus:

MOD ( f ) EA ( R )

OUT

EA (f ) m,EA C

pMOD

MOD ( f ) MOD ( dc )

GAIN GAIN 1

GAIN g f

GAIN GAIN f

×× =

= ×

Therefore:

MOD (f ) m,EA C

OUT

GAIN g R 1

× × ×=

Solving for RC:

OUT

m,EA FB MOD (f )

Rg V GAIN

=××

Set the error-amplifier compensation zero formed by

RC and CC at the fpMOD. Calculate the value of CC as

follows:

2f R

pMOD

π× ×

If fzMOD is less than 5 x fC, add a second capacitor CF

from COMP1 to GND. The value of CF is:

2f R

zMOD

π× ×

As the load current decreases, the modulator pole also

decreases; however, the modulator gain increases accord-

ingly and the crossover frequency remains the same.

Below is a numerical example to calculate the compensa-

tion network component values of Figure 4:

AV_CS = 8V/V

RDCR=22mΩ

gmc = 1/(AV_CS x RDC) = 1/(8 x 0.022) = 5.68

VOUT = 5V

IOUT(MAX) = 5A

RLOAD = VOUT/IOUT(MAX)=5V/6A=0.833Ω

COUT = 4 x 47µF = 188µF

ESR=9mΩ/4=2.25mΩ

fSW = 0.420MHz

GAINMOD(dc) = 5.68 x 0.833 = 4.73

pMOD

pMOD C

zMOD

f 1kHz

2 188 F 0.833

1kHz f 80.6 kHz , Select f 20 kHz

f 376 kHz

2 2.25 m 188 F

= ≈

π× µ ×

<< ≤

<< ≤ =

= ≈

π× Ω× µ

Since fzMOD > fC:

RC≈33kΩ

CC≈4.7nF

CF≈12pF

OUT2/OUT3 Adjustable Output-Voltage Option

The device’s adjustable output-voltage version (see the

Selector Guide for details) allows the customer to set

the outputs to any voltage between 0.8V and 3.95V.

Connect a resistive divider from the buck converter output

(VOUT_(BUCK)) to OUT_ to GND to set the output voltage

(Figure 5). Select R4 (OUT_ to GND resistor) less than

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

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│

orequalto100kΩ.CalculateR3(VOUT_(BUCK) to OUT_

resistor) with the following equation:

OUT_( BUCK )

OUT_

R3 R4 1









= −









where VOUT_ = 800mV (see the Electrical Characteristics).

The external feedback resistive divider must be frequency

compensated for proper operation. Place a capacitor in

parallel to R3 in the resistive divider network. Use the fol-

lowing equation to determine the value of the capacitor:

if R4/R3 > 1, C2 = C(R4/R3)

else, C2 = C, where C = 10pF.

For fixed output-voltage options, connect OUT_ to VOUT_

for the factory-programmed, fixed-output voltage between

0.8V and 3.95V.

OUT2/OUT3 Inductor Selection

Three key inductor parameters must be specified for

operation with the MAX16993: inductance value (L),

inductor saturation current (ISAT), and DC resistance

(RDCR). Use the following formulas to determine the mini-

mum inductor value.

( )

IN OUT_ OUT

MI N1 IN SW MAX

VV V

L V f I % 3 5

−×

=×× ×

The next equation ensures that the inductor current down

slope is less than the internal slope compensation. For

this to be the case the following equation needs to be

satisfied:

-m≥m2/2

Solving for L and adding a 1.5 multiplier to account for

tolerances in the system:

MIN2 OUT

L V 1.5

=××

To satisfy both LMIN1 and LMIN2, LMIN must be set to the

larger of the two.

LMIN = max (LMIN1, LMIN2)

The maximum inductor value recommended is 1.6 times

the chosen value from the above formula.

LMAX = 1.6 x LMIN

Select a nominal inductor value based on the following

formula:

LMIN<LNOM <LMAX

OUT2/OUT3 Input Capacitor

Place a single 4.7µF ceramic bypass capacitor on the

PV2 and PV3 inputs. Phase interleaving of the two low-

voltage buck converters contributes to a lower required

input capacitance by cancelling input ripple currents. Place

the bypass capacitors as close as possible to their cor-

responding PV_ input to ensure the best EMI and jitter

performance.

OUT2/OUT3 Output Capacitor

The minimum capacitor required depends on output

voltage, maximum device current capability, and the

error-amplifier voltage gain. Use the following formula to

determine the required output capacitor value:

=π× × ×

REF EAMP

OUT(MIN) CO OUT CS

C2f V R

The low gain setting trades off increased load-regulation

error for a smaller output capacitor requirement. This

allows optimization of system cost when system require-

ments allow for the increase in load regulation.

RCS 0.378Ωfor1.5Achannel

0.167Ωfor3.0Achannel

IMAX

3.0A or 1.5A depending on part number. Use the

maximum output capability of the output channel

for the part number being used.

fSW Operating frequency. This value is 2.1MHz unless

externally synchronized to a different frequency.

m2 The inductor current downslope. [VOUT/L x RCS]

-m Slope Compensation [0.47 x V/µs]

VREF Reference voltage, VREF = 0.8V.

RCS

Internal current-sense resistance. See the Selector

Guideforthevalueforeachspecicpartnumber.

RCS=0.378Ω;for1.5Aoutputchannels

RCS=0.167Ω;for3.0Aoutputchannels

fCO Target crossover frequency, which is 210kHz.

GEAMP

Error-ampliervoltagegain.SeetheSelector

Guide for the setting for each channel.

44.7V/V = Normal gain setting

31.7V/V = Low gain setting

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

www.maximintegrated.com Maxim Integrated

│

Figure 5. Adjustable OUT2/OUT3 Voltage Configuration

For proper functionality, ceramic capacitors must be

used. Make sure that the self-resonance of the ceramic

capacitors is above 1MHz to avoid instability.

Thermal Considerations

How much power the package can dissipate strongly

depends on the mounting method of the IC to the PCB

and the copper area for cooling. Using the JEDEC test

standard, the maximum power dissipation allowed is

2160mW in the side-wettable QFND package. More

power dissipation can be handled by the package if great

attention is given during PCB layout. For example, using

the top and bottom copper as a heatsink and connect-

ing the thermal vias to one of the middle layers (GND)

transfers the heat from the package into the board more

efficiently, resulting in lower junction temperature at

high power dissipation in some MAX16993 applications.

Furthermore, the solder mask around the IC area on both

top and bottom layers can be removed to radiate the heat

directly into the air. The maximum allowable power dis-

sipation in the IC is as follows:

J ( MAX ) A

MAX

JC CA

(T T )

−

=θ +θ

where TJ(MAX) is the maximum junction temperature

(+150°C), TAistheambientairtemperature,θJC (2.8°C/W

for the side-wettable QFND) is the thermal resistance

from the junction to the case, and θCA is the thermal

resistance from the case to the surrounding air through

thePCB,coppertraces,andthepackagematerials.θCA

is directly related to system-level variables and can be

modified to increase the maximum power dissipation. The

QFND package has an exposed thermal pad on its under-

side. This pad provides a low thermal-resistance path for

heat transfer into the PCB. This low thermally resistive

path carries a majority of the heat away from the IC. The

PCB is effectively a heatsink for the IC. The exposed pad

should be connected to a large ground plane for proper

thermal and electrical performance. The minimum size

of the ground plane is dependent upon many system

variables. To create an efficient path, the exposed pad

should be soldered to a thermal landing, which is con-

nected to the ground plane by thermal vias. The thermal

landing should be at least as large as the exposed pad

and can be made larger depending on the amount of free

space from the exposed pad to the other pin landings. A

sample layout is available on the MAX16993 Evaluation

Kit to speed designs.

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching

losses and clean, stable operation. Use a multilayer board

whenever possible for better noise immunity and power

dissipation. Follow these guidelines for good PCB layout:

1) Use a large contiguous copper plane under the device

package. Ensure that all heat-dissipating components

have adequate cooling.

2) Isolate the power components and high-current path

from the sensitive analog circuitry. This is essential to

prevent any noise coupling into the analog signals.

3) Keep the high-current paths short, especially at the

ground terminals. This practice is essential for stable,

jitter-free operation. The high-current path comprising

of input capacitor, high-side FET, inductor, and the

output capacitor should be as short as possible.

4) Keep the power traces and load connections short. This

practice is essential for high efficiency. Use thick copper

PCBs (2oz vs. 1oz) to enhance full-load efficiency.

5) The analog signal lines should be routed away from

the high-frequency planes. This ensures integrity of

sensitive signals feeding back into the device.

6) Use a single ground plane to reduce the chance of

ground-potential differences. With a single ground

plane, enough isolation between analog return signals

and high-power signals must be maintained.

VOUT_(BUCK)

MAX16993

OUT_

LX_

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

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│

Typical Application Circuit

BIAS PV1

BIAS

VBATP

2.2µF

BST1

0.1µF

VSUP

DH1

1µF

LX1

MAX16993

GND

CS1

OUT1

0.1µF220µF

BIAS

FB1

BIAS

EN2

BIAS

SYNC

CSEL1

SSEN GND

VOUT1

VBATP

VOUT1

(5V, 5A)

47µF

20pF

47µF

PV3

LX3

10µF

0.6µH

VOUT1

PGND3

OUT3

1µF

COMP1

RESET1

47pF

4.7nF

0.1µF

FB1

0.1µF0.1µF

47µF47µF47µF47µF

DL1

2.2µH

22mΩ

40kΩ

10Ω

EN1

100kΩ

5.1kΩ

RESET1

ERR

RESET2RESET2

RESET3

EN3

RESET3

ERR

VOUT3

(1.2V, 3A)

10kΩ

20kΩ

47µF

3.3pF

47µF

PV2

LX2

10µF

1µH

VOUT1

PGND2

OUT2

VOUT2

(3.3V, 3A)

75kΩ

24kΩ

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

www.maximintegrated.com Maxim Integrated

│

Selector Guide

Ordering Information

Note: Insert the desired suffix letter (from the Selector Guide)

into the blank to indicate buck switching frequency, active time-

out period, fixed or adjustable output voltages, and maximum

output current.

/ V denotes an automotive qualified part.

+Denotes a lead(Pb)-free/RoHS-compliant package.

*Future product—contact factory for availability.

**EP = Exposed pad/side-wettable flanked package.

†EP = Exposed pad.

Contact factory for options that are not included. Factory-

selectable features include:

• fSW1 divide ratio with respect to master clock

• DC-DC output voltage

• Number of cycles in active timeout period

• Independent current limit for each channel up to 3A

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

OPTION

BUCK 1 BUCK 2 BUCK 3

SYNC

FIXED

OUTPUT

VOLTAGE

(V)

fSW1

DIVIDE

RATIO

FROM fSW

ACTIVE

TIMEOUT

PERIOD

(ms)

FIXED

OUTPUT

VOLTAGE

(V)

MAX

OUTPUT

CURRENT

(A)

ACTIVE

TIMEOUT

PERIOD

(ms)

FIXED

OUTPUT

VOLTAGE

(V)

MAX

OUTPUT

CURRENT

(A)

ACTIVE

TIMEOUT

PERIOD

(SAME AS

BUCK 2)

(ms)

A 3.3/5.0 ÷5 3.9 ADJ 3.0 3.9 ADJ 3.0 3.9 Input

B 3.3/5.0 ÷5 3.9 3.15 1.5 3.9 1.8 (L) 1.5 3.9 Input

C 3.3/5.0 ÷5 1.9 ADJ 1.5 1.9 ADJ 1.5 1.9 Input

D 3.3/5.0 ÷5 3.9 1.05 3.0 3.9 3.3 1.5 3.9 Input

E 3.3/5.0 ÷5 3.9 3.30 1.5 3.9 1.5 1.5 3.9 Input

F 3.3/5.0 ÷5 3.9 3.3 1.5 3.9 1.2 1.5 3.9 Input

G 3.3/5.0 ÷5 3.9 3.3 1.5 3.9 1.8 1.5 3.9 Input

H 3.3/5.2 ÷5 3.9 3.3 3.0 3.9 1.8 1.5 3.9 Input

I ADJ ÷5 1.9 ADJ 1.5 1.9 ADJ 1.5 1.9 Input

J* 3.3/5.0 ÷4 3.9 ADJ 3.0 3.9 ADJ 3.0 3.9 Input

K 3.3/5.0 ÷5 3.9 1.05 3.0 3.9 3.3 3.0 3.9 Input

L 3.3/4.9 ÷5 3.9 3.3 1.5 3.9 1.25 1.5 3.9 Input

PART TEMP RANGE PIN-PACKAGE

MAX16993AGJ_/VY+ -40°C to +125°C 32 QFND-EP**

MAX16993ATJ_+ -40°C to +125°C 32 TQFN-EP†

MAX16993ATJ_/V+ -40°C to +125°C 32 TQFN-EP†

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

32 QFND-EP G3255Y+1 21-0563 90-0361

32 TQFN-EP T3255+4 21-0140 90-0012

(L) = Low gain setting.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

MAX16993 Step-Down Controller with

Dual 2.1MHz Step-Down DC-DC Converters

│

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 5/13 Initial release —

1 8/13 Corrected package type (from TQFN to QFND) 1, 2, 9, 22, 24

2 10/13

Added TQFN package, and updated SYNC pin function, limit/short-circuit information,

Package Thermal Characteristics, Typical Application Circuit, Selector Guide, Ordering

Information, and Package Information sections

1, 2, 9, 10,

16, 23, 24

3 12/13 Updated bypass capacitor on PV pin in Pin Description and added /V TQFN package

to Ordering Information 9, 24

4 2/14 Removed lossless DCR sensing from data sheet, updated Typical Operating Circuit,

and updated GCS values in OUT2/OUT3 Output Capacitor section 11, 15, 21

5 3/14 Corrected the GCS equation and -m equation in the OUT2/OUT3 Inductor Selection

tables; updated the TQFN package code in the Package Information table 20, 24

6 6/14

Removed references to SYNC output functionality: updated General Description,

Electrical Characteristics, Pin Description, General Description, Synchronization

(SYNC), OUT2/OUT3 Inductor Selection sections, and Typical Application Circuit and

Ordering Information

1, 5, 10, 12, 13,

20, 23, 24

7 7/14 Removed future product references from option F, G, H, and I variants in Selector

Guide 24

8 7/14 Corrected equation for slope compensation 20

9 10/14 Removed future product reference and updated Option D in Selector Guide, corrected

land pattern number for TQFN in Package Information 24

10 1/15 Added option J variant in Selector Guide 24

11 3/15

Updated Benets and Features, added new Note 1 to Absolute Maximum Ratings

and renumbered remaining notes in Package Thermal Characteristics and Electrical

Characteristics, added missing units in Electrical Characteristics,clariedequations

in OUT1 Inductor Selection, Compensation Network, and OUT2/OUT3 Adjustable

Output-Voltage Option sections, updated OUT2/OUT3 Inductor Selection and OUT2/

OUT3 Output Capacitor section, deleted Table 2 and Table 3, and added future

product designation to option J variant in Selector Guide

1–5, 16, 19–21,

12 9/15 Miscellaneous updates 4, 14, 18, 20,

13 7/16 Updated Absolute Maximum Ratings and Linear Regulator (BIAS) sections; removed

future product reference from Option K and added Option L in Selector Guide 2, 12, 23

14 12/16 Removed future product reference from Option L in Selector Guideandchangedxed

output voltage from 3.3/5.0 to 3.3/4.9 23

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Maxim Integrated:

MAX16993AGJA/VY+ MAX16993AGJC/VY+ MAX16993AGJI/VY+ MAX16993ATJB/V+T MAX16993ATJG/V+T

MAX16993ATJG+ MAX16993ATJB+ MAX16993ATJC+T MAX16993ATJE/V+T MAX16993ATJA/V+T

MAX16993AGJF/VY+ MAX16993ATJH/V+ MAX16993ATJF/V+T MAX16993AGJG/VY+ MAX16993ATJF+T

MAX16993ATJE+T MAX16993ATJE+ MAX16993ATJB/V+ MAX16993ATJC+ MAX16993AGJB/VY+T

MAX16993ATJF+ MAX16993ATJG/V+ MAX16993ATJF/V+ MAX16993ATJA/V+ MAX16993AGJH/VY+T

MAX16993ATJI+ MAX16993ATJE/V+ MAX16993ATJH+ MAX16993ATJA+T MAX16993ATJI/V+

MAX16993AGJA/VY+T MAX16993ATJI+T MAX16993ATJC/V+ MAX16993ATJA+ MAX16993AGJI/VY+T

MAX16993AGJE/VY+ MAX16993AGJH/VY+ MAX16993ATJI/V+T MAX16993AGJE/VY+T MAX16993AGJB/VY+

MAX16993ATJD+T MAX16993AGJG/VY+T MAX16993ATJH/V+T MAX16993ATJH+T MAX16993ATJD/V+

MAX16993ATJB+T MAX16993AGJC/VY+T MAX16993AGJF/VY+T MAX16993ATJG+T MAX16993ATJC/V+T

MAX16993AGJL/VY+T MAX16993AGJL/VY+ MAX16993AGJD/VY+ MAX16993ATJJ/V+ MAX16993AGJK/VY+