REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added device types 03, 04, 05, and 06. Added electrical test limits for device types 03, 04, 05, and 06 to table I. Added vendor CAGE code 34335. Editorial changes throughout. 90-05-09 William K. Heckman B Added device types 07, 08, 09, and 10. Added electrical parameters testing to table I for device types 07, 08, 09, and 10. Added a new package for device type 07. Editorial changes throughout. 92-03-25 Monica L. Poelking C Added vendor CAGE code 0C7V7. Update boilerplate to MIL-PRF-38535 requirements. - LTG 02-12-18 Thomas M. Hess REV SHEET REV C C C C C C C C C C C C C C SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Tim H. Noh STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil CHECKED BY Tim H.Noh APPROVED BY William K. Heckman MICROCIRCUIT, DIGITAL, CMOS, SERIAL COMMUNICATION CONTROLLER, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-02-06 AMSC N/A REVISION LEVEL C SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited 1 OF 5962-88689 28 5962-E130-03 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88689 01 Q X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Frequency 01 02 03 Z85C3006 Z85C3008 AM85C30-10 6.0 MHz 8.0 MHz 10.0 MHz 04 AM85C30-12 12.0 MHz 05 AM85C30-16 16.0 MHz 06 AM85C30-08 8.0 MHz 07 08 Z85C3010 Z8523010 10.0 MHz 10.0 MHz 09 Z8523016 16.0 MHz 10 Z8523008 8.0 MHz Circuit function Serial communication controller Serial communication controller 2/ Serial communication controller with SDLC enhancements 1/ Serial communication controller with SDLC enhancements Serial communication controller with SDLC enhancements 1/ Serial communication controller with SDLC enhancements 1/ Serial communication controller 3/ Serial communication controller with SDLC enhancements 1/ Serial communication controller with SDLC enhancements 1/ Serial communication controller with SDLC enhancements 1/ 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Q X Y Descriptive designator Terminals GDIP1-T40 or CDIP2-T40 GQCC1-J44 CQCC1-N44 Package style 40 44 44 Dual-in-line package Square "J" lead chip carrier Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1/ Device types 03, 05, 06, 08, 09, and 10 are not functionally identical. 2/ Device type 02 is not functionally identical with device types 06 or 10. 3/ Device type 07 is not functionally identical with device types 03 or 08. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 2 1.3 Absolute maximum ratings. VCC supply voltage range (referenced to ground).................... Voltage on any pin (referenced to ground).............................. Storage temperature range (TSTG)........................................... Maximum power dissipation (PD)............................................. Lead temperature (soldering, 10 seconds) ............................. Maximum operating junction temperature (TJ) ........................ Thermal resistance, junction-to-case (JC) .............................. -0.3 V dc to +7.0 V dc -0.3 V dc to +7.0 V dc -65C to +150C 0.5 W +270C +180C See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage (VCC)................................................................ Minimum high level input voltage (VIH) .................................... Maximum low level input voltage (VIL) ..................................... Frequency of operation: Device type 01 ..................................................................... Device types 02, 06, 10 ....................................................... Device types 03, 07, 08 ....................................................... Device type 04 ..................................................................... Device types 05 and 09 ....................................................... Case operating temperature range (TC) .................................. Clock rise and fall times: Device type 09 ..................................................................... Device type 05 ..................................................................... Device types 01, 02, 03, 04, 06, 07, 08, 10 ......................... 4.5 V dc minimum to 5.5 V dc maximum 2.2 V dc 0.8 V dc 0.5 MHz to 6.0 MHz 0.5 MHz to 8.0 MHz 0.5 MHz to 10 MHz 0.5 MHz to 12.5 MHz 0.5 MHz to 16.4 MHz -55C to +125C 5 ns maximum 8 ns maximum 10 ns maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 3 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Timing waveforms and test circuits. The timing waveforms and test circuits shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 and QML-38535 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, appendix A. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified High input voltage VIH Low input voltage VIL Logic low output voltage VOL IOL = 2.0 mA, VCC = 4.5 V VOH1 VOH2 ICC VIH = 4.8 V VIL = 0.2 V VCC = 5.0 V Oscillator off Logic high output voltage Power supply current Group A subgroups Device type Max VCC+0.3 2/ 2.2 1, 2, 3 All -0.3 2/ 1, 2, 3 All IOH = -1.6 mA, VCC = 4.5 V 1, 2, 3 All 2.4 V IOH = -250 A, VCC = 4.5 V 1, 2, 3 All VCC0.8 V 1, 2, 3 01,02,06 30 1, 2, 3 03,07,08 18 1, 2, 3 04,05,09 22 1, 2, 3 10 VOUT = 0.4 V, VCC = 5.5 V 1, 2, 3 All ILOH VOUT = 2.4 V, VCC = 5.5 V 1, 2, 3 All Input low current IIL VIN = 0.4 V, VCC = 5.5 V 1, 2, 3 All Input high current IIH VIN = 2.4 V, VCC = 5.5 V 1, 2, 3 All Input capacitance CIN Output cpacitance COUT fc = 1.0 MHz See 4.3.1c Bidirectional capacitance CI/O See 4.3.1d VCC = 4.5 V, 5.5 V fMAX Min All ILOL Maximum frequency Unit 1, 2, 3 Output leakage current low Output leakage current high Functional test Limits See figure 3 VCC = 4.5 V 0.8 V 0.5 V mA 15 A -10 +10 -10 +10 4 All 10 4 All 15 4 All 20 7, 8 All 9, 10, 11 V 05, 09 16.0 04 12.0 03,07,08 10.0 02,06,10 8.0 01 6.0 pF MHz See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 5 TABLE I. Electrical performance characteristics - Continued. Test Symbol PCLK low width PCLK high width PCLK fall time 2/ 3/ PCLK rise time 2/ 3/ twPCL Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified See figure 3, read and write, interrupt, reset, and cycle timings. CL = 50 pF 10% VCC = 4.5 V twPCH tfPC trPC Group A subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Ref no. 1 2 3 4 Device type Limits Min Max 01 70 1000 02,06,10 50 1000 03,07,08 40 1000 04 34 1000 05, 09 26 1000 01 70 1000 02,06,10 50 1000 03,07,08 40 1000 04 34 1000 05, 09 01,02,03, 04,06,07, 08, 10 26 1000 Address to WR setup time Address to WR hold time tcPC tsA(WR) thA(WR) 9, 10, 11 9, 10, 11 9, 10, 11 5 6 7 ns ns 10 05 8 09 01,02,03, 04,06,07, 08, 10 5 10 05 8 09 PCLK cycle time Unit ns ns 5 01 165 2000 02,06,10 125 2000 03,07,08 100 2000 04 80 2000 05, 09 61 2000 01 80 02,06,10 70 03,07,08 50 04 45 05, 09 35 All 0 ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits 9, 10, 11 8 01 80 02,06,10 70 03,07,08 50 Min Address to RD setup time Address to RD hold time INTACK to PCLK setup time 4/ INTACK to WR setup time 5/ INTACK to WR hold time INTACK to RD setup time 5/ INTACK to RD hold time 4/ INTACK to PCLK hold time CE low to WR setup time CE to WR hold time tsA(RD) See figure 3, read and write, interrupt, reset, and cycle timings. CL = 50 pF 10% VCC = 4.5 V 04 45 05, 09 35 Unit Max ns thA(RD) 9, 10, 11 9 All 0 ns tsIA(PC) 9, 10, 11 10 01,02,03, 06,07,08, 10 20 ns 04,05,09 15 01 160 02,06,10 145 tsIAi(WR) 9, 10, 11 11 07 130 03, 08 120 04 95 05, 09 70 ns thIA(WR) 9, 10, 11 12 All 0 ns tsIAi(RD) 9, 10, 11 13 01 02,03,06, 07,08,10 160 ns tsIAi(RD) 9, 10, 11 14 thIA(PC) 9, 10, 11 15 145 04 95 05, 09 70 All 0 ns 01 100 ns 02,06,10 40 03,07,08 30 04 20 05, 09 15 tsCEL(WR) 9, 10, 11 16 All 0 ns thCE(WR) 9, 10, 11 17 All 0 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits 9, 10, 11 18 01 70 02,06,10 60 Min CE high to WR setup time CE low to RD setup time 5/ CE to RD hold time 5/ CE high to RD setup time 5/ RD low width 5/ RD to read data active delay 2/ RD to read data not valid delay 2/ RD to read data valid delay RD to read data float delay 2/ 6/ tsCEh(WR) See figure 3, read and write, interrupt, reset, and cycle timings. CL = 50 pF 10% VCC = 4.5 V 03,07,08 50 04 40 Unit Max ns 05, 09 30 tsCEL(RD) 9, 10, 11 19 All 0 ns thCE(RD) 9, 10, 11 20 All 0 ns tsCEh(RD) 9, 10, 11 21 01 70 ns 02,06,10 60 twRDL 9, 10, 11 22 03,07,08 50 04 40 05, 09 30 01 200 02,06,10 150 03,07,08 125 04 90 ns 05, 09 75 tdRD(DRA) 9, 10, 11 23 All 0 ns tdRDr(DR) 9, 10, 11 24 All 0 ns tdRDf(DR) 9, 10, 11 25 01 180 02,06,10 140 03,07,08 125 04 90 tdRD(DRZ) 9, 10, 11 26 05, 09 70 01 45 02,06,10 40 03,07,08 35 09 30 04 25 05 20 ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type 9, 10, 11 27 01 Limits Min Address required valid to read data valid delay tdA(DR) See figure 3, read and write, interrupt, reset, and cycle timings. CL = 50 pF 10% VCC = 4.5 V WR low width WR to write data valid WRITE data to WR hold time WR to wait valid delay 7/ RD to wait valid delay 7/ WR to W/REQ not valid delay tsDW(WR) 9, 10, 11 9, 10, 11 28 29 Max 280 02,06,10 220 07 180 03, 08 160 04 120 05, 09 twWRL Unit 100 01 200 02,06,10 150 03,07,08 125 04 90 05, 09 75 ns 03,06,07 35 04 05,08,09, 10 25 01, 02 0 9, 10, 11 30 All tdWR(W) 9, 10, 11 31 01 200 02,06,10 170 tdWRf(REQ) 9, 10, 11 9, 10, 11 32 33 ns 20 thDW(WR) tdRD(W) ns 0 ns 07 160 03, 08 100 04 70 05, 09 50 01 200 02,06,10 170 07 160 03, 08 100 04 70 05, 09 50 01 200 02,06,10 170 07 160 03, 08 120 04 100 05, 09 70 ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 9 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type 9, 10, 11 34 01 Limits Min RD to W/REQ not valid delay WR to DTR/REQ not valid delay WR to DTR/REQ not valid delay RD to DTR/REQ not valid delay PCLK to INT valid delay 7/ tdRDf(REQ) See figure 3, read and write, interrupt, reset, and cycle timings. CL = 50 pF 10% VCC = 4.5 V RD (acknowledge) width Max 200 02,06,10 170 07 160 03, 08 120 04 100 ns 05, 09 70 tdWRr(REQ) 9, 10, 11 35 All 4.0 tcPC ns tdWRr(EREQ) 8/ 9, 10, 11 35 03,06,08, 10 120 ns 04 100 05, 09 70 tdRDr(REQ) 9, 10, 11 36 All 4.0 tcPC ns tdPC(INT) 9, 10, 11 37 01,02,06, 07, 10 500 ns 03 400 04 350 08 320 05, 09 INTACK to RD (acknowledge) delay 9/ Unit tdIAi(RD) twRDA 9, 10, 11 9, 10, 11 38 39 175 01 200 02,06,10 150 03,07,08 125 04 95 05, 09 50 01 200 02,06,10 150 03,07,08 125 04 95 05, 09 75 ns ns See footnotes at end of table. ANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 10 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits 9, 10, 11 40 01 180 02,03,06, 07,08,10 140 04 90 Min RD (acknowledge) to read data valid delay tdRDA(DR) See figure 3, read and write, interrupt, reset, and cycle timings. CL = 50 pF 10% VCC = 4.5 V 05, 09 IEI to RD (acknowledge) setup time IEI to RD (acknowledge) hold time IEI to IEO delay time PCLK to IEO delay RD to INT inactive delay 7/ RD to WR delay for no reset 2/ WR to RD delay for no reset 2/ tsIEI(RDA) 9, 10, 11 41 Max 100 02,03,06, 07,08,10 95 04 65 ns 05, 09 50 9, 10, 11 42 All 0 tdIEI(IEO) 9, 10, 11 43 01 02,03,06, 07,08,10 100 04 65 tdRA(INT) 9, 10, 11 9, 10, 11 44 45 tdRD(WRQ) 9, 10, 11 46 tdWRQ(RD) 9, 10, 11 47 ns ns 95 05, 09 45 01 02,03,06, 07 250 08 175 04 130 05, 09 01,02,06, 07 500 03, 10 450 08 320 04 260 05, 09 01,02,03, 06,07,08, 10 ns 70 01 thIEI(RDA) tdPC(IEO) Unit ns 200 80 ns 200 15 04,05,09 10 01 30 02,03,06, 07,08,10 15 04,05,09 10 ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 11 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits 9, 10, 11 48 01 200 02,03,06, 10 150 07, 08 100 04 85 05, 09 01,02,06, 07,08,09, 10 4.0 tcPC Min WR and RD coincident low for reset 2/ Valid access recovery time 2/ 10/ twRES See figure 3, read and write, interrupt, reset, and cycle timings. CL = 50 pF 10% VCC = 4.5 V trC 9, 10, 11 49 03,04,05 PCLK to W/REQ valid delay PCLK to wait inactive delay tdPC(REQ) See figure 3, general timings. CL = 50 pF 10% VCC = 4.5 V tdPC(W) 9, 10, 11 9, 10, 11 1 2 RxC to PCLK setup time (PCLK / 4 case only) 11/ 12/ RxD to RxC setup time (X1 mode) 11/ RxD to RxC hold time (X1 mode) 11/ RxD to RxC setup time (X1 mode) 11/ 13/ 9, 10, 11 3 Max ns 75 ns 3.5 tcPC 01,02,06, 07, 10 250 03, 08 150 04 120 05, 09 01,02,06, 07, 10 350 03, 08 250 04 220 ns 80 05, 09 tsRXC(PC) Unit ns 180 01 70 twPCL 02, 06 60 twPCL 07 40 twPCL 03,04,05, 08,09,10 0 ns tsRXD(RXCr) 9, 10, 11 4 All 0 ns thRXD(RXCf) 9, 10, 11 5 01,02,06, 07, 10 150 ns 03, 08 125 04 100 05, 09 50 All 0 tsRXD(RXCf) 9, 10, 11 6 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 12 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits 9, 10, 11 7 01,02,06, 07, 10 150 03, 08 125 04 100 05, 09 01,02,06, 07, 10 -200 03, 08 -150 04 -125 05, 09 ns ns Min RxD to RxC hold time (X1 mode) 11/ 13/ SYNC to RxC setup time 11/ SYNC to RxC hold time 11/ TxC to PCLK setup time 12/ 14/ TxC to TxD 14/ delay (X1 mode) TxC to TxD delay (X1 mode) 13/ 14/ thRXD(RXCf) See figure 3, general timings. CL = 50 pF 10% VCC = 4.5 V tsSY(RXC) 8 ns 50 ns thSY(RXC) 9, 10, 11 9 All tsTXC(PC) 9, 10, 11 10 All 0 tdTXCf(TXD) 9, 10, 11 11 01 230 02, 06 200 10 190 tdTXCr(TXD) 9, 10, 11 9, 10, 11 12 13 03,07,08 150 04 130 05, 09 80 01 230 02, 06 200 10 190 03,07,08 150 04 130 05, 09 01,02,06, 07, 10 80 200 03, 08 140 04 120 05, 09 RTxC high width 15/ Max -100 5.0 tcPC tdTXD(TRX) TxD to TRxC delay (send clock echo) 9, 10, 11 twRTxh 9, 10, 11 14 Unit ns ns ns 80 01 180 02,06,07 150 10 130 03, 08 120 04 100 05, 09 80 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 13 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits 9, 10, 11 15 01 180 02,06,07 150 Min RTxC low width 15/ RTxC cycle time (RxD, TxD) 15/ 16/ Crystal oscillator period 4/ 17/ TRxC high width 15/ TRxC low width 15/ TRxC cycle time 15/ 16/ twRTxl See figure 3, general timings. CL = 50 pF 10% VCC = 4.5 V tcRTX tcRTXX twTRXh twTRXl tcTRX 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 16 17 18 19 20 10 130 03, 08 120 04 100 05, 09 80 01 640 02, 06 500 10 472 Max ns ns 03,07,08 400 04 320 05, 09 244 01 165 1000 02,06,10 125 1000 03,07,08 100 1000 04 80 1000 05, 09 62 1000 01 180 02,06,07 150 10 130 03, 08 120 04 100 05, 09 80 01 180 02,06,07 150 10 130 03, 08 120 04 100 05, 09 80 01 640 02, 06 500 10 472 03,07,08 400 04 320 05, 09 244 Unit ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 14 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits 9, 10, 11 21 01,02,06, 07, 10 200 03, 08 120 04 100 05, 09 01,02,06, 07,10 200 03, 08 120 Min twEXT DCD to CTS pulse width See figure 3, general timings. CL = 50 pF 10% VCC = 4.5 V twSY SYNC pulse width RxC to W/REQ valid delay 2/ 11/ 18/ RxC to wait inactive delay 2/ 7/ 11/ 18/ RxC to SYNC valid delay RxC to INT valid delay 2/ 7/ 11/ 18/ TxC to W/REQ valid delay 2/ 14/ 18/ TxC to wait inactive delay 2/ 7/ 14/ 18/ TxC to DTR/REQ valid delay 2/ 14/ 18/ TxC to DTR/REQ valid delay 2/ 8/ 14/ 18/ tdRXC(REQ) 9, 10, 11 See figure 3, system timings. CL = 50 pF 10% VCC = 4.5 V tdRXC(W) tdRXC(SY) tdRXC(INT) tdTXC(REQ) tdTXC(W) tdTXC(DRQ) tdTXC(EDRQ) 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 22 1 2 3 4 5 6 7 7a Unit Max ns 70 ns 04 100 05, 09 70 08,09,10 13 17 01,02,03, 04,05,06, 07 8 12 08,09,10 13 17 01,02,03, 04,05,06, 07 8 14 08,09,10 01,02,03, 04,05,06, 07 9 12 4 7 08,09,10 01,02,03, 04,05,06, 07 15 21 10 16 08,09,10 8 11 01,02,03, 04,05,06, 07 5 8 08,09,10 8 14 01,02,03, 04,05,06, 07 5 11 08,09,10 7 10 01,02,03, 04,05,06, 07 4 7 08,09,10 9 12 03,04,05, 06 5 8 tcPC tcPC tcPC tcPC tcPC tcPC tcPC tcPC See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 15 TABLE I. Electrical performance characteristics - Continued. Test Symbol TxC to INT valid delay 2/ 7/ 14/ 18/ SYNC transition to INT valid delay 2/ 7/ 18/ DCD or CTS transition to INT valid delay 2/ 7/ 18/ tdTXC(INT) Conditions 1/ -55C TC +125C VCC = 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Min Max 9, 10, 11 8 08,09,10 9 13 01,02,03, 04,05,06, 07 6 10 See figure 3, system timings. CL = 50 pF 10% VCC = 4.5 V Limits Unit tcPC tdSY(INT) 9, 10, 11 9 All 2 6 tcPC tdEXT(INT) 9, 10, 11 10 10 3 8 tcPC 01,02,03, 04,05,06, 07,08,09 2 6 1/ All tests must be performed under the worst case conditions. 2/ Guaranteed to the limit specified herein if not tested. 3/ For device types 03, 04, 05, and 06, clock rise and fall times are controlled at approximately 5 ns by the tester. 4/ Tested in interrupt acknowledge cycle only. 5/ Parameter does not apply to interrupt acknowledge transactions. 6/ Float delay is defined as the time required for a 0.5 V change in the output with a maximum dc load and minimum ac load. 7/ Open-drain output, measured with open-drain test load. 8/ Applies to versions with SDLC enhancements only. 9/ Parameter is system dependent. For any SCC in the daisy chain, tdIAi(RD) must be greater than the sum of tdPC(IEO) for the highest priority device in the daisy chain, tsIEI(RDA) for the SCC, and tdIEIf(IEO) for each device seperating them in the daisy chain. 10/ Parameter applies only between transactions involving the SCC. 11/ RxC is RTxC or TRxC, whichever is supplying the receive clock. 12/ Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and PCLK or TxC and PCLK is required. 13/ Parameter applies only to FM encoding/decoding. 14/ TxC is TRxC or RTxC, whichever is supplying the transmit clock. 15/ Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to chip PCLK requirements. 16/ The maximum receive or transmit data is one-fourth PCLK. 17/ Both RTxC and SYNC have 30 pF capacitors to ground connected to them. 18/ The value of this parameter is dependent on PCLK cycle time. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 16 Device type Case outline Terminal number Terminal symbol All Q Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D1 D3 D5 D7 INT IEO IEI INTACK VCC W/REQA SYNCA RTxCA RxDA TRxCA TxDA DTR/REQA RTSA CTSA DCDA PCLK 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DCDB CTSB RTSB DTR/REQB TxDB TRxCB RxDB RTxCB SYNCB W/REQB GND D/C CE A/B WR RD D6 D4 D2 D0 Device type Case outlines Terminal number Terminal symbol All Y and X 1/ Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 D0 D1 D3 D5 D7 INT IEO IEI INTACK VCC W/REQA SYNCA RTxCA RxDA TRxCA TxDA NC NC DTR/REQA RTSA CTSA DCDA 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PCLK DCDB CTSB RTSB DTR/REQB NC TxDB TRxCB RxDB RTxCB SYNCB W/REQB GND NC D/C CE A/B WR RD D6 D4 D2 1/ Case X is applicable to device type 07 only. NC = No connection. FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 17 FIGURE 2. Block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 18 FIGURE 3. Timing waveforms and test circuits. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 19 FIGURE 3. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 20 FIGURE 3. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 21 FIGURE 3. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 22 Device types 01, 02, 07, 08, 09, 10 Switching test circuits AC testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0". FIGURE 3. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 23 Device types 03, 04, 05, 06 Switching test circuits AC testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0". FIGURE 3. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 24 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Interim electrical parameters (method 5004) Final electrical test parameters (method 5004) Group A test requirements (method 5005) Groups C and D end-point electrical parameters (method 5005) Subgroups (in accordance with MIL-STD-883, method 5005, table I) ---1*, 2, 3, 7, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3 * PDA applies to subgroup 1. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN, COUT, and CI/O measurements) shall be measured only for the initial test and after process or design changes which may affect input capacitance. A minimum sample size of five devices with zero rejects is required. d. Subgroups 7 and 8 shall verify the functionality of the device. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 25 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614) 692-0547. 6.6 Pin descriptions. A/B Channel A/channel B select (input). This signal selects the channel in which the read or write operation occurs. CE Chip enable (input, active low). This signal selects the SCC for a read or write operation. CTSA, CTSB Clear to send (inputs, active low). If these pins are programmed as auto enables, a low on the inputs enables the respective transmitters. If not programmed as auto enables, they may be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow rise time inputs. The SCC detects pulses on these inputs and can interrupt the CPU on both logic level transitions. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 26 6.6 Pin descriptions - Continued. D/C Data/control select (input). This signal defines the type of information transferred to or from the SCC. A high means data is transferred, a low indicates a command. DCDA, DCDB Data carrier detect (inputs, active low). These pins function as receiver enables if they are programmed for auto enables; otherwise they may be used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommodate slow rise time signals. The SCC detects pulses on these pins and can interrupt the CPU on both logic level transitions. D0-D7 Data bus (bidirectional, three-state). These lines carry data and commands to and from the SCC. DTR/REQA, DTR/REQB Data terminal ready/request (outputs, active low). These outputs follow the state programmed into the DTR bit. They can also be used as general purpose outputs or as request lines for a DMA controller. IEI Interrupt enable in (input, active high). IEI is used with IEO to form an interrupt daisy chain when there is more than one interrupt driven device. A high IEI indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. IEO Interrupt enable out (output, active high). IEO is high only if IEI is high and the CPU is not servicing an SCC interrupt or the SCC is not requesting an interrupt (interrupt acknowledge cycle only). IEO is connected to the next lower priority device's IEI input and thus inhibits interrupts from lower priority devices. INT Interrupt request (output, open-drain, active low). This signal is activated when the SCC requests an interrupt. INTACK Interrupt acknowledge (input, active low). This signal indicates an active interrupt acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD becomes active, the SCC places an interrupt vector on the data bus (if IEI is high). INTACK is latched by the rising edge of PCLK. PCLK Clock (input). This is the master SCC clock used to synchronize internal signals. PCLK is a TTL level signal. PCLK is not required to have any phase relationship with the master system clock. RD Read (input, active low). This signal indicates a read operation and when the SCC is selected, enables the SCC's bus drivers. During the interrupt acknowledge cycle, this signal gates the interrupt vector onto the bus if the SCC is the highest priority device requesting an interrupt. RxDA, RxDB Receive data (inputs, active high). These input signals receive serial data at standard TTL levels. RTxCA, RTxCB Receive/transmit clocks (inputs, active low). These pins can be programmed in several different modes of operation. In each channel, RTxC may supply the receive clock, the transmit clock, the clock for the baud rate generator, or the clock for the digital phase-locked loop. These pins can also be programmed for use with the respective SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous modes. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 27 6.6 Pin descriptions - Continued. RTSA, RTSB Request to send (outputs, active low). When the request to send (RTS) bit in write register 5 is set, the RTS signal goes low. When the RTS bit is reset in the asynchronous mode and auto enable is on, the signal goes high after the transmitter is empty. In synchronous mode or in asynchronous mode with auto enable off, the RTS pin strictly follows the state of the RTS bit. Both pins can be used as general purpose outputs. SYNCA, SYNCB Synchronization (inputs or outputs, active low). These pins can act either as inputs, outputs, or part of the crystal oscillator circuit. In the asynchronous receive mode (crystal oscillator option not selected), these pins are inputs similar to CTS and DCD. In this mode, transitions on these lines affect the state of the synchronous/hunt status bits in read register 0 but have no other function. In external synchronization mode with the crystal oscillator not selected, these lines also act as inputs. In this mode, SYNC must be driven low two receive clock cycles after the last bit in the synchronous character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of SYNC. In the internal synchronization mode (monosync and bisync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which synchronous characters are recognized. The synchronous condition is not latched, so these outputs are active each time a synchronization pattern is recognized (regardless of character boundaries). In SDLC mode, these pins act as outputs and are valid on receipt of a flag. TxDA, TxDB Transmit data (outputs, active high). These output signals transmit serial data at standard TTL levels. TRxCA, TRxCB Transmit/receive clocks (inputs or outputs, active low). These pins can be programmed in several different modes of operation. TRxC may supply the receive clock or the transmit clock in the input mode or supply the output of the digital phase-locked loop, the crystal oscillator, the baud rate generator, or the transmit clock in the output mode. WR Write (input, active low). When the SCC is selected, this signal indicates a write operation. The coincidence of RD and WR is interpreted as a reset. W/REQA, W/REQB Wait/request (outputs, open-drain when programmed for a wait function, driven high or low when programmed for a request function). These dual-purpose outputs may be programmed as request lines for a DMA controller or as wait lines to synchronize the CPU to the SCC data rate. The reset state is wait. 6.7 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103 and QML-38535. The vendors listed in MIL-HDBK-103 and QML-38535 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88689 A REVISION LEVEL C SHEET 28 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 02-12-18 Approved sources of supply for SMD 5962-88689 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-8868901QA 5962-8868901YA 0C7V7 0C7V7 Z85C3006CMB Z85C3006LMB 5962-8868902QA 5962-8868902YA 0C7V7 0C7V7 Z85C3008CMB Z85C3008LMB 5962-8868903QX 5962-8868903YX 3/ 3/ AM85C30-10/BQA AM85C30-10/BUA 5962-8868904QX 5962-8868904YX 3/ 3/ AM85C30-12/BQA AM85C30-12/BUA 5962-8868905QX 5962-8868905YX 3/ 3/ AM85C30-16/BQA AM85C30-16/BUA 5962-8868906QX 5962-8868906YX 3/ 3/ AM85C30-8/BQA AM85C30-8/BUA 5962-8868907QA 5962-8868907XA 5962-8868907YA 0C7V7 0C7V7 0C7V7 Z85C3010CMB Z85C3010NMB Z85C3010LMB 5962-8868908QA 5962-8868908YA 0C7V7 0C7V7 Z8523010CMB Z8523010LMB 5962-8868909QA 5962-8868909YA 0C7V7 0C7V7 Z8523016CMB Z8523016LMB 5962-88689010QA 5962-88689010YA 0C7V7 0C7V7 Z8523008CMB Z8523008LMB See footnotes on next page. 1 of 2 STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source of supply. Vendor CAGE number Vendor name and address 0C7V7 Qualified Parts Laboratory, Inc. 3605 Kifer Road Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. 2 of 2