Ultrafast SiGe
ECL Clock/Data Buffers
ADCLK905/ADCLK907/ADCLK925
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
95 ps propagation delay
7.5 GHz toggle rate
60 ps typical output rise/fall
60 fs random jitter (RJ)
On-chip terminations at both input pins
Extended industrial temperature range: −40°C to +125°C
2.5 V to 3.3 V power supply (VCC − VEE)
APPLICATIONS
Clock and data signal restoration and level shifting
Automated test equipment (ATE)
High speed instrumentation
High speed line receivers
Threshold detection
Converter clocking
GENERAL DESCRIPTION
The ADCLK905 (one input, one output), ADCLK907 (dual one
input, one output), and ADCLK925 (one input, two outputs) are
ultrafast clock/data buffers fabricated on the Analog Devices, Inc.,
proprietary XFCB3 silicon germanium (SiGe) bipolar process.
The ADCLK905/ADCLK907/ADCLK925 feature full-swing
emitter coupled logic (ECL) output drivers. For PECL (positive
ECL) operation, bias VCC to the positive supply and VEE to ground.
For NECL (negative ECL) operation, bias VCC to ground and
VEE to the negative supply.
The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate,
10 Gbps data rate, and 60 fs random jitter (RJ).
The inputs have center tapped, 100 Ω, on-chip termination
resistors. A VREF pin is available for biasing ac-coupled inputs.
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total
differential output swing of 1.6 V.
The ADCLK905/ADCLK907/ADCLK925 are available in
16-lead LFCSP packages.
TYPICAL APPLICATION CIRCUITS
D
D
Q
VCC
VEE
VT
Q
VREF
06318-001
Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer
D1
D1
Q1
V
CC
V
EE
V
T
1
Q1
V
REF
1
D2 Q2
V
CC
V
EE
V
T
2
D2
V
REF
2
Q2
06318-002
Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer
D
D
V
CC
V
EE
V
T
V
REF
Q1
Q1
Q2
Q2
06318-003
Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Circuits........................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ..............................................8
Applications Information.............................................................. 11
Power/Ground Layout and Bypassing..................................... 11
Output Stages ............................................................................... 11
Optimizing High Speed Performance ..................................... 11
Buffer Random Jitter.................................................................. 11
Typical Application Circuits ......................................................... 12
Evaluation Board Schematic ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
8/07—Revision 0: Initial Version
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min) and maximum (Max) values are
given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +125°C variation, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Conditions
DC INPUT CHARACTERISTICS
Input Voltage High Level VIH V
EE + 1.6 VCC V
Input Voltage Low Level VIL V
EE V
CC − 0.7 V
Input Differential Range VID 0.2 3.4 V p-p −40°C to +85°C
(±1.7 V between input pins)
V
ID 0.2 2.8 V p-p 85°C to 125°C
(±1.4 V between input pins)
Input Capacitance CIN 0.4 pF
Input Resistance, Single-Ended Mode 50 Ω
Input Resistance, Differential Mode 100 Ω
Input Resistance, Common Mode 50 kΩ Open VT
Input Bias Current 20 μA
DC OUTPUT CHARACTERISTICS
Output Voltage High Level VOH V
CC − 1.26 VCC − 0.76 V 50 Ω to (VCC − 2.0 V)
Output Voltage Low Level VOL V
CC − 1.99 VCC − 1.54 V 50 Ω to (VCC − 2.0 V)
Output Voltage Differential VOD 610 1040 mV 50 Ω to (VCC − 2.0 V)
Reference Voltage VREF
Output Voltage (VCC + 1)/2 V −500 μA to +500 μA
Output Resistance 250 Ω
AC PERFORMANCE
Propagation Delay tPD 70 95 125 ps VCC = 3.3 V ± 10%,
VICM = VREF, VID = 0.5 V p-p
70 95 125 ps VCC = 2.5 V ± 5%,
VICM = V REF, VID = 0.5 V p-p
Propagation Delay Temperature Coefficient 50 fs/°C
Propagation Delay Skew (Output to Output)
ADCLK907
15 ps VID = 0.5 V
Propagation Delay Skew (Output to Output)
ADCLK925
10 ps VID = 0.5 V
Propagation Delay Skew (Device to Device) 35 ps VID = 0.5 V
Toggle Rate 6 7.5 GHz >0.8 V differential output swing,
VCC = 3.3 V ± 10%
6.5 GHz >0.8 V differential output swing,
VCC = 2.5 V ± 5%
Random Jitter RJ 60 fs rms VID = 1600 mV, 8 V/ns, VICM = 1.85 V
Rise/Fall Time tR/tF 30 85 ps 20%/80%
Additive Phase Noise
622.08 MHz −138 dBc/Hz @10 Hz offset
−144 dBc/Hz @100 Hz offset
−152 dBc/Hz @1 kHz offset
−159 dBc/Hz @10 kHz offset
−161 dBc/Hz @100 kHz offset
−161 dBc/Hz >1 MHz offset
122.88 MHz −135 dBc/Hz @10 Hz offset
−145 dBc/Hz @100 Hz offset
−153 dBc/Hz @1 kHz offset
−160 dBc/Hz @10 kHz offset
−161 dBc/Hz @100 kHz offset
−161 dBc/Hz >1 MHz offset
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 4 of 16
Parameter Symbol Min Typ Max Unit Conditions
POWER SUPPLY
Supply Voltage Requirement VCC − VEE 2.375 3.63 V 2.5 V − 5% to 3.3 V + 10%
Power Supply Current Static
ADCLK905
Negative Supply Current IVEE 24 mA VCC − VEE = 2.5 V
25 40 mA
VCC − VEE = 3.3 V ± 10%
Positive Supply Current IVCC 47 mA VCC − VEE = 2.5 V
48 63 mA
VCC − VEE = 3.3 V ± 10%
ADCLK907
Negative Supply Current IVEE 48 mA VCC − VEE = 2.5 V
50 80 mA
VCC − VEE = 3.3 V ± 10%
Positive Supply Current IVCC 94 mA VCC − VEE = 2.5 V
96 126 mA
VCC − VEE = 3.3 V ± 10%
ADCLK925
Negative Supply Current IVEE 29 mA VCC − VEE = 2.5 V
31 51 mA
VCC − VEE = 3.3 V ± 10%
Positive Supply Current IVCC 76 mA VCC − VEE = 2.5 V
77 97 mA
VCC − VEE = 3.3 V ± 10%
Power Supply Rejection1PSRVCC 3 ps/V VCC − VEE = 3.0 V ± 20%
Output Swing Supply Rejection2PSRVCC 26 dB VCC − VEE = 3.0 V ± 20%
1 Change in TPD per change in VCC.
2 Change in output swing per change in VCC.
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage
VCC − VEE 6.0 V
Input Voltage
D (D1, D2), D (D1, D2) VEE − 0.5 V to
VCC + 0.5 V
D1, D2, D1, D2 to VT Pin
(CML or PECL Termination)
±40 mA
D (D1, D2) to D (D1, D2) ±1.8 V
Maximum Voltage on Output Pins VCC + 0.5 V
Maximum Output Current 35 mA
Input Termination, VT to D (D1, D2), D (D1, D2) ±2 V
Voltage Reference, VREF V
CC − VEE
Temperature
Operating Temperature Range, Ambient −40°C to +125°C
Operating Temperature, Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
16-lead LFCSP 70 °C/W
ESD CAUTION
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC = NO CONNECT
1D
2D
3NC
4NC
11 Q
12 Q
10 NC
9NC
5
NC
6
NC
7
V
EE
8
V
CC
15 V
REF
16 V
T
14 V
EE
13 V
CC
ADCLK905
TOP VIEW
(Not to Scale)
06318-004
Figure 4. ADCLK905 Pin Configuration
Table 4. Pin Function Descriptions for 1:1 ADCLK905 Buffer
Pin No. Mnemonic Description
1 D Noninverting Input.
2 DInverting Input.
3, 4, 5, 6,
9, 10
NC No Connect. No physical connection to the die.
7, 14 VEE Negative Supply Voltage.
8, 13 VCC Positive Supply Voltage.
11 QInverting Output.
12 Q Noninverting Output.
15 VREF Reference Voltage. Reference voltage for biasing ac-coupled inputs.
16 VT Center Tap. Center tap of 100 Ω input resistor.
Heat Sink NC No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit.
It can be left floating for optimal electrical isolation between the package handle and the substrate of the die.
It can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance
to vias and other components.
PIN 1
INDICATOR
1D1
2D1
3D2
4D2
11 Q1
12 Q1
10 Q2
9Q2
5
V
T
2
6
V
REF
2
7
V
EE
8
V
CC
15 V
REF
1
16 V
T
1
14 V
EE
13 V
CC
ADCLK907
TOP VIEW
(Not to Scale)
06318-005
Figure 5. ADCLK907 Pin Configuration
Table 5. Pin Function Descriptions for Dual 1:1 ADCLK907 Buffer
Pin No. Mnemonic Description
1 D1 Noninverting Input 1.
2 D1 Inverting Input 1.
3 D2 Noninverting Input 2.
4 D2 Inverting Input 2.
5 VT2 Center Tap 2. Center tap of 100 Ω input resistor, Channel 2.
6 VREF2 Reference Voltage 2. Reference voltage for biasing ac-coupled inputs, Channel 2.
7, 14 VEE Negative Supply Voltage.
8, 13 VCC Positive Supply Voltage. Pin 8 and Pin 13 are not strapped internally.
9 Q2 Inverting Output 2.
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 7 of 16
Pin No. Mnemonic Description
10 Q2 Noninverting Output 2.
11 Q1 Inverting Output 1.
12 Q1 Noninverting Output 1.
15 VREF1 Reference Voltage 1. Reference voltage for biasing ac-coupled inputs, Channel 1.
16 VT1 Center Tap 1. Center tap of 100 Ω input resistor, Channel 1.
Heat Sink NC No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit.
It can be left floating for optimal electrical isolation between the package handle and the substrate of the die.
It can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance
to vias and other components.
PIN 1
INDICATOR
NC = NO CONNECT
1D
2D
3NC
4NC
11 Q1
12 Q1
10 Q2
9Q2
5
NC
6
NC
7
V
EE
8
V
CC
15 V
REF
16 V
T
14 V
EE
13 V
CC
ADCLK925
TOP VIEW
(Not to Scale)
06318-006
Figure 6. ADCLK925 Pin Configuration
Table 6. Pin Function Descriptions for 1:2 ADCLK925 Buffer
Pin No. Mnemonic Description
1 D Noninverting Input.
2 DInverting Input.
3, 4, 5, 6 NC No Connect. No physical connection to the die.
7, 14 VEE Negative Supply Voltage.
8, 13 VCC Positive Supply Voltage.
9 Q2 Inverting Output 2.
10 Q2 Noninverting Output 2.
11 Q1 Inverting Output 1.
12 Q1 Noninverting Output 1.
15 VREF Reference Voltage. Reference voltage for biasing ac-coupled inputs.
16 VT Center Tap. Center tap of 100 Ω input resistor.
Heat Sink NC No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit.
It can be left floating for optimal electrical isolation between the package handle and the substrate of the die.
It can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance
to vias and other components.
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0.0 V, TA = 25°C, outputs terminated 50 Ω to VCC − 2 V, unless otherwise noted.
06318-007
Q
Q
1.37V
200ps/DIV
100mV/DI
V
2.37V
Figure 7. Output Waveform, VCC = 3.3 V
–
90
–100
–110
–120
–130
–140
–150
–160
–17010 100 1k 10k 100k 1M 10M 100M
06318-008
f (Hz)
L[f] (dBc/Hz)
AGILENT E5500
CARRIER: 122.88MHz
NO SPURS
Figure 8. Phase Noise at 122.88 MHz
–
90
–100
–110
–120
–130
–140
–150
–160
–170
10 100 1k 10k 100k 1M 10M 100M
0
6318-009
f (Hz)
L[f] (dBc/Hz)
AGILENT E5500
CARRIER: 245.76MHz
NO SPURS
Figure 9. Phase Noise at 245.76 MHz
06318-010
Q
Q
100ps/DIV
100mV/DI
V
1.37V
2.37V
Figure 10. Output Waveform, VCC = 3.3 V
–
90
–100
–110
–120
–130
–140
–150
–160
–17010 100 1k 10k 100k 1M 10M 100M
06318-011
f (Hz)
L[f] (dBc/Hz)
AGILENT E5500
CARRIER: 622.08MHz
NO SPURS
Figure 11. Phase Noise at 622.08 MHz
0
50
100
150
200
250
300
012345678
0
6318-012
INPUT SLEW RATE (V/ns)
RMS JITTER (fs)
Figure 12. RMS Jitter vs. Input Slew Rate
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 9 of 16
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1234
–55°C
+25°C
+125°C
0
6318-013
SUPPLY VOLTAGE (V)
OUTPUT SWING (V)
Figure 13. VOD vs. Power Supply Voltage
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
3.0 3.52.5 4.0
06318-014
POWER SUPPLY VOLTAGE (V)
POWER SUP P LY CURRENT ( A)
–55°C
+25°C
+125°C
–55°C
+25°C
+125°C
Figure 14. Power Supply Current vs. Power Supply Voltage, ADCLK905
–55°C
+25°C
+125°C
90
95
100
105
110
1.6 2.1 2.6 3.1 3.6
06318-015
INPUT CO MM O N MO DE (V)
PROP AGATION D EL AY
(ps)
Figure 15. Propagation Delay vs. VICM; Input Swing = 200 mV
01234
0
0.01
0.02
0.03
0.04
0.05
0.06
0.09
0.08
0.07
06318-016
SUPPLY VOLTAGE (V)
POWER SUP P LY CURRENT (A)
–55°C
+25°C
+125°C
+25°C
+125°C
–55°C
Figure 16. Power Supply Current vs. Supply Voltage, ADCLK925
94
95
96
97
98
99
100
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
06318-017
V
ID
(V)
tPD
(ps)
Figure 17. Propagation Delay vs. VID
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
06318-018
FREQUENCY (GHz)
V
OD
(V)
Figure 18. Toggle Rate, Differential Output Swing vs. Frequency
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 10 of 16
1
3
58ps/DIV
C4
2
06318-019
17ps/DIV
1
3
2
C4
06318-023
Figure 19. 2.488 Gbps PRBS 223 − 1 with OC-48/STM-16 Mask,
Measured p-p Jitter 8.1 ps, Source p-p Jitter 3.5 ps
Figure 22. 8.50 Gbps PRBS 223 − 1 with FC8500E ABS Beta Rx Mask,
Measured p-p Jitter 10.9 ps, Source p-p Jitter 4.4 ps
15ps/DIV
2
1
3
C4
06318-022
1
3
2
58ps/DIV
C4
06318-021
Figure 20. 9.95 Gbps PRBS 223 − 1 with OC-193/STM-64 Mask,
Measured p-p Jitter 10.5 ps, Source p-p Jitter 6.0 ps
Figure 23. 2.5 Gbps PRBS 223 − 1 with PCI Express 2.5 Rx Mask,
Measured p-p Jitter 8.1 ps, Source p-p Jitter 3.5 ps
34ps/DIV
1
3
C4
2
06318-020
1
3
2
29ps/DIV
C4
06318-024
Figure 21. 4.25 Gbps PRBS 223 − 1 with FC4250 (Optical) Mask,
Measured p-p Jitter 8.2 ps, Source p-p Jitter 3.4 ps Figure 24. 5.0 Gbps PRBS 223 − 1 with PCI Express 5.0 Rx Mask,
Measured p-p Jitter 8.7 ps, Source p-p Jitter 3.5 ps
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 11 of 16
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCLK905/ADCLK907/ADCLK925 buffers are designed
for very high speed applications. Consequently, high speed design
techniques must be used to achieve the specified performance.
It is critically important to use low impedance supply planes for
both the negative supply (VEE) and the positive supply (VCC) planes
as part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.
It is also important to adequately bypass the input and output
supplies. A 1 µF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.001 µF bypass capacitors
should be placed as close as possible to each of the VEE and VCC
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be strictly avoided to maximize the
effectiveness of the bypass at high frequencies.
OUTPUT STAGES
The specified performance can be achieved only by using proper
transmission line terminations. The outputs of the ADCLK905/
ADCLK907/ADCLK925 buffers are designed to directly drive
800 mV into 50 Ω cable or microstrip/stripline transmission
lines terminated with 50 Ω referenced to VCC − 2 V. The PECL
output stage is shown in Figure 25. The outputs are designed for
best transmission line matching. If high speed signals must be
routed more than a centimeter, either the microstrip or the
stripline technique is required to ensure proper transition times
and to prevent excessive output ringing and pulse width-
dependent propagation delay dispersion.
VEE
VCC
Q
Q
06318-025
Figure 25. Simplified Schematic Diagram of
the ADCLK905/ADCLK907/ADCLK925 PECL Output Stage
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed circuit, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and cause oscillation. Discontinuities along input and output
transmission lines can also severely limit the specified jitter
performance by reducing the effective input slew rate.
In a 50 Ω environment, input and output matching have a
significant impact on performance. The buffer provides internal
50 Ω termination resistors for both D and D inputs. The return
side should normally be connected to the reference pin provided.
The termination potential should be carefully bypassed, using
ceramic capacitors to prevent undesired aberrations on the
input signal due to parasitic inductance in the termination
return path. If the inputs are directly coupled to a source, care
must be taken to ensure the pins are within the rated input
differential and common-mode ranges.
If the return is floated, the device exhibits 100 cross termination,
but the source must then control the common-mode voltage
and supply the input bias currents.
There are ESD/clamp diodes between the input pins to prevent
the application of excessive offsets to the input transistors. ESD
diodes are not optimized for best ac performance. When a
clamp is desired, it is recommended that appropriate external
diodes be used.
BUFFER RANDOM JITTER
The ADCLK905/ADCLK907/ADCLK925 are specifically
designed to minimize added random jitter over a wide input
slew rate range. Provided sufficient voltage swing is present,
random jitter is affected most by the slew rate of the input signal.
Whenever possible, excessively large input signals should be
clamped with fast Schottky diodes because attenuators reduce
the slew rate. Input signal runs of more than a few centimeters
should be over low loss dielectrics or cables with good high
frequency characteristics.
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 12 of 16
TYPICAL APPLICATION CIRCUITS
V
REF
V
CC
V
T
D
D
06318-026
CONNECT V
T
TO V
CC
.
Figure 26. Interfacing to CML Inputs
V
REF
V
CC
–2V
V
T
D
D
06318-028
CONNECT V
T
TO V
CC
−2V.
Figure 27. Interfacing to PECL
V
REF
V
T
D
D
06318-029
NOTES
1. PLACING A BYPASS CAPACITOR
FROM V
T
TO GROUND CAN IMPROVE
THE NOISE PERFORMANCE.
CONNECT V
T
TO V
REF
.
Figure 28. AC Coupling Differential Signals
VREF
VT
D
D
06318-030
CONNECT VT,V
REF, AND D. PLACE A BYPASS
CAPACITOR FROM VTTO GROUND.
ALTERNATIVELY, VT,V
REF, AND D CAN BE
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180º PHASE SHIFT.
Figure 29. Interfacing to AC-Coupled Single-Ended Inputs
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 13 of 16
EVALUATION BOARD SCHEMATIC
0
6318-031
VAL
ADCLK9XX
D1
D1
D2
D2
VT2
Q2
Q2
Q1
Q1
PAD
VREF2
VEE_7
VCC_8
VCC_13
VEE_14
VREF1
VT1
LFCSP16-3X3
Solder bridges will be completed
by end user if desired.
0Ω resistors are NOT to be installed.
matched length ×2
VCC
VREF2
VREF1
matched lengths
matched length ×2
VT2
VT1
VEE
Jumpers are NOT to be installed.
Solder bridges will be completed
by end user if desired.
Solder bridges will be completed
by end user if desired.
0Ω resistors are NOT to be installed.
C45
.01UF
VCC
C44
.01UF
C12
.1U F
C11
.1U F C10
.1U F
C9
.1UF
C16
.1UF
C15
.1U F C26
.1U F
C14
.1UF C13
.1UF
C32
.1UF
C33
.1UF
C34
.1UF
C35
.1U F
C31
.1U F
C28
.1U F
C29
.1U F
C30
.1U F
C40
.1U F
C41
.1U F
C42
.1U F
C43
.1U F
C39
.1U F
C38
.1U F
C37
.1U F
C36
.1UF
C17
.1U F
C18
.1U F
C19
.1U F
C20
.1U F
C21
.1U F
C22
.1U F
C23
.1U F
C24
.1U F
C8
.1U F
C7
.1U F
C6
.1U F
C5
.1U F
C4
.1U F
C3
.1U F
C2
.1U F
C1
.1U F
C25
2.2UF
C27
2.2UF
Q2_ B
Q2
Q1_B
Q1
D2_B
D2
D1_B
D1
CAL_2
CAL_1
1
2
4
3
5
9
10
12
11
PAD
6
7
8
13
14
15
16
A1
VT1
R1
0
R2
0
12
JP7
0
12
JP1
0
VREF2VREF1
VT1
VREF2VT2
J12
J4
J3
J6
J5
J2
J1
J7
VREF2
VREF1
1
TP5
RED
1
TP4
BLK
1
TP3
RED
1
TP1
BLK
1
TP2
RED
VEE
VCC
VEE
1
TP8
RED
J8
J9J10
J11
VT2
VREF1VT1
12
JP2
0
12
JP3
0
12
JP4
0
12
JP5
0
12
JP6
0
12
JP8
0
1
TP6
RED
1
TP7
RED
VT2
VEE
VCC
VEE
Figure 30. Evaluation Board Schematic
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 14 of 16
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1
INDICATO
R
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATO
R
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
(BOTTOM VIEW)
*COMPLIANT
TO
JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 31. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADCLK905BCPZ-WP1−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 Y03
ADCLK905BCPZ-R71−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 Y03
ADCLK905BCPZ-R21−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 Y03
ADCLK907BCPZ-WP1−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 Y06
ADCLK907BCPZ-R71−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 Y06
ADCLK907BCPZ-R21−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 Y06
ADCLK925BCPZ-WP1−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 Y08
ADCLK925BCPZ-R71−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 Y08
ADCLK925BCPZ-R21−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 Y08
ADCLK905/PCBZ1 Evaluation Board
ADCLK907/PCBZ1 Evaluation Board
ADCLK925/PCBZ1 Evaluation Board
1 Z = RoHS Compliant Part.
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 15 of 16
NOTES
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 16 of 16
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06318-0-8/07(0)
